32-bit pipelined risc processor

13
-bit Pipelined RISC Proces Group 1 Group 1 aka “Go aka “Go Us” Us” Alice Wang Ann Ho Jason Fong CS m152b TA: Young Cho Lab section 1

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32-bit Pipelined RISC Processor. Group 1. aka “Go Us”. CS m152b TA: Young Cho Lab section 1. Alice Wang Ann Ho Jason Fong. IF/ID. ID/EX. EX/MEM. MEM/WB. Register File. PC Control. ALU. Data Memory. Instruction Memory. General Review of a Pipelined Processor. - PowerPoint PPT Presentation

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Page 1: 32-bit Pipelined RISC Processor

32-bit Pipelined RISC Processor

Group 1Group 1aka “Go Us”aka “Go Us”

Alice WangAnn HoJason Fong

CS m152bTA: Young ChoLab section 1

Page 2: 32-bit Pipelined RISC Processor

General Review of a Pipelined Processor

Instruction Memory

Register File ALU

Data Memory

PC Control

IF/ID ID/EX EX/MEM MEM/WB

Page 3: 32-bit Pipelined RISC Processor

Memory Controller Design

Design challenge: 32-bit processor with 16-bit memory interface• One every memory access, need to make two memory accesses in

order to get a 32-bit word out of a 16-bit memory interface.

Solution: Clock memory controller twice as fast as rest of processor• Effectively makes a memory access on the rising and falling edge of

the processor’s clock cycle• Each processor clock cycle corresponds to two clock cycles of the

memory controller• This allows two memory accesses per processor clock cycle

Page 4: 32-bit Pipelined RISC Processor

Instruction Format

31 28 27 25 24 22 21 19 8 4 3 0

31 28 27 25 24 22 15 0

31 28 15 0

R-type instruction

I-type instruction

J-type instruction

opcode rs rt rd shamt funct

opcode rs rt imm16

opcode imm16

Page 5: 32-bit Pipelined RISC Processor
Page 6: 32-bit Pipelined RISC Processor

Multiplier

0 • • • 3 2 - b i t v a l u e • • • 0 0 0 0 0 0 0 0 0 0 0

Page 7: 32-bit Pipelined RISC Processor

Parallel Multiplier(more efficient, but more hardware)

x4 x3 x2 x1 x0

y0

y1

y2

y3

y4

z9 z8 z7 z6 z5 z4 z3 z2 z1 z0

Page 8: 32-bit Pipelined RISC Processor

Data Forwarding

ID/EX EX/MEM MEM/WB

Forward From ALU output

Forward From memory output

Page 9: 32-bit Pipelined RISC Processor

Hardware NOP Insertion

1

IF/ID

PC Adder

NOP

Hold PC value

Insert NOP

Page 10: 32-bit Pipelined RISC Processor

Data Forwarding and Stall Insertions:Observed Results

Sample program: Bubble-sort 6 numbers

Assembler insertion of NOPs for data hazards and branch/jump delays

Machine code size: 66 words of memory

Execution time: ~750 clock cycles

Hardware data forwarding and stall insertion:

Machine code size: 35 words of memory

Execution time: ~400 clock cycles

Page 11: 32-bit Pipelined RISC Processor

Conclusion

Still cooking something up…

We conclude that we do not know what to conclude.

Page 12: 32-bit Pipelined RISC Processor

References

• Hennessey and Patterson, Computer Organization and Design (2nd Ed.), 1998, pages 476-495

• Donaldson, John L., “Pipeline Hazards”, http://occs.cs.oberlin.edu/faculty/jdonalds/317/lecture08.html

• Ercegovac, Intro To Digital Systems

Page 13: 32-bit Pipelined RISC Processor

• Add stuff about assembler