3-dimensional ics

8/7/2019 3-DIMENSIONAL ICs

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33--DIMENSIONAL ICsDIMENSIONAL ICs

Swetapadma MishraSwetapadma Mishra

Regd.no. 0701287035Regd.no. 0701287035

77thth semestersemester


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22--D ICSD ICS::

These are the ICs in which the inbuilt circuits are placed side byThese are the ICs in which the inbuilt circuits are placed side by

side, like the ones we usually use.side, like the ones we usually use.

33--D ICsD ICs::

In 3In 3--D ICs, vertical stacking of the layers of 2D ICs, vertical stacking of the layers of 2--D ICs is done.D ICs is done.

They extend Moores law and enables a new generation of tiny butThey extend Moores law and enables a new generation of tiny but

powerful devices.powerful devices.


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LIMITATIONS OFLIMITATIONS OF

EXISTING INTERCONNECTEXISTING INTERCONNECTTECHNOLOGIESTECHNOLOGIES


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Performances of deep sub micron ICs are limited by increasingPerformances of deep sub micron ICs are limited by increasinginterconnect loading effect.interconnect loading effect.

Long global clock networks account for the larger part of the powerLong global clock networks account for the larger part of the powerconsumption in chips.consumption in chips.

Capacitance and resistance of interconnects have increased due to theCapacitance and resistance of interconnects have increased due to thesmaller wire cross sections, smaller wire pitch and longer length. Thissmaller wire cross sections, smaller wire pitch and longer length. This

has resulted in increased RC delay.has resulted in increased RC delay.

As technology is advancing, scaling of interconnect is also increasing.As technology is advancing, scaling of interconnect is also increasing.In such scenario, increased RC delay is becoming major bottleneck inIn such scenario, increased RC delay is becoming major bottleneck inimproving performance of advanced ICs.improving performance of advanced ICs.

Increasing drive for the integration of disparate signals (digital,Increasing drive for the integration of disparate signals (digital,analog, RF) and technologies (SiGe, GaAs and so on) is introducinganalog, RF) and technologies (SiGe, GaAs and so on) is introducingvarious SoC design concepts, for which existing planner (2various SoC design concepts, for which existing planner (2--D) ICD) IC

design may not be suitable.design may not be suitable.


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LIMITATIONS OF Cu/LOWLIMITATIONS OF Cu/LOW

k INTERCONNECTSk INTERCONNECTS


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At submicron level of 250 nm, copper with lowAt submicron level of 250 nm, copper with low--k dielectric wask dielectric was

introduced to decrease affects of increasing interconnect delay. Butintroduced to decrease affects of increasing interconnect delay. But

below 130 nm technology node interconnect delays are increasingbelow 130 nm technology node interconnect delays are increasing

further despite introducing lowfurther despite introducing low--k dielectric.k dielectric.

As the scaling increases, new physical and technological effects likeAs the scaling increases, new physical and technological effects like

resistivityresistivity andand barrier thicknessbarrier thickness start dominating and interconnectstart dominating and interconnect

delay increases.delay increases.

Introduction of repeaters to shorten the interconnect length increasesIntroduction of repeaters to shorten the interconnect length increases

total area. The vias connecting repeaters to global layers can causetotal area. The vias connecting repeaters to global layers can cause

blockage in lower metal layers.blockage in lower metal layers.

Increasing metal layer width will cause increase in metallization layer.Increasing metal layer width will cause increase in metallization layer.

This cant be a solution for the problem as it increases complexity,This cant be a solution for the problem as it increases complexity,

reliability and cost.reliability and cost.


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Cu lowCu low--k dielectric films are deposited by a process known ask dielectric films are deposited by a process known asDamascene process.Damascene process.

Adhesion property of Cu with dielectric materials is very poor. UnderAdhesion property of Cu with dielectric materials is very poor. Underelectric bias, they drift easily and cause short between metal layers.electric bias, they drift easily and cause short between metal layers.

To avoid this problem, a barrier layer is deposited between dielectricTo avoid this problem, a barrier layer is deposited between dielectricand Cu trench.and Cu trench.

Even though it decreases effective cross section of interconnectsEven though it decreases effective cross section of interconnectscompared to drawn dimensions, it improves reliability. The barriercompared to drawn dimensions, it improves reliability. The barrierthickness becomes significant in deep submicron level and effectivethickness becomes significant in deep submicron level and effectiveresistance of the interconnect rises further.resistance of the interconnect rises further.

In addition to this increasing electron scattering and self heatingIn addition to this increasing electron scattering and self heatingcaused by the electron, flow in interconnects due to comparablecaused by the electron, flow in interconnects due to comparableincrease in internal chip temperature also contributes to increasedincrease in internal chip temperature also contributes to increased

interconnect resistance.interconnect resistance.


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MOTIVATIONS BEHINDMOTIVATIONS BEHIND

33--D ICSD ICS

Form factorForm factor

Increased electrical performancesIncreased electrical performances

Heterogeneous integrationHeterogeneous integration

Performance motivationPerformance motivationCost motivationCost motivation


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FORM FACTORFORM FACTOR ::

To increase density and achieve highest capacity to volume ratio.To increase density and achieve highest capacity to volume ratio.

INCREASED ELECTRICAL PERFORMANCESINCREASED ELECTRICAL PERFORMANCES ::For shorter interconnects, length and better electrical insulation.For shorter interconnects, length and better electrical insulation.

HETEROGENEOUS INTEGRATIONHETEROGENEOUS INTEGRATION ::

Integration of different functions (memory + logic + sensor + imagersIntegration of different functions (memory + logic + sensor + imagers+ different substrate materials + )+ different substrate materials + )

PERFORMANCE MOTIVATIONPERFORMANCE MOTIVATION ::

Wireless communication chips are used in power amplifiers inWireless communication chips are used in power amplifiers inwireless LAN and mobile applications. Future plans target highwireless LAN and mobile applications. Future plans target highperformance servers and supercomputer chips.performance servers and supercomputer chips.


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COST MOTIVATIONCOST MOTIVATION ::

Conventional cost reduction approaches have less cost than NANDConventional cost reduction approaches have less cost than NAND

flash memories and consider vertical stacking of memory cells on aflash memories and consider vertical stacking of memory cells on a

single Si wafer.single Si wafer.


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WHAT IS A 3DWHAT IS A 3D--IC?IC?


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Stacked 2D (Conventional) ICs


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FABRICATIONFABRICATION

TECHNOLOGIESTECHNOLOGIES


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Many options available for realization of 3DMany options available for realization of 3D

circuitscircuits

Choice of Fabrication depends onChoice of Fabrication depends on

requirements of Circuit Systemrequirements of Circuit System

BeamBeam

RecrystallizationRecrystallization

ProcessedWaferProcessedWafer

BondingBonding

Silicon EpitaxialSilicon Epitaxial

GrowthGrowth

Solid PhaseSolid Phase

CrystallizationCrystallization

Deposit polysillicon andDeposit polysillicon and

fabricate TFTsfabricate TFTs

--not practical for 3D circuitsnot practical for 3D circuits

due to high temp of meltingdue to high temp of melting

polysilliconpolysillicon

--Suffers from Low carrierSuffers from Low carrier

mobilitymobility

--However high performanceHowever high performance

TFTs have been fabricatedTFTs have been fabricated

using low temp processingusing low temp processing

which can be used towhich can be used to

implement 3D circuitsimplement 3D circuits

Bond two fully processedBond two fully processed

wafers together.wafers together.

--Similar Electrical PropertiesSimilar Electrical Properties

on all deviceson all devices

--Independent of temp. sinceIndependent of temp. since

all chips are fabricated thenall chips are fabricated then

bondedbonded

--Good for applications whereGood for applications where

chips do independentchips do independent

processingprocessing

--However Lack ofHowever Lack of

Precision(alignement)Precision(alignement)

restricts interchiprestricts interchip

communication to globalcommunication to global

metal lines.metal lines.

Epitaxially grow a singleEpitaxially grow a single

crystal Sicrystal Si

--High temperatures causeHigh temperatures cause

significant degradation insignificant degradation in

quality of devices on lowerquality of devices on lower

layerslayers

--Process not yetProcess not yet

manufacturablemanufacturable

Low Temp alternative to SE.Low Temp alternative to SE.

--Offers Flexibility ofOffers Flexibility of

creating multiple layerscreating multiple layers

--Compatible with currentCompatible with current

processing environmentsprocessing environments

--Useful for Stacked SRAMUseful for Stacked SRAMand EEPROM cellsand EEPROM cells


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33--D IC DESIGN STRATEGYD IC DESIGN STRATEGY


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33--D IC design architecture consists of a number of blocks which areD IC design architecture consists of a number of blocks which are

divided from 2divided from 2--D chip(s). Different silicon layers are stacked oneD chip(s). Different silicon layers are stacked one

above the other and different blocks are placed on different layersabove the other and different blocks are placed on different layers

known as tier.known as tier.

Multiple layers of interconnects can be constructed in each Si tier.Multiple layers of interconnects can be constructed in each Si tier.

These interconnects are linked byThese interconnects are linked by verticalvertical interconnects.interconnects. By routingBy routing

vertical interconnects appropriately, long wire length can bevertical interconnects appropriately, long wire length can be

shortened.shortened.

Multiple active routing layers enhances the options to place theMultiple active routing layers enhances the options to place the

critical path components close to each other thereby decreasing RCcritical path components close to each other thereby decreasing RC

delay and significantly improve performance of the design.delay and significantly improve performance of the design.

Global interconnects are made common to all layers. Long wire interGlobal interconnects are made common to all layers. Long wire inter--

block communication delay is eliminated by placing these blocks inblock communication delay is eliminated by placing these blocks in

different layers and connecting them by a vertical interconnect.different layers and connecting them by a vertical interconnect.


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Three dimensional integration can reduce the wiring and hence reduceThree dimensional integration can reduce the wiring and hence reducethe capacitance, power dissipation and chip area and so improvethe capacitance, power dissipation and chip area and so improveoverall performance of the chip.overall performance of the chip.

The powerful advantage of 3The powerful advantage of 3--D chip design methodology can beD chip design methodology can beexploited to build System on Chips (SoCs). Circuits with differentexploited to build System on Chips (SoCs). Circuits with differentvoltage and performance requirements such as digital and analogvoltage and performance requirements such as digital and analogcomponents in the mixedcomponents in the mixed--signal systems can be placed in differentsignal systems can be placed in differentlayers.layers.

Blocks placed in different layers have lesser electromagneticBlocks placed in different layers have lesser electromagneticinterference noise. This can achieve better noise performance of theinterference noise. This can achieve better noise performance of theintended design. High performance SoCs require Synchronous clockintended design. High performance SoCs require Synchronous clockdistribution. At the topmost layer of the 3distribution. At the topmost layer of the 3--D IC,D IC, optical interconnectsoptical interconnectsand I/Os can be employed to achieve this.and I/Os can be employed to achieve this.


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VARIOUS 3 DIMENSIONALVARIOUS 3 DIMENSIONAL

IC TECHNOLOGIESIC TECHNOLOGIES

WirebondedWirebonded

MicroMicro--bump technologybump technology

Through via interconnectThrough via interconnect

Contactless interconnect technologyContactless interconnect technology


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WIREBONDEDWIREBONDED ::

Individual die are stacked and wire bonded in this technique.Individual die are stacked and wire bonded in this technique.

Connections between chips are made through the board or chipConnections between chips are made through the board or chip--carriercarrier

and back to other chips in stack.and back to other chips in stack.

This approach is limited by the resolution of wireThis approach is limited by the resolution of wire--bonders (35bonders (35 m andm and

15 m) and larger number of I/Os in the IC stack limit the wire15 m) and larger number of I/Os in the IC stack limit the wire--bondbondtechnique.technique.

To protect the pad from tearing off due to mechanical stress duringTo protect the pad from tearing off due to mechanical stress during

bond process, all metal layers are required.bond process, all metal layers are required.


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MICROMICRO--BUMP TECHNOLOGYBUMP TECHNOLOGY ::

Connections are made using solder or gold bumps on the surface ofConnections are made using solder or gold bumps on the surface ofdie.die.

Typically, the pitch of bumps is 50Typically, the pitch of bumps is 50--500500 m. Dies are assembled into am. Dies are assembled into acube.cube.

Since assembly related mechanical stresses are less, the pads requireSince assembly related mechanical stresses are less, the pads requiremaximum two layers.maximum two layers.

Compared to wire bonded technology, micro bump technologyCompared to wire bonded technology, micro bump technologyprovides greater vertical interconnect density.provides greater vertical interconnect density.

Since signals have to be routed to the periphery of the chip, noSince signals have to be routed to the periphery of the chip, nosignificant reduction of parasitic capacitance can be achieved. Heatsignificant reduction of parasitic capacitance can be achieved. Heatgenerated inside the cube limits the number of tiers that can begenerated inside the cube limits the number of tiers that can bestacked.stacked.


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With proper placement of blocks in the 3With proper placement of blocks in the 3--D architecture, the use ofD architecture, the use of

highhigh--power dynamic logic circuits, repeaters, pipelined stages longpower dynamic logic circuits, repeaters, pipelined stages long

routing paths could be reduced decreasing overall power consumptionrouting paths could be reduced decreasing overall power consumption

by 15% increasing performance by 15%.by 15% increasing performance by 15%.


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THROUGH VIA INTERCONNECTTHROUGH VIA INTERCONNECT ::

There are two types of through via interconnect technologiesThere are two types of through via interconnect technologiesavailable. They are : through via bulk and through Silicon Insulatoravailable. They are : through via bulk and through Silicon Insulator(SoI). Both methods have the potential to offer the greatest(SoI). Both methods have the potential to offer the greatest

interconnect density with disadvantage of the greatest cost.interconnect density with disadvantage of the greatest cost.

The first and second wafers are placed face to face and as the tierThe first and second wafers are placed face to face and as the tiergrows, higher layers are placed face to back. Connection is providedgrows, higher layers are placed face to back. Connection is providedby filling tungsten in etched wafers.by filling tungsten in etched wafers.

The next chip sits on the polished surface of the previously etchedThe next chip sits on the polished surface of the previously etchedchip. Power, ground and I/O connectivity is provided by the top tier.chip. Power, ground and I/O connectivity is provided by the top tier.

Number of tiers is mainly limited by the heat generated inside theNumber of tiers is mainly limited by the heat generated inside the

stack. Lesser the tier number, higher is the yield.stack. Lesser the tier number, higher is the yield.

Through via Silicon Insulator technology has achieved smallest interThrough via Silicon Insulator technology has achieved smallest intertier pitch of the order of 5tier pitch of the order of 5 m, all layers in the upper tiers and the topm, all layers in the upper tiers and the toplayer in the lower tier is consumed in this technology.layer in the lower tier is consumed in this technology.


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CONTACTLESS INTERCONNECT TECHNOLOGYCONTACTLESS INTERCONNECT TECHNOLOGY ::

Contact less or ACContact less or AC--coupled interconnect use capacitive or inductivecoupled interconnect use capacitive or inductivecoupling to communicate between tiers. This method eliminates thecoupling to communicate between tiers. This method eliminates thesignal interconnect connection to the periphery of the IC as well assignal interconnect connection to the periphery of the IC as well asinterinter--tier routing.tier routing.

Half capacitors formed by top level of metal are used on capacitiveHalf capacitors formed by top level of metal are used on capacitivecoupling. The distance between the tiers, the rise/fall times of thecoupling. The distance between the tiers, the rise/fall times of the

technology, and the dielectric constant of the gap decides the intensitytechnology, and the dielectric constant of the gap decides the intensityof these interconnects.of these interconnects.

Half capacitors approach requires the tiers to be faceHalf capacitors approach requires the tiers to be face--toto--face. Thisface. Thislimits the number of tiers to two.limits the number of tiers to two.

Power supply between the chips is provided by the help of bumps.Power supply between the chips is provided by the help of bumps.The distance between two half plates should be small.The distance between two half plates should be small.


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Either highEither high--k dielectric or trench formation is used to achieve betterk dielectric or trench formation is used to achieve better

capacitive coupling. Inductive coupling is more suitable whereincapacitive coupling. Inductive coupling is more suitable wherein

separation of the coupling elements is of the order of lateral dimensionseparation of the coupling elements is of the order of lateral dimension

of the coupling elements.of the coupling elements.


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PERFORMANCEPERFORMANCE

CHARACTERISTICSCHARACTERISTICS

TimingTiming

Energy performanceEnergy performance


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TIMINGTIMING ::

In current technologies,In current technologies,

timing is interconnecttiming is interconnectdriven.driven.

Reducing interconnectReducing interconnectlength in designs canlength in designs can

dramatically reduce RCdramatically reduce RCdelays and increase chipdelays and increase chipperformance.performance.

The graph shows the resultsThe graph shows the results

of a reduction in wire lengthof a reduction in wire lengthdue to 3D routing.due to 3D routing.


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ENERGY PERFORMANCEENERGY PERFORMANCE ::

Wire length reduction has an impact on the cycle time and the energyWire length reduction has an impact on the cycle time and the energy

dissipation.dissipation.

Energy dissipation decreases with the number of layers used in theEnergy dissipation decreases with the number of layers used in the

design.design.


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ENERGY PERFORMANCE GRAPHSENERGY PERFORMANCE GRAPHS


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CONCERNS IN 3CONCERNS IN 3--D ICsD ICs

Thermal Issues in 3DThermal Issues in 3D--circuitscircuits

EMIEMI

Reliability IssuesReliability Issues


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HEAT FLOW IN 2HEAT FLOW IN 2--DD

Heat generated arises due to

switching.

In 2D circuits we have only one

layer of Si to consider.


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HEAT FLOW IN 3HEAT FLOW IN 3--DD

With multi-layer circuits, the upperlayers will also generate a significant

fraction of the heat.

Heat increases linearly with level increase.


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EMIEMI ::

Interconnect Coupling Capacitance and cross talkInterconnect Coupling Capacitance and cross talk::

Coupling between the top layer metal of the first active layer and theCoupling between the top layer metal of the first active layer and the

device on the second active layer devices is expected.device on the second active layer devices is expected.

Interconnect Inductance Effects :

Shorter wire lengths help reduce the inductance

Presence of second substrate close to global wires might help lower

inductance by providing shorter return paths


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Reliability IssuesReliability Issues ::

Electro thermal and Thermo-mechanical effects between various

active layers can influence electro-migration and chip performance.

Die yield issues may arise due to mismatches between die yields of

different layers, which affect net yield of 3D ICs.


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ADVANTAGES OF 3ADVANTAGES OF 3--D ICsD ICs

Reduction of interconnect delayReduction of interconnect delay

Microprocessor designMicroprocessor design

Mixed signal integrated circuitsMixed signal integrated circuitsSpeedSpeed

PowerPower

DesignDesign

Heterogeneous integrationHeterogeneous integration


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REDUCTION OF INTERCONNECT DELAYREDUCTION OF INTERCONNECT DELAY ::

Interconnect delays contribute significant portion of the overall pathInterconnect delays contribute significant portion of the overall path

delay. Critical path is a result of improper placement of logic cells duedelay. Critical path is a result of improper placement of logic cells due

to design constraints. Long interconnect delays contribute moreto design constraints. Long interconnect delays contribute moretowards the timing violations. So, placing logic blocks in differenttowards the timing violations. So, placing logic blocks in different

silicon layers minimizes interconnect length and critical path delay.silicon layers minimizes interconnect length and critical path delay.

MICROPROCESSOR DESIGNMICROPROCESSOR DESIGN ::Generally in microprocessor designs, onGenerally in microprocessor designs, on--chip cache is physicallychip cache is physically

located on the corner of the die. The logics which access cachelocated on the corner of the die. The logics which access cache

memory are distributed apart. So, onmemory are distributed apart. So, on--chip cache memory is involvedchip cache memory is involved

in most of the critical paths in microprocessor design. Cache memoryin most of the critical paths in microprocessor design. Cache memory

and related logical blocks can be placed close one over the other inand related logical blocks can be placed close one over the other in

different tiers. So, closer proximity of the ondifferent tiers. So, closer proximity of the on--chip is assuredchip is assured..


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MIXED SIGNAL INTEGRATED CIRCUITSMIXED SIGNAL INTEGRATED CIRCUITS ::

22--D approach of System on Chip (SoC) integration causes severalD approach of System on Chip (SoC) integration causes several

serious design issues. Switching noise from digital circuit creeps intoserious design issues. Switching noise from digital circuit creeps into

analog and RF circuits and degrades the fidelity of the analog signals.analog and RF circuits and degrades the fidelity of the analog signals.33--D IC integration can solve these problems effectively. AnalogD IC integration can solve these problems effectively. Analog

related all circuits can be realized in separate tier with differentrelated all circuits can be realized in separate tier with different

technology and can be integrated with digital circuits, which is in atechnology and can be integrated with digital circuits, which is in a

separate layer. Such methodology provides very good noise isolationseparate layer. Such methodology provides very good noise isolation

very much essential for mixed signal circuits.very much essential for mixed signal circuits.

SPEEDSPEED ::

The average wire length becomes much shorter. Because propagatingThe average wire length becomes much shorter. Because propagating

delay is proportional to the square of wire length, overall performancedelay is proportional to the square of wire length, overall performanceincreases.increases.


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POWERPOWER ::

Keeping a signal onKeeping a signal on--chip reduces its power consumption by 10x tochip reduces its power consumption by 10x to100x. Shorter wires also reduce power consumption by producing less100x. Shorter wires also reduce power consumption by producing lessparasitic capacitance. Reducing the power budget leads to less heatparasitic capacitance. Reducing the power budget leads to less heatgeneration, extended battery life and lower cost of operation.generation, extended battery life and lower cost of operation.

DESIGNDESIGN ::

The vertical dimension adds a higher order of connectivity and opens aThe vertical dimension adds a higher order of connectivity and opens a

world of new design possibilities.world of new design possibilities.

HETEROGENEOUS INTEGRATIONHETEROGENEOUS INTEGRATION ::

Circuit layers can be built with different processes or even on differentCircuit layers can be built with different processes or even on differenttypes of wafers. This means that components can be optimized to atypes of wafers. This means that components can be optimized to amuch greater degree than if they were built together on a single wafer.much greater degree than if they were built together on a single wafer.Even more interesting, components with completely incompatibleEven more interesting, components with completely incompatiblemanufacturing could be combined in a single device.manufacturing could be combined in a single device.


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SOME SHORTCOMINGSSOME SHORTCOMINGS

WIRE BONDINGWIRE BONDING


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WIRE BONDINGWIRE BONDING ::

This technique is limited by the resolution of wireThis technique is limited by the resolution of wire--bonders (35bonders (35 m andm and15 m) and larger numbers of I/Os in the IC stack.15 m) and larger numbers of I/Os in the IC stack.

MICROMICRO--BUMPSBUMPS ::Since signals have to be routed to the periphery of the chip, noSince signals have to be routed to the periphery of the chip, nosignificant reduction of parasitic capacitance can be achieved. Heatsignificant reduction of parasitic capacitance can be achieved. Heatgenerated inside the cube limits the number of tiers that can begenerated inside the cube limits the number of tiers that can bestacked.stacked.

CONTACTLESS INTERCONNECTCONTACTLESS INTERCONNECT ::

For half capacitance technology, the tiers should be faceFor half capacitance technology, the tiers should be face--toto--face. Thisface. Thislimits the number of tiers to two.limits the number of tiers to two.

THROUGH VIA INTERCONNECTTHROUGH VIA INTERCONNECT ::Fabrication cost is very high.Fabrication cost is very high.


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CONCLUSIONCONCLUSION

33 D IC kD IC k Fl h d DRAM k d i hFl h d DRAM k d i h


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33--D IC markets:D IC markets:--Flash and DRAM stacked memories, cacheFlash and DRAM stacked memories, cachememories + logic, image sensors on DSP, FPGAs. . .memories + logic, image sensors on DSP, FPGAs. . .

33--D IC is at the R&D stage in the largest IC companies today andD IC is at the R&D stage in the largest IC companies today andtechnical issues are close to be solved.technical issues are close to be solved.

The adoption of advanced packaging technologies could also changeThe adoption of advanced packaging technologies could also changethe industry food chain of the semiconductor.the industry food chain of the semiconductor.

Wire bonding tends to be limited in density and performances.Wire bonding tends to be limited in density and performances.Through via interconnect seems to be unavoidable in future forThrough via interconnect seems to be unavoidable in future forminiaturization.miniaturization.

The current goal is to develop a cost effective technology toolbox forThe current goal is to develop a cost effective technology toolbox for33--D ICs.D ICs.


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THANK YOU ALLTHANK YOU ALL

3-dimensional ics

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