3 clock wb - university of illinois at chicagologos.cs.uic.edu/366/notes/mano diagrams/ch12...stage...
TRANSCRIPT
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-1
(a) Conventional
Function unit
MUX B
MUX D
Clock
3 ns
3 ns
1 ns
4 ns
1 ns
Register file
(b) Pipelined
MUX B
MUX D
Clock
Register file
Function unit
3
WB
OF
1
OF
EX
2
EX
WB
3
1 ns
3 ns
3 ns
1 ns
1 ns
4 ns
1 ns
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-2
AA
Constant in
FS
V
C
N
Z
RW
DA
OF�Operand Fetch (OF)
OF
EX
EX
WB
Write-back (WB)�WB
1
2Execute (EX)
3
Address out
Data out
Data in
Register�file
BA
MB
A data B data
A
Function�unit
F
MD 0
MUX B
MUX D
B
1
D data�Register�
file (same�as above)
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-3
1 9
Clock cycle
OF EX WB
OF EX WB
OF EX WB
OF EX WB
OF EX WB
OF EX WB
OF EX WB
Microoperation
1
2
3
4
5
6
7
8765432
R1 R2 2 R3
R4 sl R6
R7 R7 1 1
R1 R0 1 2
Data out R3
R4 Data in
R5 0
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-4
IF
IF
DOF
Stage�1
Address
DOF
EX
EX
WB
Stage�2
Stage�3
AA BA
Register�file
A data
Zero fill
Instruction decoderMUX B MB
Data A Data B
Address outFS MW
AABAMB
FSCVNZ
A
Function�unit
MDDA RWStage�4
WB
F
MD MUX D
RWDA
Data F Data I
Data in
Data out MW
Data out
Data�memory
Address
CONTROL DATAPATH
4
PC
IR
Instruction�memory
Instruction
B
B data
D data�register�
file (same�as above)
Data�memory�(same as�above)
Data in Address
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-5
1
2
3
4
5
6
7
Instruction
1 2 3 4 5 6 7 8 9 10
Clock cycle
DOF EX WB
DOF EX WB
DOF EX WB
DOF EX WB
DOF EX WB
DOF EX WB
DOF EX WB
IF
IF
IF
IF
IF
IF
IF
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-6
R0 5 0
R1
R31
Register file
Program counter
PC
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-7
OPCODE DR Immediate
OPCODE DR Target offset
Three-register type
Two-register type
Branch
OPCODE DR
SA
SA
SA SB
31 25 24 20 19 15 14 10 9 0
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-1 TABLE 12-1RISC Instruction Operations
OperationSymbolicNotation Opcode Action
No Operation NOP 0000000 NoneMove A MOVA 1000000 R[DR] R[SA]Add ADD 0000010 R[DR] R[SA] �+ R[SB]
Subtract SUB 0000101 R[DR] R[SA] �+ � 1AND AND 0001000 R[DR] R[SA] R [SB]OR OR 0001001 R[DR] R[SA] R[SB]Exclusive-OR XOR 0001010 R[DR] R[SA] R[SB]Complement NOT 0001011 R[DR]Add Immediate ADI 0100010 R[DR] R[SA] �+ se IMSubtract Immediate SBI 0100101 R[DR] R[SA] �+ � 1AND Immediate ANI 0101000 R[DR] R[SA] (0 || IM)OR Immediate ORI 0101001 R[DR] R[SA] (0 || IM)Exclusive-OR Immediate
XRI 0101010 R[DR] R[SA] (0 || IM)
Add Immediate Unsigned
AIU 1000010 R[DR] R[SA] �+ (0 || IM)
Subtract Immediate Unsigned
SIU 1000101 R[DR] R[SA] �+ � 1
Move B MOVB 0001100 R[DR] R[SB]Logical Right Shift by SH Bits
LSR 0001101 R[DR] lsr R[SA] by SH
Logical Left Shift by SH Bits
LSL 0001110 R[DR] lsl R[SA] by SH
Load LD 0010000 R[DR] M[R[SA]]Store ST 0100000 M[R[SA]] R[SB]Jump Register JMR 1110000 PC R[SA]Set if Less Than SLT 1100101 If R[SA] R[SB], then R[DR] +� 1Branch on Zero BZ 1100000 If R[SA] =�
≠ 0, then PC PC +� 1 �+ se IM
Branch on Nonzero BNZ 1010000 If R[SA] 0, then PC PC�+ 1 �+ se IMJump JMP 1101000 PC PC�+ 1 +� se IMJump and Link JML 0110000 PC PC�+ 1 +� se IM, R[DR] PC �+ 1
�← �← �← R SB� � ←� �∧ �← �∨ �←
R SA� �←� ←� ←� se IM + �← � ←� �
←� �
←�
←� 0 || IM( )
←�
←�
←�
←� ←�
←�
←�� �←
←� ←� �
[ ]
[ ] +
⊕
�∧�∨
⊕
�+
�←
<
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-8
MD 0 1 2
MUX D
RWDA
031
AAMA MB BA CS PC21
RW DA MD
MUX C0 1 3 2
BrARAAPC
+1
AddressInstructionmemoryInstruction
PC21
PC22
Adder
BS PS MWFS SH
SH
CSAA
MA MB
Bus A Bus B
RAAAddress
Datamemory
Data outMW
BS0
BS1
PSZ
IM 5 IR14:0
SH 5 IR4:0
Instruction decoder
Constant unit32 3 32Register filewith R0 5 0A data B data BA
1 0 1 0
MUX A MUX B
SHFS
Z
C
A B
Modifiedfunctionunit
F
Bus D
BrA
55
IFDOF
EXWB
WB
IF
DOFEX
D Data32 3 32
Register filewith R0 5 0
Data in Write
AddressDatamemory
IR
N
V
2
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-9
SH0
47 4-to-1 multiplexers (rotate right 0, 16, 32, or 48 bit positions)
32 4-to-1 multiplexers (rotate right 0, 1, 2, or 3 bit positions)
G
Selective2’s complementS
Left/right
2 2 2
5
64
47
35
32
0 || A
35 4-to-1 multiplexers (rotate right 0, 4, 8, or 12 bit positions)
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-2
TABLE 12-2Definition of Control Fields BS and PS
Register TransferBS Code
PSCode Comments
00 X Increment PC
01 0 Branch on Zero
1 Branch on Nonzero
10 X Jump to Contents of R[AA]
11 X Unconditional Branch
PC PC 1�+�←
Z: PC BrA Z: PC PC 1+��←,�←�
Z: PC BrA Z: PC PC 1+�←�,�←�
PC R AA[ ] � �←
PC BrA←
01
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-3 TABLE 12-3Control Words for Instructions
SymbolicNotation Action
OpCode
Control Word Values
RW MD BS PS MW FS MB MA CS
NOP None 0000000 0 XX 00 X 0 XXXX X X X
MOVA R[DR] R[SA] 1000000 1 00 00 X 0 0000 X 0 X
ADD R[DR] R[SA] �+ R[SB] 0000010 1 00 00 X 0 0010 0 0 X
SUB R[DR] R[SA] �+ � 1 0000101 1 00 00 X 0 0101 0 0 X
AND R[DR] R[SA] R[SB] 0001000 1 00 00 X 0 1000 0 0 X
OR R[DR] R[SA] R[SB] 0001001 1 00 00 X 0 1001 0 0 X
XOR R[DR] R[SA] R[SB] 0001010 1 00 00 X 0 1010 0 0 X
NOT R[DR] 0001011 1 00 00 X 0 1011 X 0 X
ADI R[DR] R[SA] +� se IM 0100010 1 00 00 X 0 0010 1 0 1SBI R[DR] R[SA] + � � 1 0100101 1 00 00 X 0 0101 1 0 1ANI R[DR] R[SA] zf IM 0101000 1 00 00 X 0 1000 1 0 0ORI R[DR] R[SA] zf IM 0101001 1 00 00 X 0 1001 1 0 0XRI R[DR] R[SA] zf IM 0101010 1 00 00 X 0 1010 1 0 0AIU R[DR] R[SA] �+ zf IM 1000010 1 00 00 X 0 0010 1 0 0SIU R[DR] R[SA] �+ � 1 1000101 1 00 00 X 0 0101 1 0 0MOVB R[DR] R[SB] 0001100 1 00 00 X 0 1100 0 X X
LSR R[DR] lsr R[SA] by SH 0001101 1 00 00 X 0 1101 X 0 XLSL R[DR] lsl R[SA] by SH 0001110 1 00 00 X 0 1110 X 0 X
LD R[DR] M[R[SA]] 0010000 1 01 00 X 0 XXXX X 0 X
ST M[R[SA]] R[SB] 0100000 0 XX 00 X 1 XXXX 0 0 X
JMR PC R[SA] 1110000 0 XX 10 X 0 XXXX X 0 X
SLT If R[SA] <� R[SB] then R[DR] � 1 1100101 1 10 00 X 0 0101 0 0 X
BZ If R[SA] � 0, then PC PC +� 1�+ se IM 1100000 0 XX 01 0 0 0000 1 0 1BNZ If R[SA] 0, then PC PC +�1 +� se IM 1010000 0 XX 01 1 0 0000 1 0 1JMP PC PC �+ 1�+ se IM 1101000 0 XX 11 X 0 XXXX 1 X 1JML PC PC �+ 1 +� se IM, R[DR] PC �+ 1 0110000 1 00 11 X 0 0000 1 1 1
←� ←� ←� R SB[ ] ←� ∧ �← � ←� ⊕�← R SA[ ]�
←� ←� se IM( ) ←� ∧� ←� � ←� ⊕ ←� ←� zf IM( ) ←� ←� ←� ←�
←� ←�
←��≠ ←�
←� � ←�←
+
+
�←
+
∨
∨
=
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-10
(b) A program-based solution
IF DOF EX WB
IF DOF EX WB
IF DOF EX WB
Write R1
Write R2
First read R1
Second read R1
NOP
MOVA R1, R5
ADD R2, R1, R6
ADD R3, R1, R2
NOP
IF DOF EX WB
IF DOF EX WB
Read R2
R2 R1 1 R6
R3 R1 1 R2
R1 R5
(a) The data hazard problem
1 3 4
IF DOF EX WB
IF DOF EX WB
IF DOF EX WB
Write R1
Write R2
First read R1
Second read R1
Read R2
MOVA R1, R5
ADD R2, R1, R6
ADD R3, R1, R2
R1 R5
R2 R1 1 R6
5 62
R3 R1 1 R2
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-11
IF DOF EX WB
IF DOF
IF DOF EX WB
R1 write and reads
R2 Write and read
R2 data hazard detected,pipeline stalled, andbubble launched.
MOVA R1, R5
ADD R2, R1, R6
ADD R3, R1, R2
(ADD R2, R1, R6)
(ADD R3, R1, R2) IF DOF
IF DOF EX WB
1 2 3 4 5 6 7
R1 data hazard detectedpipeline stalled, and bubble launched
8
R1 R5
R2 R1 1 R6
R2 R1 1 R6
R3 R1 1 R2
R3 R1 1 R2
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-12
Z
C
55
SHFS
RAA
DHSHA
HB
MUX C0 1 3 2
BrA RAA
Address�Instruction�
memory�Instruction
PC21
Adder
BS0
BS1
PSZ
IM 5 IR14:0
SH 5 IR4:0
Constant unit
IR
PC
11
BrA
AAMA MB BA
RW DA MD
BS PS MW FS SH
RWDA
AddressData�
memoryData out
32 3 32�Register file�with R0 5 0
A data
1 0MUX A MUX B
A B
Modified�function�
unit
F
IF
DOF
EX
WB
WB
DOF
EX
D Data32 3 32�
Register file�with R0 = 0
Data inWrite
Address
Data�memory
MD 0 1 2MUX D
Bus D
0 31
MW
Comp
CompSH
AA BA
MBMABus A Bus B
PC21
CS
CS
IF
Instruction decoder
1 0
N
V
2
PC22
B data
DHS
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-13
Z
C
55
SHFS
HB
RAA
MUX C0 1 3 2
BrA RAA
Address�Instruction�
memory�Instruction
PC21
Adder
BS0
BS1
PSZ
IM 5 IR14:0
SH 5 IR4:0
Constant unit
IR
PC
11
BrA
AAMA MB BA
RW DA MD
BS PS MW FS SH
RWDA
AddressData�
memoryData out
32 3 32�Register file�with R0 5 0
A data
1 0MUX A MUX B
A B
Modified�function�
unit
F
IF
DOF
EX
WB
WB
DOF
EX
D Data32 3 32�
Register file�with R0 = 0
Data inWrite
Address
Data�memory
MD 0 1 2MUX D
Bus D
031
MW
Comp
CompSH
AA BA
MBMABus A Bus B
PC21
CS
CS
HA
IF
Instruction decoder
MUX D'0 1 2
031
2 1 02 HBHA
Bus D'
N
V
2
PC22
B data
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-14
1 3 4
IF DOF EX WB
IF DOF EX WB
IF DOF EX WB
R1 data hazard detected�and R1 value forwarded
R1 write and read
R2 data hazard detected�and R2 value forwarded
MOVA R1, R5
ADD R2, R1, R6
ADD R3, R1, R2
R1 R5
R2 R1 1 R6
R3 R1 1 R2
Write R22 5 6
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-15
(a) Branch Hazard Problem
IF DOF EX WB
IF DOF EX WB
IF DOF EX WB
R1 = 0 evaluated
PC set to 20
Instruction MOV R5, R6fetched from target address
1 BZ R1, 18
3 MOV R1, R2
2 MOV R2, R3
20 MOV R5, R6 IF DOF EX WB
Change in R2
Change in R1
1 2 3 4 5 6 7
(b) Program-based Solution
IF DOF EX WB
IF DOF EX WB
IF DOF EX WB
R1 = 0 evaluated
PC set to 20
Instruction MOV R5, R6fetched from target address
1 BZ R1, 18
3 NOP
2 NOP
20 MOV R5, R6 IF DOF EX WB
No change
No change
1 2 3 4 5 6 7
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-16
IF
IF
IF
IF
DOF
DOF
DOF
DOF
EX
EX
EX
WB
WB
WB
WB
R1 = 0 evaluated
PC set to 20
Instruction MOV R5, R6fetched from target address
1 BZ R1, 18
3 MOVA R1 R2
2 MOVA R2 R3
20 MOVA R5 R6
No change
No change
1 2 3 4 5 6 7
Branch detectedand bubbles launched
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-17
0 1 2MUX D
RWDA
031
AAMA MB BA CS PC21
RW DA MD
MUX C 0 1 23
BrA RAAPC
11
AddressInstruction
memoryInstruction
PC21
PC22
ADDER
BS PS MW FS SH
SH
CSAA
MA MB
Bus A Bus B
RAA
AddressDatamemory
Data outMW
BS0BS1
PS
IM 5 IR14:0
SH 5 IR4:0
Instruction decoder
Constant unit 32 3 32Register filewith R0 = 0A data B data BA
1 0 1 0MUX A MUX B
SHFS
Z
C
A B
Modifiedfunctionunit
F
Bus D
BrA
55
IFDOF
EXWB
WB
IF
DOFEX
D Data32 3 32
Register filewith R0 = 0
Data inWrite
AddressDatamemory
IR
2
N
V
Z
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-18
MicroprogramCounter
Control ROM
Instruction fetch
Decode & Operand Fetch
Execute
Write-back
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-19
OPCODE DR SA Immediate
Three-register type
Two-register type
OPCODE DR SA Long target offsetBranch 1
OPCODE DR SA SB
31 25 24 20 19 15 14 10 9 0
OPCODE DR SA Short target offsetBranch 2 SB
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-20
MD 0 1MUX D
RWFDA
027
AA BA
CS
PC21
RW MD
MUX C0 1 3 2
BrA RAAPC
11 AddressInstructionmemoryInstruction
PC21
PC22
Adder
BS PS MW FS
CS
Bus A Bus B
RAA
AddressDatamemory
Data outMW
BS0BS1
PSZ
IM = IR14:0
Instruction decoder
Constant unit 32 x 32Register filewith R0 = 0
A data B data
1 0 1 0MUX AMUX B
SHFS
Z C
A B
Modifiedfunctionunit
F
Bus D
BrA
5
5
IF
DOF
EX
WB
IF
DOF
EX
D Data32 3 32
Register filewith R0 5 0
Data in Write
AddressDatamemory
IR
N V
2
5
5
Registeraddresslogic
AXBX DX
AA
BA
DA
4
4
4 5
5
Z
L
WB
IR4:0
01 MUX I
MIR30:0
AX BX
SA
CA
MI
MS
LC
LC
2
CC
To Mux A
From CCDA
SH
FDA
DX
DFDA
DFDA
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-4TABLE 12-4Added or Modified Control Word (Microinstruction) Fields for CISC
Control Fields Register Fields CS MA LC
MZ2b
CA8h
BS2b
PS Action Code
5h Action Code2b Action Code
2b Action Code
SeeTable12-3
NextAddressor Con-
stant
SeeTable12-2
AX, BX zf IMse IMse IMS
zf CA
00011011
A Data PC�−10 || CC
000110
Hold CCLoad CC
01
R[SA], R[SB]R16...
R31
0X10...1F
DX
Source R[DR]and Dest. R[SB]Dest R[DR]with
R16...
R31
00
0X
10...1F
X 0≠
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
12-21
11
MC
MIR
MIR30:0
SA
8 8 8
8
Microcode ROM
Address
Data
0 1Mux E
ME Microaddresscontrol
MSMIMZ
PSZ
MZ212 3
CACA21
41
82 31CA
DOF
EX
MZ
82CA21MZ21
(a)
MZ
40 39 38 31 30 29 25 24 23 22 21 20 19 16 15 14 13 12 11 7 6 2 1 0
RW
PS
MW
LC
MA
MB
CS
MD
CA DX BS FS AX BX
(b)
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-5
TABLE 12-5Address Control
Inputs Outputs
Register Transfer Due to MEMZ � 1 MZ MI PS Z ME1 ME0 MS
11 01 X 0 0 0 0 1
11 01 X 0 1 0 1 1
11 01 X 1 0 0 1 1
11 01 X 1 1 0 0 0
0X 01 X X X 0 0 1
X0 01 X X X 0 0 1
XX 00 0 X X 1 0 0
XX 00 1 X X 0 1 1
XX 10 X 0 X 1 0 0
XX 10 X 1 X 1 0 1
XX 11 X X X 0 0 1
PS Z� : MC MC 1�+�←
PS Z� : MC CA−1��←
PS Z� : MC CA−1��←
PS Z� : MC MC 1�+�←
MC MC 1�+�←
MC MC 1�+�←
MC CA←�
MC SA�←
PS: MC CA�←
PS: MC CA�←
MC MC 1�+�←
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-6ATABLE 12-6Example Microprograms for CISC Architecture
Action Address
Microinstructions
MZ CARW DX
MD BS
PS
MW FS
LC MA
MB AX BX CS
Shared Microinstructions
IDLE 00 00 0 00 0 00 0 0 0 0 00 0 00 00 00 (NOP) Arbitrary 01 XX 0 00 0 00 0 0 0 0 00 0 00 00 00
Load Indir ect Indexed (LII)LII0 01 00 1 10 0 00 0 0 2 0 00 1 00 00 00
(NOP) LII1 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00LII2 01 00 1 11 1 00 0 0 0 0 00 0 10 00 00
(NOP) LII3 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00LII4 10 IDLE 1 01 1 00 0 0 0 0 00 0 11 00 00
Compare Less Than or Equal To (BLE)
BLE0 01 00 0 01 0 00 0 0 5 1 00 0 00 00 00
(NOP) BLE1 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00BLE2 01 18 1 1F 0 00 0 0 8 0 10 1 00 00 11
(NOP) BLE3 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00
BLE4 11 BLE7 0 00 0 00 1 0 0 0 00 0 1F 00 00
(NOP) BLE5 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00BLE6 00 IDLE 0 00 0 00 0 0 0 0 00 0 00 00 00
BLE7 10 IDLE 0 00 0 11 0 0 0 0 01 1 00 00 10
MI: MC SA�← MI:MC 00�←,�MC MC 1+←�
R16 R SA[ ] � �zf IML+←�MC MC 1+��R17 M R16[ ] � �←�MC MC 1+�←�R DR[ ] � �M R17[ ] � �←�
R SA[ ] � �R SB[ ] � �CC L Z N C V�����←MC MC 1�+�←R31 CC 11000∧��MC MC 1�+←�if R31( 0)MC BLE7←��
else MC MC 1�+�←�MC MC 1�+←�MC IDLE�←PC PC 1� se IML�←� ,�
MC IDLE←�+−
←�
�←
|| || || ||
≠
−
© 2004 Pearson Education, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 3e
T 12-6B
Move Memory Block (MMB)MMB0 01 00 1 10 0 00 0 0 C 0 00 0 00 00 00
(NOP) MMB1 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00MMB2 01 01 1 10 0 00 0 0 5 0 00 1 00 00 11MMB3 01 00 1 00 0 00 0 0 C 0 00 0 00 11 00MMB4 01 00 1 12 0 00 0 0 2 0 00 0 00 10 00MMB5 01 00 1 13 0 00 0 0 2 0 00 0 11 10 00MMB6 01 00 1 14 1 00 0 0 0 0 00 0 12 00 00
(NOP) MMB7 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00MMB8 01 00 0 00 0 00 0 1 0 0 00 0 13 14 00MMB9 11 MMB2 0 00 0 00 1 0 0 1 00 0 10 00 00
(NOP) MMB10 01 00 0 00 0 00 0 0 0 0 00 0 00 00 00MMB11 10 IDLE 0 00 0 00 0 0 0 0 00 0 00 00 00
R16 ←�R[SB]MC MC 1+�←�R16 R16 1−�←�R17 R DR[ ] � �←�R18 R16�← R[SA]R19 R17 R16�+←�R20 M R18[ ] � ��←MC MC 1�←�M R19[ ] � �R20←�if R16 0� MC MMB2←�MC MC 1�+�←MC IDLE←�
TABLE 12-6Example Microprograms for CISC Architecture
Action Address
Microinstructions
MZ CARW DX
MD BS
PS
MW FS
LC MA
MB AX BX CS
Shared Microinstructions
IDLE 00 00 0 00 0 00 0 0 0 0 00 0 00 00 00 (NOP) Arbitrary 01 XX 0 00 0 00 0 0 0 0 00 0 00 00 00
MI: MC SA�← MI:MC 00�,�MC MC 1�←�
+
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+
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