2sk3115
TRANSCRIPT
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MOS FIELD EFFECT TRANSISTOR
The information in this document is subject to change without notice. Before using this document, pleaseconfirm that this is the latest version.Not all devices/types available in every country. Please check with local NEC representative foravailability and additional information.
© 1998, 2001
2SK3115SWITCHING
N-CHANNEL POWER MOS FETINDUSTRIAL USE
Document No. D13338EJ2V0DS00 (2nd edition)Date Published January 2001 NS CP (K)Printed in Japan
DATA SHEET
The mark shows major revised points.
DESCRIPTION The 2SK3115 is N-Channel DMOS FET device that features a low gate charge and excellent switching haracteristics, and
designed for high voltage applications such as switching power supply, AC adapter.
FEATURES• Low gate charge
QG = 26 nC TYP. (VDD = 450 V, VGS = 10 V, ID = 6.0 A)
• Gate voltage rating ±30 V
• Low on-state resistance
RDS(on) = 1.2 Ω MAX. (VGS = 10 V, ID = 3.0 A)
• Avalanche capability ratings
ABSOLUTE MAXIMUM RATINGS (T A = 25°C)
Drain to Source Voltage (VGS = 0 V) VDSS 600 V
Gate to Source Voltage (VDS = 0 V) VGSS ±30 V
Drain Current (DC) (TC = 25°C) ID(DC) ±6.0 A
Drain Current (pulse) Note1ID(pulse) ±24 A
Total Power Dissipation (TA = 25°C) PT1 2.0 W
Total Power Dissipation (TC = 25°C) PT2 35 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg −55 to +150 °C
Single Avalanche Current Note2IAS 6.0 A
Single Avalanche Energy Note2EAS 24 mJ
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%
2. Starting Tch = 25°C, VDD = 150 V, RG = 25 Ω, VGS = 20 → 0 V
ORDERING INFORMATION
PART NUMBER PACKAGE
2SK3115 Isolated TO-220
(Isolated TO-220)
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Data Sheet D13338EJ2V0DS2
2SK3115
ELECTRICAL CHARACTERISTICS (T A = 25°C)
Characteristics Symbol Test Conditions MIN. TYP. MAX. Unit
Zero Gate Voltage Drain Current IDSS VDS = 600 V, VGS = 0 V 100 µA
Gate Leakage Current IGSS VGS = ±30 V, VDS = 0 V ±100 nA
Gate Cut-off Voltage VGS(off) VDS = 10 V, ID = 1 mA 2.5 3.5 V
Forward Transfer Admittance | yfs | VDS = 10 V, ID = 3.0 A 2.0 S
Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 3.0 A 0.9 1.2 Ω
Input Capacitance Ciss VDS = 10 V 1100 pF
Output Capacitance Coss VGS = 0 V 200 pF
Reverse Transfer Capacitance Crss f = 1 MHz 20 pF
Turn-on Delay Time td(on) VDD = 150 V, ID = 3.0 A 18 ns
Rise Time tr VGS(on) = 10 V 12 ns
Turn-off Delay Time td(off) RG = 10 Ω, RL = 50 Ω 50 ns
Fall Time tf 15 ns
Total Gate Charge QG VDD = 450 V 26 nC
Gate to Source Charge QGS VGS = 10 V 6 nC
Gate to Drain Charge QGD ID = 6.0 A 10 nC
Body Diode Forward Voltage VF(S-D) IF = 6.0 A, VGS = 0 V 1.0 V
Reverse Recovery Time trr IF = 6.0 A, VGS = 0 V 1.4 µs
Reverse Recovery Charge Qrr di/dt = 50 A/µs 6.5 µC
TEST CIRCUIT 3 GATE CHARGE
VGS = 20 → 0 VPG.
RG = 25 Ω
50 Ω
D.U.T.L
VDD
TEST CIRCUIT 1 AVALANCHE CAPABILITY
PG.
D.U.T.RL
VDD
TEST CIRCUIT 2 SWITCHING TIME
RG
PG.
IG = 2 mA
50 Ω
D.U.T.RL
VDD
IDVDD
IASVDS
BVDSS
Starting Tch
VGS
0
τ = 1 µsDuty Cycle ≤ 1%
τ
VGSWave Form
VDSWave Form
VGS
VDS
10%0
0
90%
90%
90%
VGS(on)
VDS
ton toff
td(on) tr td(off) tf
10% 10%
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Data Sheet D13338EJ2V0DS 3
2SK3115
TYPICAL CHARACTERISTICS (T A = 25°C)
DERATING FACTOR OF FORWARD BIASSAFE OPERATING AREA
Tch - Channel Temperature - ˚C
dT -
Per
cent
age
of R
ated
Pow
er -
%
0 4020 60 100 14080 120 160
100
80
60
40
20
0
TC - Case Temperature - ˚C
PT
- T
otal
Pow
er D
issi
patio
n -
W
0 8020 40 60 100 140120 160
80
60
40
20
TOTAL POWER DISSIPATION vs. CASE TEMPERATURE
FORWARD BIAS SAFE OPERATING AREA
10 100 1000
ID -
Dra
in C
urre
nt -
A
1
VDS - Drain to Source Voltage - V
100
10
1
0.1
Power Dissipation Limited
100 µs
10 ms
1 ms
100 ms
PW = 10 µs
RDS(on) Limited
ID(pulse)
ID(DC)
TC = 25˚CSingle Pulse
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
PW - Pulse Width - s
r th
(t) -
Tra
nsie
nt T
herm
al R
esis
tanc
e -
˚C/W
100 m 1 10 100 100010 m1 m100 µ10 µ
100
10
1
0.1
0.01
Rth(ch-A) = 62.5˚C/W
Rth(ch-C) = 3.57˚C/W
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Data Sheet D13338EJ2V0DS4
2SK3115
DRAIN CURRENT vs.DRAIN TO SOURCE VOLTAGE
VDS - Drain to Source Voltage - V
ID -
Dra
in C
urre
nt -
A
10 4020 30
5
15
20
10
0
25
6 V
VGS = 10 V
8 V
Pulsed
FORWARD TRANSFER CHARACTERISTICS
VGS - Gate to Source Voltage - V
ID -
Dra
in C
urre
nt -
A
151050
100
10
1.0
0.1
VDS = 10 VPulsed
Tch = 125˚C 75˚C
Tch = 25˚C−25˚C
GATE CUT-OFF VOLTAGE vs.CHANNEL TEMPERATURE
Tch - Channel Temperature - ˚C
VG
S(o
ff) -
Gat
e C
ut-o
ff V
olta
ge -
V
−50 0 50 100 150
5.0
4.0
3.0
2.0
1.0
0
VDS = 10 V
ID = 1mA
FORWARD TRANSFER ADMITTANCE vs.DRAIN CURRENT
1.0 10
ID - Drain Current - A
| yfs
| -
For
war
d T
rans
fer
Adm
ittan
ce -
S
10
0.1
1.0
0.1
VDS = 10 VPulsed
Tch = −25˚C 25˚C 75˚C 125˚C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.GATE TO SOURCE VOLTAGE
8 2016
2.0
VGS - Gate to Source Voltage - V
RD
S (
on) -
Dra
in to
Sou
rce
On-
stat
e R
esis
tanc
e -
Ω
ID = 6.0 A3.0 A
1.0
04 12
Pulsed
0
DRAIN TO SOURCE ON-STATERESISTANCE vs. DRAIN CURRENT
1.0 10 100
0.8
ID - Drain Current - A
RD
S(o
n) -
Dra
in to
Sou
rce
On-
stat
e R
esis
tanc
e -
Ω
0.4
2.0
0
1.2
1.6
VGS = 10 V20 V
Pulsed
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Data Sheet D13338EJ2V0DS 5
2SK3115
DRAIN TO SOURCE ON-STATE RESISTANCE vs.CHANNEL TEMPERATURE
50 150
RD
S (
on) -
Dra
in to
Sou
rce
On-
stat
e R
esis
tanc
e -
Ω
ID = 6.0 A3.0 A
2.0
00 100−50
Tch - Channel Temperature - ˚C
3.0
1.0
VGS = 10 V
Pulsed
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
VSD - Source to Drain Voltage - V
ISD -
Dio
de F
orw
ard
Cur
rent
- A
1.51.00.50
100
10
1.0
0.1
Pulsed
0 VVGS = 10 V
1000100101.0
10000
1000
100
10
1
CAPACITANCE vs. DRAIN TOSOURCE VOLTAGE
Cis
s, C
oss,
Crs
s -
Cap
acita
nce
- pF
Ciss
Coss
Crss
VDS - Drain to Source Voltage - V
VGS = 0 Vf = 1 MHz
SWITCHING CHARACTERISTICS
0.1 1 10
ID - Drain Current - A
td(o
n), t
r, td
(off)
, tf -
Sw
itchi
ng T
ime
- ns
100
10
1
0.1
VDD = 150 VVGS = 10 VRG = 10 Ω
td(off)
td(on)
tf
tr
REVERSE RECOVERY TIME vs.DRAIN CURRENT
1.0 10 100
trr -
Rev
erse
Rec
over
y T
ime
- ns
0.1
ID - Drain Current - A
10000
1000
100
10
di/dt = 50 A/µsVGS = 0 V
Qg - Gate Charge - nC
VD
S -
Dra
in to
Sou
rce
Vol
tage
- V
0 2010 30 40
600
400
200
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
VG
S -
Gat
e to
Sou
rce
Vol
tage
- V
16
14
12
10
8
6
4
2
0
ID = 6 A
VGSVDD = 450 V300 V120 V
VDS
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Data Sheet D13338EJ2V0DS6
2SK3115
SINGLE AVALANCHE CURRENT vs.INDUCTIVE LOAD
100 µ 1 m 10 m
100
L - Inductive Load - H
IAS -
Sin
gle
Ava
lanc
he C
urre
nt -
A
1.0
10
0.110 µ
RG = 25 ΩVDD = 150 VVGS = 20 → 0 VStarting Tch = 25˚C
EAS = 24 mJ
IAS = 6 A
SINGLE AVALANCHE ENERGYDERATING FACTOR
75 150125
120
100
80
60
40
20
0
Starting Tch - Starting Channel Temperature - ˚C
Ene
rgy
Der
atin
g F
acto
r -
%
50 10025
VDD = 150 VRG = 25 ΩVGS = 20 → 0 VIAS ≤ 6 A
PACKAGE DRAWING (Unit: mm)
10.0 ± 0.33.2 ± 0.2φ
4.5 ± 0.2
2.7 ± 0.2
2.5 ± 0.1
0.65 ± 0.11.5 ± 0.22.54
1.3 ± 0.2
2.54
0.7 ± 0.1
4 ±
0.2
15.0
± 0
.3
12.0
± 0
.2
3 ±
0.1
1 2 3
1.Gate2.Drain3.Source
13.5
MIN
.
Isolated TO-220(MP-45F)
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
EQUIVALENT CIRCUIT
BodyDiode
Source (S)
Drain (D)
Gate (G)
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Data Sheet D13338EJ2V0DS 7
2SK3115
[MEMO]
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2SK3115
M8E 00. 4
The information in this document is current as of January, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.NEC semiconductor products are classified into the following three quality grades:"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
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