2d electronics: graphene and beyond
TRANSCRIPT
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
2D Electronics: Graphene and Beyond
Kaustav Banerjee
ESSDERC 2013, Bucharest, Romania
NanResearch Lab
Department of Electrical and Computer Engineering University of California Santa Barbara [email protected]
Sep. 19, 2013
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
According to the International Energy Agency:
i) Electronic devices currently account for 15% of household electricity consumption
ii) Energy consumed by information and communications technologies as well as consumer electronics will double by 2022 and triple by 2030 to 1,700 Terawatt hours
= the entire total residential electricity consumption of US and Japan in 2009!!!
Energy Consumption by Electronics…
Source: 2009 U.S. Greenhouse Gas Inventory Report, April 2009
http://www.epa.gov/climatechange/emissions/usinventoryreport.html 0
500
1000
1500
2000
Transportation Residential
Without Green Electronics
With Green Electronics
CommercialIndustruial
CO
2 (
Mil
lio
n M
etr
ic T
on
s) -24%
-29%
-33%-33%
With improved efficiency of IT usage, around 30% reduction per year in GHG is achievable, which is equivalent to gross energy and fuel savings of 315 billion U.S. dollars!!!
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Energy/Power Consumption in ICs… 6X
1.6X
S. Borkar (Intel)
On-die global interconnect energy
scales slower than compute
On-die data movement energy will
start to dominate
Dragon Energy
Need Green Interconnects
Need Green Transistors
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
So, How can we design Green Electronics?
I will use 2D electronic materials:
Graphene and Beyond
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
2D Electronic Materials
2D family tree
TMD family
Graphene family
Other families • Bi2Sr2Co2O8
• Ti2C, Ti2CF2, Ti2C(OH)2
• etc
• Graphene (semi-metal)
(Eg=0eV)
• h-BN (dielectric) (Eg>5eV)
• Silicine (semiconductor)
(Eg=0.6 eV, experimentally)
• MoS2, WSe2, etc (semiconductors)
• CrO2, CrS2, etc (half-metals) (0<Eg<1eV)
• VO2, VS2, etc (metals)
• NbSe2, etc (superconductor)
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Advantages of 2D ─ Ultra Thin Body
few Å
Can be exfoliated
Layered structure
Van der Waals force
Covalent bonds
3D 2D
● band gap varies uncontrollably with thickness ● cause variations when scaled
● intrinsic thickness < 1nm/L ● controllable precise band gap ● enable scaling in nm regime ● lead to novel applications
Covalent bonds
Onion-like Potato-like
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Advantages of 2D ─ Ultra Thin Body (contd.)
3D 2D
● mobile carriers exist at >1 nm away from the surface ● limited gate electrostatics ● short-channel effects
● carriers confined to <1 nm thickness ● excellent gate electrostatics ● reduce short-channel effects
Gate Gate
Potential B
arrier
|Ψ(x)|2
V(x)
x
Potential B
arrier
|Ψ(x)|2
V(x)
x
Carriers confined
Mobile charges centroid
Oxide Oxide
Substrate
1.2
nm
d
ee
p
few
Å
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Advantages of 2D ─ Pristine Interface
No dangling bonds (pristine interface)
Dangling bonds (may form traps)
● suffer from interface traps ● Fermi level pinning, increased scattering, etc.
● fewer interface traps ● increase stability/reliability
3D 2D Unsaturated atoms
saturated atoms
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Forms of Carbon… Carbon atom can form several distinct types of valence bonds….
+6 - -
-
- -
-
6C
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
2D and 1D Carbon Nanomaterials
Graphene (Thinnest 2D Crystal)
Single-wall CNT (1D) Multi-wall CNT (1D)
Graphene (Thinnest 2D Crystal)
Monolayer Graphene NanoRibbons (GNRs) (1D) zigzag
↑ armchair
Multi-layer GNR (1D)
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
kx
ky
Energy (E)
Crystal & Band Structure of Graphene
Energy (E)
kx
ky
Dirac point
𝐸(𝑘𝑥, 𝑘𝑦) − 𝐸𝐹𝑖 = ±ℎ𝑣𝐹 𝑘𝑥2 + 𝑘𝑦
2
Unit cell
A
B
Basis
sp2 bonds
pz orbitals
hopping energy
≈ 3 eV
e -
● Zero bandgap ● Linear E-k near Dirac point ● Close to zero effective mass ● Electrons and holes are equal
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Chiralities and Band Gap Tuning of Graphene
(n=0, 1, 2, …)
zz ac, NW=3n-1 ac, NW=3n ac, NW=3n+1
Simulations (n=1,2,…):
empirical experiment
Li, Xiaolin, et al., Science 319. 5867 (2008)
Graphene Graphene NanoRibbon (GNR)
E
kBandgap
opening
Energy (E)
kx
ky
Dirac point
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Superb Properties of CNT and Graphene
Si Cu SWCNT MWCNT Graphene or
GNR
Max current density
(A/cm2) - 107
>1x109
Radosavljevic, et al., Phys. Rev. B, 2001
>1x109
Wei, et al., Appl. Phys. Lett.,
2001
>1x108
Novoselov, et al., Science, 2001
Melting point (K) 1687 1356 3800 (graphite)
Tensile strength
(GPa) 7 0.22 22.2±2.2 11-63
Mobility (cm2/V-s) 1400 >10000 >10000
Thermal
conductivity
(103 W/m-K) 0.15
0.38
5
1.75-5.8 Hone, et al.,
Phys. Rev. B, 1999
3.0 Kim, et al.,
Phys. Rev. Lett., 2001
3.0-5.0 Balandin, et al., Nano Lett., 2008
Temp. Coefficient of
Resistance (10-3
/K) - 4
<1.1 Kane, et al.,
Europhys. Lett., 1998
-1.37 Kwano et al.,
Nano Lett., 2007
-1.47 Shao et al.,
Appl. Phys. Lett., 2008
Mean free path
(nm) @ room
temp. 30 40
>1,000 McEuen, et al.,
Trans. Nano., 2002
25,000 Li, et al.,
Phys. Rev. Lett., 2005
~1,000 Bolotin, et al.,
Phys. Rev. Lett., 2008
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Graphene Preparation
Top-down approach
• Mechanical exfoliation of graphite
• Liquid phase exfoliation
Bottom-up approach
• CVD from hydrocarbon (Large-area, high quality)
• Epitaxial growth on SiC
• Organic synthesis
Carrier Layer (PMMA/PDMS)
Coating carrier layer Etching metal catalyst Releasing graphene
Graphene Transfer
Monolayer Bilayer
K. S. Novoselov et al., Science,2004
X. Li, et al., Science,2008
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Graphene FETs with Record Mobility: • synthesized using CVD; • controlled synthesis of monolayer and bilayer graphene demonstrated W. Liu, H. Li, C. Xu, Y. Khatami and K. Banerjee, "Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition," CARBON, Vol. 49, No. 13, pp. 4122-4130, 2011.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Wafer scale AB stacked bilayer graphene
>98% AB stacking order with high quality
Most reliable method of synthesizing AB stacked BLG
Typical electron diffraction pattern of AB stacked bilayer Synthesized bilayer graphene shows high ON/OFF ratio
W. Liu et al., UCSB/Rice, (2013) (under review)
Controllable Synthesis of AB Stacked Bilayer Graphene
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Applications of Graphene
S
TG
D
BG
GNR NDR
S DG
FETS(Graphene FET, GNRTFET, etc.)
DS
G
Biosensor
NDR-based SRAM
BG
TG
Vout
BG
VDD
GND
TG
N-NDR
P-NDR
NDR-based SRAM
Interconnect Inductor
VDD
GND
Vin
Vin
Vout2
Vout1
Inverter 1Inverter 2
All-graphene
Logic Circuit
S D
G
FG
Floating-Gate
Memory
Transparent
Electrode
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Interconnect Power Dissipation
34%
15%
51%
Logic (gate capacitance)
Logic (diffusion capacitance)
Interconnect
FF FF FF
Clock Clock Clock
l
s s s
l
s s s
L
Global interconnects must be optimally pipelined to meet clock period and power criteria
N. Magen et al., SLIP, pp. 7-13, 2004.
K. Banerjee and A. Mehrotra IEEE TED, vol. 49, no. 11, pp. 2001-2007, 2002.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Low Power Interconnects
s s sss
H. Li, C. Xu and K. Banerjee, “Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs ” IEEE Design and Test, vol. 27, no.4, pp. 20-31, 2010
sss
Inverter insertion configuration:
Lower delay allows larger distance between inverters, thus reduces the power
If delay is kept identical to Cu optimal delay CNT/GNR global interconnect could save ~50% power!!
Perc
enta
ge
(%
)
0
20
40
60
80
100
22 nm 14 nm
CuSWCNT
Fm=1MWCNT
GNR
p=1
50.9448.47 57.64
51.4550.63 57.49
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
High-Q CNT/GNR based Low-Loss Inductors
0.1 1 100
10
20
30
40
50
Cu
SWCNT, Fm=1/3
MWCNT, D=10 nm
GNR p=0
GNR p=1
Frequency (GHz)
sub
= 10 -cm
Qu
ality
Fa
cto
r
0.1 1 100
10
20
30
40
50
60
70
(a) Frequency [GHz]
142%
sub= 10 -cm
Cu
SWCNT Fm=1/3
SWCNT Fm=1
MWCNT D=10nm
MWCNT D=20nm
MWCNT D=40nm
Qu
ality
Facto
r
• CNTs can provide better performance than Cu
• MWCNT gives 2.4X higher Q factor than that of Cu
• GNR shows an improvement of:
~20% over Cu
~50% over 1/3 metallic SWCNT
D. Sarkar, C. Xu, H. Li and K. Banerjee, TED , Vol. 58, March 2011 .
H. Li and K. Banerjee, TED, vol. 56, no. 9, 2009
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
H. Li, C. Xu, N. Srivastava, and K. Banerjee, “Carbon nanomaterials for next generation interconnects and passives: Physics, status, and prospects,” TED, vol. 56, no. 9, pp. 1799-1821, 2009.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
First Demonstration of Long Horizontal CNT Bundle Interconnects @ UCSB
• Longer than 120 mm horizontal CNT bundle
• Thickness ranges from 100nm – 2 mm
50mm
Raman TEM SEM
H. Li et. al., IEEE T-ED, Vol. 60, No. 9, pp. 2862-2869, 2013.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
First Demonstration of Horizontal CNT Bundle Based Manhattan Structure
100mm
Liquid flow
100mm
(a) (b)First demonstration of a
Kanji character using
horizontal CNT bundles
H. Li et. al., IEEE T-ED, Vol. 60, No. 9, pp. 2862-2869, 2013.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
• First time demonstration of CNT bundle based inductor
• Single turn with diameter 100-150 mm
• Segment width 10-30 mm, thickness 300nm - 2 mm
100 mm
H. Li et. al., IEEE T-ED, Vol. 60, No. 9, pp. 2862-2869, 2013.
First Demonstration of Carbon Nanotube Inductor
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Transparent Electrodes
• Mainstream: ITO (limited) • Limited Indium supply • Fabrication/Integration Cost • Lack of flexibility
• Alternatives (under research) • Metal grids • Thin film • Metal oxides • Graphene
• Industry requirement: • Optical transmission >90%
• Electrical conductivity <10 Ω/sq
Transparent electrode market by year
Graphene Electrode Advantages
• Low cost fabrication (CVD)
• Large-area high quality sheets
• High electrical conductivity
• High mobility
• High optical transparency
• Mechanical flexibility
• High thermal stability
• Impermeability to moisture
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Graphene Electrode Applications
Bae et. al., Nature Nano, 5, 2010.
Touch Panels
Chul-Ho Lee, et al., Adv. Mater., 23, 2011.
Light Emitting Devices
Display
Solar Cells
Xuan Wang, et al., Nano Lett., 8, 2008
S.Lara-Avila, et al., Adv. Mater., 23, 2011.
Light Sensors
Graphene Electrode
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
First ESD Characterization of Graphene (UCSB/Intel)
● Breakdown current: 4.5mA/mm for 100 ns TLP and 8mA/mm for 10 ns TLP ● Maximum Current density: 2-5x 108 A/cm2 ● Graphene devices show clear “open cut” in the channel after breakdown
a b c d e f0
1
2
3
4
5
Devices
It2
pe
r M
icro
n (
mA
/mm
)
3 layer4-5 layer
open
0 2 4 6 8 10 120
2
4
6
8
10
TL
P C
urr
ren
t (m
A)
TLP Voltage (V)
W=3.8 mm
L =3.1 mm
@100ns
H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee, 34th EOS/ESD Symp., 2012.
Best Paper Award & Best Student Paper Award
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Dimension scaling Increase transistor density
Oxide thickness scaling Higher Performance
VDD scaling Energy Efficiency
CMOS Transistor Scaling Issue
Aggressive scaling leads to an
exponential increase in leakage power!!!
VG
log(ID) VDD scaling
Solution to leakage Issue: Steeper turn on
High Off Current
Low Off Current
2
DDVE
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Ideal-Switch: Greenest Transistor!
Gate voltage (Vgs)
Dra
in c
urr
en
t (l
og
(Id))
ΔVgs
Δlog(Id)
An ideal switch
Solid-state devices
Vth
S = ΔVgs/Δlog(Id)
Subthreshold Swing (S) should be as low as possible!!
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
MOSFET vs. Tunnel-FET
ON Current
OFF Current
ON Current
OFF Current
Barrier
(~Eg)
(Leakage) (Nearly
No Leakage)
Source Drain
Channel
EC
EV
Source Drain
Channel
EV
Gate Oxide
Gate Oxide
Oxide Gate
n+ n+
p
Source Drain
Channel p+ n(+) i
Source Drain
Channel
(Tunnel Current)
S ≥ 60 mV/decade S << 60 mV/decade
Source
Drain
Channel
EC
EV
Drain Source Channel
Y. Khatami and K. Banerjee, TED, vol. 56, no. 11, 2009.
barrier(Φbi)
EC
Boltzmann tail (of carrier density)
EC
EV
ON State
OFF State
Boltzmann tail
Boltzmann tail
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Due to excellent electrostatics, band gap tunability and direct band gap, GNR is a great
material for Tunnel-FETs…..
Graphene for Tunnel-FET
Y. Khatami, M. Krall, H. Li, C. Xu and K. Banerjee, Device Research Conference, 2010, pp. 65-66.
-0.1 0.0 0.1 0.2 0.3 0.4 0.510
-13
10-11
1x10-9
1x10-7
1x10-5
1x10-3
VDD
=0.5 V
RC =13 k
Lg =20 nm
W1(nm) W2(nm)
1.3 1.3
2.1 1.3
3.3 1.3
4.3 1.3
I DS (
A/m
m)
VGS
(V)
Heterojunction GNRTFET
ION = 1 mA/μm, ION/IOFF = 109,
SS = 10 mV/dec
VDD = 0.5 V, and Lch = 20 nm
Gate Source Drain
W1 W2
E
kBandgap
opening
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
VDD
VOUT
Graphene interconnects
GNRNTFETP+-Source
i-Channel
N-Drain
GNRPTFET
GNRPTFET
Via
GND
N+
PiVIN
VOUT2
Graphene interconnects
Via
Inverter 1
Inverter 2
VG2
VG1
VINVOUT2
VOUTInverter 1
(Unit size)
Inverter 2
(Size=2)
All-Graphene Monolithic Logic Circuits
J. Kang, D. Sarkar, Y. Khatami and K. Banerjee, APL, 103, 2013.
Patterning by
Lithography
Doping
Source and Drain Deposition and
Patterning of
metal and oxide
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Inverter Delay
Inverter Noise Margin Inverter Gain
22nm-CMOS
(Low Power Model)
22nm-CMOS (High
Performance Model)
Performance Evaluation
Power Consumption
All-Graphene
Monolithic Logic
Circuits
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
0 5 10 15 20
-1.0
-0.5
0.0
0.5
1.0
-
Ch
VDS
=0.01 V
EV
EC
S TG BG D
En
erg
y (
eV
)
(b)
Position (nm)0 5 10 15 20
QW
VDS
=0.4 V
S TG BG D
Position (nm)
(d)
EC
EV
0 5 10 15 20
VDS
=0.13 V
Position (nm)
S TG BG D
(c)
Ch
GNR based Negative Differential Resistance (NDR) Device
Bottom Oxide
High peak to valley current ratio (PVCR)
• Top and bottom gates dope the channel electrostatically • Low gap states • Pristine GNRs • No dopants • Bottom gate connected to drain • Fixed voltage on top gate • High current density: 700μA/μm
High PVCR
Y. Khatami, J. Kang, K. Banerjee, APL, 102, 043114, 2013.
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Compact SRAM Cell based on GNR NDR Devices
0.0 0.1 0.2 0.30
1
2
-3
-190.30.2
*
**
0.1
VTG
VDD
VOUT
VBG
TG
BG
p-type
n-type
**
Pull-
Up
Pull-Dow
n
|ID
S|
(mA
)
VOUT (V)
*
Stable points Low voltage operation
• Complimentary devices • Currents matching in
n- and p-type devices • An access transistor
used for read/write • Minimum VDD: Vvalley • n-device keeps VOUT~0 • p-device keeps VOUT~VDD
Y. Khatami, J. Kang, K. Banerjee, APL, 102, 043114, 2013.
NDR-based SRAM
BG
TG
Vout
BG
VDD
GND
TG
N-NDR
P-NDR
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
First Proposal for Tunnel-FET Biosensors: Ultra-Low Power and Ultra-Sensitive
D. Sarkar and K. Banerjee
Weak Current
Source Drain
Channel
EC
EV
ON Current
(high current)
Drain Source Channel
EC
EV
DS
G
receptor molecules
target biomolecules
graphene channel
Before conjugation
DS
G
After conjugation
TFET Biosensor in Research Highlights of Nature Nanotechnology
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Beyond Graphene Electronic Materials ─ TMD Family Transition Metal Dichalcogenides
1.8 eV
WSe2
MoS2
1.1 eV
MoTe2
2.2 eV
SnS2Ec
Ev
1.6 eV
Superconductor Example: NbSe2
Semiconductor (Eg: 1-2 eV) Example: MoS2, WSe2
Half-metal (Eg: 0-1 eV) Example: CrO2, CrS2
Metal Example: VO2, VS2
• Layered material
• Hexagonal lattice
• ~50 members known
• Eg up to 2.2 eV
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
PN
AS
2
00
5
• Demonstration of
exfoliated MoS2
• Measured mobility
0.5 ~ 3 cm2/Vs
• Low gate modulation
6-7 Å
~3.3 Å
Side view 2
Mo
S
Sgap (Van der Waals)
Mo
S
S
Side view 1
zig
zag
armchair
Top view
ΓM
K
Γ
EFi
E-E
F (
eV)
K M K
Eg = 1.8 eV0
2
4
-2
-4
Ec
Ev
k-point
Crystal and Electronic Structures of MoS2
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Synthesis of MoS2 ─ CVD Methods
Keng-ku Liu, et al., Nano letters (2012): 1538-1544.
Najmaei Sina, et al., Nature Materials
(2013): 754-759.
MoO3 + S powders as the reactants
Thermal decomposition of (NH4)2MoSO4
Single crystainllin MoS2 directly grows on dielectric film (Al2O3, BN, SiO2 et al.,)
Lee, Yi‐Hsien, et al., Advanced Materials
24.17 (2012): 2320-2325.
Yongjie Zhan, et al., Small 8.7 (2012): 966-971.
Mo film + S as the reactants
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
• Demonstration of transistor performance boosting by using high-ĸ dielectrics
Contact resistance dominates TMD FET performance (1-3 order higher than that of CMOS)
Applications of TMD materials: TMD Transistors
SS ~ 74 mV/dec
On/Off Ratio ~ 108
Mobility ~ 200 cm2/Vs
(15 after recent
correction..)
ON current = 2.5uA/um
@ Vds = 0.5 V
Na
tu
re
Na
no
20
11
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Three Main Issues in TMD Transistor Applications
Contact
Substrate (dielectric)
x
z dopant
MoS2
Doping
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Text box for
animation use. Do
not move.
Main Issues 1: Contact
A Framework to Evaluate and Optimize Contacts to 2D Semiconductors
J. Kang, D. Sarkar, W. Liu, D. Jena and K. Banerjee, IEDM, 2012, pp. 407-410.
Choosing MetalsStep 1
Interface ModelingStep 2
Vacuum
Metal
TMD xy
Unit Cellz
Optimized
Geometry
Valence
Electron
Density
Partial
Density
of States
Effective
Potential
Step 3
Density Function
Theory (DFT)
Calculation
Mulliken
Population
A
B
C
D E
Step 4
Contact Evaluation
Evac
EC
EV
EF
Metal
EF
TMDTunnel Barrier
Orbital Overlap (Bonding)
Schottky Barrier
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
(a) b
3L
1L
High Performance Monolayer n-type WSe2 FET
Monolayer WSe2 with a bandage of 1.6-1.7 eV Optical contrast and Raman mapping can estimate thickness of few layer WSe2
a
High mobility: 142 cm2/V.s Record On Current : 210 µA/µm
1.6 eV
L: 3.5µm W: 3µm
W. Liu et al., (UCSB), Nano Letters, 2013, Vol. 13, no. 5, pp. 1983-1990, 2013.
2L c
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Main Issues 2: Doping of TMD
Chemical p-doping of single layered WSe2 by NO2
Hui Fang, et al., Nano Lett., 12.7 (2012): 3788-3792.
Currently there is no stable and reliable doping method for TMD semiconductors • chemical doping: volatile • electrostatic doping: raise new questions ─ manufacturability, alignment and additional parasitics
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
receptor molecules
target biomolecules
VG
VDD
First Demonstration of MoS2 FET Biosensor @UCSB
D. Sarkar, W. Liu, X. Xie, A. C. Anselmo, S. Mitragotri and K. Banerjee (under review)
• 74-fold higher sensitivity than graphene • Femto-molar detection • Highly scalable
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Applications of TMD materials: Floating-Gate Transistors based on Graphene/TMD
MoS2 (/WSe2) channel
Graphene floating gate
Gate dielectric (i.e. h-BN)
Graphene electrode
W. Cao, J. Kang, S. Bertolazzi, A. Kis and K. Banerjee (under review).
Graphene as FG • immunite to cell-to-cell interference
Advantages:
TMD as channel • Small Vth roll-off • Small SS
Selected 2D-nanocrystals can significantly extend the lifetime of the FG based memory cell
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Applications of TMD materials: “All-2D” Hybrid Circuit Design Scheme
N-Channel(MoS2)
GND
Interconnect (graphene)
P-Channel(WSe2)
Input
Output
VDD
Gate(graphene)
Dielectric(h-BN)
Interconnect (graphene)
Interconnect (graphene)
Dielectric(h-BN)
Gate(graphene)
• utilize the promising properties of various 2D electronic materials • future ultra-dense high-efficiency and low-power digital circuits • a simple example:
Compact (Stackable) Flexible (Wearable) Transparent
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
All-2D Heterostructures: Lateral & Vertical
Zheng Liu, et al., Nature Nanotechnology, 8,119–124 (2013)
Woo Jong Yu, et al., Nature Materials, 16, (2012)
Vertical 2D inverter: MoS2 as N-device; BSCO as P-device Voltage transfer curve and gain
fabrication of planar graphene/h-BN structure with controlled domain
graphene/h-BN transferred to PDMS
Vin
Vout
GND
VDD
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
A creative child
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
VDD
GND
Vin
Vin
Vout2Vout1
Inverter 1 Inverter 2
All-Graphene Logic CircuitNDR-based SRAM
BG
TG
Vout
BG
VDD
GND
TG
N-NDR
P-NDR
DS
G
GNRTFET Biosensor
We researchers
S
DG
GNRTFET
2D dielectric
2D semiconductor 2D half-metal 2D semi-metal
2D metal
A future 2D “Legoland”
ESSDERC, Bucharest, Sep. 19, 2013. Kaustav Banerjee, UCSB
Acknowledgments
Wei Liu
Postdoctoral Fellow
PhD 2008, Institute of Chemistry-Chinese Academy of Sciences
Hong Li
PhD Sept 2012
now with Micron Technology, R&D group, Idaho
Navin Srivstava
PhD March 2009
now with Mentor Graphics, R&D group, Oregon
Deblina Sarkar
PhD Candidate
Yasin Khatami
PhD Sept 2013
Jiahao Kang
PhD Student
Chuan Xu
PhD June 2012
now with Maxim Integrated Systems, R&D group, Oregon
Xuejun Xie
PhD Student
Wei Cao
PhD Student
NRL Members: http://nrl.ece.ucsb.edu/people