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2. Fundamentals of Logic gates

2.1 LOGIC GATES

We have seen that the foundation of logic design is seated in a well defined

axiomatic system called Boolean algebra, which was shown to be what is known as

a “Huntington system”. In this axiomatic system the definition of AND and OR

operators or functions was set forth and these were found to be well defined

operators having certain properties that allow us to extend their definition to

Hardware applications. These AND and OR operators, sometimes referred to as

connectives, actually suggest a function that can be emulated by some H/w logic

device. The logic Hardware devices just mentioned are commonly referred to as

“gates”.

Keep in mind that the usage of “gate” refers to an actual piece of Hardware

where “function” or “operation” refers to a logic operator AND. On the other hand,

when we refer to a “gate” we are referring directly to a piece of hardware called agate. The main point to remember is ‘Don’t confuse gates with logic operators’.

2.1.1 Basic Logic Gates

Positive and Negative Logic Designation

The binary signals at the inputs or outputs of any gate can have one of the

two values except during transition. One signal levels represents logic 1 and theother logic 0. Since two signal values are assigned two to logic values, there exist

two different assignments of signals to logic.

Logics 1 and 0 are generally represented by different voltage levels. Consider

the two values of a binary signal as shown in Fig. 2.5.1. One value must be higher

than the other since the two values must be different in order to distinguish

between them. We designate the higher voltage level by H and lower voltage level

by L. There are two choices for logic values assignment. Choosing the high-level (H)

to represent logic 1 as shown in (a) defines a positive logic system. Choosing the

low level L to represent logic-1 as shown in (b), defines a negative logic system.

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Fig. 2.5.1

The terms positive and negative are somewhat misleading since both signal

values may be positive or both may be negative. Therefore, it is not signal polarity

that determines the type of logic, but rather the assignment of logic values

according to the relative amplitudes of the signals.

The effect of changing from one logic designation to the other equivalent to

complementing the logic functions because of the principle of duality of Boolean

algebra.

Gate Definition

A ‘gate’ is defined as a multi-input (> 2) hardware device that has a two-level

output. The output level (1–H/0–L) of the gate is a strict and repeatable function of

the two-level (1–H/0–L) combinations applied to its inputs. Fig. 2.5.2 shows a

general model of a gate.

Fig. 2.5.2 The general model of a gate.

The term “logic” is usually used to refer to a decision making process. A logic

gate, then, is a circuit that can decide to say yes or no at the output based upon

inputs. We apply voltage as the input to any gate, therefore the Boolean (logic) 0

and 1 do not represent actual number but instead represent the state of a voltage

variable or what is called its logic level. Sometimes logic 0 and logic 1 may be called

as shown in table below:

Table 2.5.2

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a. OR Gate

The OR gate is sometimes called the “any or all gate”. To show the OR gate

we use the logical symbol in Fig. 2.5.4(a).

b.

c. Fig. 2.5.4 (a) OR gate logic symbol . (b) Practical OR gate circuit.

d.

e. A truth-table for the ‘OR’ gate is shown below according to Fig. 2.5.4(b).

The truth-table lists the switch and light conditions for the OR gate. The

unique output from the OR gate is a LOW only when all inputs are low. The

output column in Table (2.5.4) shows that only the first line generates a 0

while all others are 1.

Table 2.5.4

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f.

g. Fig. 2.5.4(c) shows the ways to express that input A is ORed with input B to

produce output Y.

h.

i. Fig. 2.5.4 (c)

j. Example. Determine the output Y from the OR gate for the given input

waveform shown in Fig. 2.5.4(d).

k.

l. Fig. 2.5.4 (d )m. Solution. The output of an OR gate is determined by realizing that it will

be low only when both inputs are low at the same time. For the inputs the

outputs is low only during period t 2. In remaining time output is 1 as shown

in Fig. 2.5.4(e).

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n.

o. Fig. 2.5.4 (e)

p. We are now familiar with AND and OR gates. At this stage, to illustrate at

least in part how a word statement can be formulated into a mathematical

statement (Boolean expression) and then to hardware network, consider

the following example:

q. Example. Utkarsha will go to school if Anand and Sawan go to school, or

Anand and Ayush go to school.

r. Solution. This statement can be symbolized as a Boolean expression as

follows:

s.

t. The next step is to transform this Boolean expression into a Hardware

network and this is where AND and OR gates are used.

u.

v. The output of gate 1 is high only if both the inputs A and S are high (mean

both Anandand Sawan go to school). This is the first condition for Utkarsha

to go to school.

w. The output of gate 2 is high only if both the inputs A and A.Y are high

(means both Anand and Ayush go to school). This is the second condition

for Utkarsha to go to school.

x. According to example atleast one condition must be fullfilled in order that

Utkarsha goesto school. The output of gate 3 is high when any of the input

to gate 3 is high means at leastone condition is fulfilled or both the inputsto gate 3 are high means both the conditions are fulfilled.

y. The example also demonstrates that Anand has to go to school in any

condition otherwise Utkarsha will not go to school.

z.

b. AND Gate

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Fig. 2.5.3 (c) shows the ways to express

that input A is ANDed with input B to produce

output Y.

Pulsed Operation

In many applications, the inputs to a gate may be voltage that change with time

between

the two logic levels and are called as pulsed waveforms. In studying the pulsed

operation of an AND gate, we consider the inputs with respect to each other in orderto determine the output level at any given time. Following example illustrates this

operation:

Example. Determine the output Y from the AND gate for the given input waveform

shown in Fig. 2.5.3(d).

.

Fig. 2.5.3 (d )

Solution. The output of an AND gate is determined by realizing that it will be

high only when both inputs are high at the same time. For the inputs the outputs is

high only during t 3 period. In remaining times, the outputs is 0 as shown in Fig.2.5.3(e).

Fig. 2.5.3 (e)

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NAND and NOR gates. The NAND and NOR gates are widely used and are

readily available from most integrated circuit manufacturers. A major reason for the

widespread use of these gates is that they are both UNIVERSAL gates, universal in

the sense that both can be used for AND operators, OR operators, as well as

Inverter. Thus, we see that a complex digital system can be completely synthesized

using only NAND gates or NOR gates.

a. NAND Gate

The NAND gate is a NOT AND, or an inverted AND function. The standard

logic symbol for the NAND gate is shown in Fig. (2.5.7a). The little invert

bubble (small circle) on the right end of the symbol means to invert the

output of AND.

b.

Fig. 2.5.7 (a) NAND gate logic symbol (b) A Boolean expression for the

output of a NAND gate.

Figure 2.5.7(b) shows a separate AND gate and inverter being used to

produce the NAND logic function. Also notice that the Boolean expression for

the AND gate, (A.B) and the NAND (A.B) are shown on the logic diagram of

Fig. 2.5.7(b).

The truth-table for the NAND gate is shown in Fig. 2.5.7(c). The truth-table for

the NAND gate is developed by inverting the output of the AND gate. ‘The

unique output from the NAND gate is a LOW only when all inputs are HIGH.

c.

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d. Fig. 2.5.7 (c) Truth-table for AND and NAND gates.

Fig. 2.5.7 (d ) shows the ways to express that input A is NANDed with input B

yielding output Y.

e.f. Fig. 2.5.7 (d )

Example. Determine the output Y from the NAND gate from the given input

waveform

shown in Fig. 2.6.7 (e).

g.

h. Fig. 2.5.7 (e)

Solution. The output of NAND gate is determined by realizing that it will be

low only

when both the inputs are high and in all other conditions it will be high. The

ouput Y is

shown in Fig. 2.5.7(f ).

i.

j. Fig. 2.5.7 (f )

The NAND gate as a UNIVERSAL Gate

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The chart in Fig. 2.5.7(g) shows how would you wire NAND gates to create

any of the other basic logic functions. The logic function to be performed is

listed in the left column of the table; the customary symbol for that function

is listed in the center column. In the right column, is a symbol diagram of howNAND gates would be wired to perform the logic function.

k.

l. Fig. 2.5.7 (g)

m. The NOR gate. The NOR gate is actually a NOT OR gate or an inverted

OR function.

n. The standard logic symbol for the NOR gate is shown in Fig. 2.5.7(h)

o.

p. Fig. 2.5.7 (h) NOR gate logic symbol (i) Boolean expression for the output

of NOR gate. Note that the NOR symbol is an OR symbol with a small

invert bubble on the right side. The NOR function is being performed by an

OR gate and an inverter in Fig. 2.5.7(i). The Boolean function for the OR

function is shown (A + B), the Boolean expression for the final NOR

function is (A + B).q. The truth-table for the NOR gate is shown in Fig. 2.5.7( j). Notice that the

NOR gate truth table is just the complement of the output of the OR gate.

The unique output from the NOR gate is a HIGH only when all inputs are

LOW.

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dd.Fig. 2.5.7 (m)

B . NOR Gate

The NOR gate as a UNIVERSAL gate.

The chart in Fig. 2.5.7(n) shows how would your wire NOR gates to create anyof the other basic logic functions.

Fig. 2.5.7 (n)

2.1.3 Coincidence gates

a. The Exclusive OR Gate

The exclusive OR gate is sometimes referred to as the “Odd but not the even

gate”. It is often shortend as “XOR gate”. The logic diagram is shown in Fig. 2.5.8

(a) with its Boolean expression. The symbol means the terms are XORed together.

Fig. 2.5.8 (a)

The truth table for XOR gate is shown in Fig. 2.5.8 (b). Notice that if any but

not all the inputs are 1, then the output will be 1. ‘The unique characteristic of the

XOR gates that it produces a HIGH output only when the odd no. of HIGH inputs are

present.’

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Y = (AB + AB)C + (AB + AB).C

Y = ABC + ABC + ABC + ABC

The HIGH outputs are generated only when odd number of HIGH inputs are

present (see T.T.)

‘This is why XOR function is also known as odd function’.

Fig. 2.5.8 (e) shows the ways to express that input A is XORed with input B yielding

output Y.

Fig. 2.5.8 (e)

The XOR gate using AND OR-NOT gates.

we know A B = AB + AB

As we know NAND and NOR are universal gates means any logic diagram can

be made using only NAND gates or using only NOR gates.

XOR gate using NAND gates only.

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XOR using NOR gates only. The procedure for implementing any logic

function using only universal gate (only NAND gates or only NOR gates) will be

treated in detail in section 2.6.

Example. Determine the output Y from the XOR gate from the given input

waveform shown in Fig. 2.5.8 (f).

Fig. 2.5.8 (f )

Solution. The output XOR gate is determined by realizing that it will be HIGH

only when the odd number of high inputs are present therefore the output Y is high

for time period t 2 and t 5 as shown in Fig. 2.5.8 (g).

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b. The Exclusive NOR gate

c.

d. The Exclusive NOR gate is sometimes reffered to as the ‘COINCIDENCE’ or

‘EQUIVALENCE’ gate. This is often shortened as ‘XNOR’ gate. The logicdiagram is shown in Fig. 2.5.9 (a).

e.

f. Fig. 2.5.9 (a)

g. Observe that it is the XOR symbol with the added invert bubble on the

output side. The Boolean expression for XNOR is therefore, the invert of

XOR function denoted by symbol O.

h.

i.

j. The truth table for XNOR gate is shown in Fig. 2.5.9 (b).

k.

l. Fig. 2.5.9 (b)

m. Notice that the output of XNOR gate is the complement of XOR truth table.

n. ‘The unique output of the XNOR gate is a LOW only when an odd number of

input are HIGH’.

o.

p. Fig. 2.5.9 (c)

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q.

r. Fig. 2.5.9 (d )

s. To demonstrate this, Fig. 2.5.9 (c) shows a three input XNOR gate logic

symbol and the truth-table 2.5.9 (d ).t. Figure 2.5.9 (e) shows the ways to express that input A is XNORed with

input B yielding

u. output Y.

v.

w.

x. Fig. 2.5.9 (e)

y. Now at this point, it is left as an exercise for the reader to make XNOR gate

using ANDOR-NOT gates, using NAND gates only and using NOR gates

only.z. Example. Determine the output Y from the XNOR gate from the given

input waveform shown in Fig. 2.5.9 (f).

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aa.

bb.Fig. 2.5.9 (f )

cc. Solution. The output of XNOR gate is determined by realizing that it will

be HIGH only when the even-number of high inputs are present, therefore

the output Y is high for time period t 2 and t 5 as shown in Fig. 2.5.9 (g).

dd.ee.F ig. 2.5.9 (g)

ff.

a.The Exclusive NOR gate

The Exclusive NOR gate is sometimes reffered to as the ‘COINCIDENCE’ or

‘EQUIVALENCE’ gate. This is often shortened as ‘XNOR’ gate. The logic diagram

is shown in Fig. 2.5.9 (a).

gg.

hh.Fig. 2.5.9 (a)

ii. Observe that it is the XOR symbol with the added invert bubble on the

output side. The Boolean expression for XNOR is therefore, the invert of

XOR function denoted by symbol O.

jj.

kk.

ll. The truth table for XNOR gate is shown in Fig. 2.5.9 (b).

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mm.

nn.Fig. 2.5.9 (b)

oo.Notice that the output of XNOR gate is the complement of XOR truth table.

pp.‘The unique output of the XNOR gate is a LOW only when an odd number of

input are HIGH’.

qq.

rr. Fig. 2.5.9 (c)

ss.

tt. Fig. 2.5.9 (d )

uu.To demonstrate this, Fig. 2.5.9 (c) shows a three input XNOR gate logic

symbol and the truth-table 2.5.9 (d ).

vv.Figure 2.5.9 (e) shows the ways to express that input A is XNORed with

input B yielding

ww.output Y.

xx.

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yy.

zz. Fig. 2.5.9 (e)

aaa.Now at this point, it is left as an exercise for the reader to make XNOR

gate using ANDOR-NOT gates, using NAND gates only and using NOR gates

only.

bbb.Example. Determine the output Y from the XNOR gate from the given

input waveform shown in Fig. 2.5.9 (f).

ccc.ddd.Fig. 2.5.9 (f )

eee.Solution. The output of XNOR gate is determined by realizing that it will

be HIGH only when the even-number of high inputs are present, therefore

the output Y is high for time period t 2 and t 5 as shown in Fig. 2.5.9 (g).

fff.

ggg.F ig. 2.5.9 (g)

hhh.

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2.2 L OGIC DIAGRAM

Are diagrams in the field of logic, used for representationand to carry out certain types of reasoning.

Basic Logic Diagrams Basic logic diagrams are used to show theoperation of a particular unit or component. Basic logic symbols are shownin their proper relationship so as to show operation only in the most

simplified form possible. Figure 6-24 shows a basic logicdiagram for a serial subtractor. The operation of the unit is

described briefly in the next paragraph. In the basic subtractor infigure 6-24, assume you want to subtract binary 011 (decimal 1) from

binary 100 (decimal 4). At time I o, the 0 input at A and 1 input at B of

inhibitor I1 results in a 0 output from inhibitor I1 and a 1 output frominhibitor I2. The 0 output from I1 and the 1 output from I2 are applied to

OR gate G1

, producing a 1 output from G1

. The 1 output from I2

is alsoapplied to the delay line. The I output from G1 along with the 0 output from

the delay line produces 1 output from I3. The 1 input from G1 and the 0input from the delay line produce a 0 output from inhibitor I4. The 0

output from L and the 1 output from I3 are applied to OR gate G2

producing a 1 output.

At time t1 the 0 inputs on the A and B input linesof I1 produce 0 outputs from I1 and I2. The 0 inputs on bothinput lines of OR gate G1 result in a 0 output from G1. The Iinput applied to the delay line at time to emerges (1 bit timedelay) and is now applied to the inhibit line of 13 producing

an 0 output from I3. The 1 output from the delay line isalso applied to inhibitor I4, and along with the 0 output

from G1 produces a 1 output from I4. The I4 output isrecycled back into the delay line, and also applied to ORgate G2. As a result of the 0 and 1 inputs from I3, and I4,OR gate G2 produces a 1 output. At time t2, the 1 input on

the A line and the 0 input on the B line of I1 produce a 1output from I1 and a 0 output from I2. These outputsapplied to OR gate G1 produce a 1 output from G1, whichis applied to 13 and I4. The delay line now produces a 1

output (recycled in at time t1), which is applied to I3 and I4. The 1 output from the delay line along with the 1 outputfrom G1 produces a 0 output from I3. The 1 output from G1

along with the 1 output from the delay line produces a 0output from I4. With 0 outputs from I3 and I4, OR gate G2

produces a 0 output.

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2.3 Truth Table

A truth table shows how a logic circuit's output responds to various combinations of the inputs,using logic 1 for true and logic 0 for false. All permutations of the inputs are listed on the left,and the output of the circuit is listed on the right. The desired output can be achieved by acombination of logic gates. A truth table for two inputs is shown, but it can be extended to anynumber of inputs. The input columns are usually constructed in the order of binary counting witha number of bits equal to the number of inputs.

Truth table for most commonly used logical operators

Here is a truth table giving definitions of the most commonly used 7 of the 16 possible truth functions of 2 binary variables (P,Q are thus boolean variables):

PQ

T T T T F T T T T

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T F F T T F F T F

F T F T T F T F F

F F F F F T T T T

Key:

T = true, F = false

= AND (logical conjunction)

= OR (logical disjunction)

= XOR (exclusive or)

= XNOR (exclusive nor)

= conditional "if-then"

= conditional "(then)-if"

biconditional or "if-and-only-if" is logically equivalent to : XNOR (exclusive

nor).

Condensed truth tables for binary operators

For binary operators, a condensed form of truth table is also used, where the row headings andthe column headings specify the operands and the table cells specify the result. For exampleBoolean logic uses this condensed truth table notation:

∧ F T

F F F

T F T

∨ F T

F F T

T T T

This notation is useful especially if the operations are commutative, although one canadditionally specify that the rows are the first operand and the columns are the second operand.This condensed notation is particularly useful in discussing multi-valued extensions of logic, as itsignificantly cuts down on combinatoric explosion of the number of rows otherwise needed. Italso provides for quickly recognizable characteristic "shape" of the distribution of the values inthe table which can assist the reader in grasping the rules more quickly.

http://en.wikipedia.org/wiki/Logical_conjunction

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http://en.wikipedia.org/wiki/Exclusive_or

http://en.wikipedia.org/wiki/Exclusive_nor

http://en.wikipedia.org/wiki/Logical_conditional


http://en.wikipedia.org/wiki/If_and_only_if


http://en.wikipedia.org/wiki/Logical_equivalence


http://en.wikipedia.org/wiki/Boolean_logic

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http://en.wikipedia.org/wiki/Boolean_logic

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Truth tables in digital logic

Truth tables are also used to specify the functionality of hardware look-up tables (LUTs) indigital logic circuitry. For an n-input LUT, the truth table will have 2^n values (or rows in theabove tabular format), completely specifying a boolean function for the LUT. By representingeach boolean value as a bit in a binary number , truth table values can be efficiently encoded as

integer values in electronic design automation (EDA) software. For example, a 32-bit integer canencode the truth table for a LUT with up to 5 inputs.

When using an integer representation of a truth table, the output value of the LUT can beobtained by calculating a bit index k based on the input values of the LUT, in which case theLUT's output value is the k th bit of the integer. For example, to evaluate the output value of aLUT given an array of n boolean input values, the bit index of the truth table's output value can be computed as follows: if the ith input is true, let Vi = 1, else let Vi = 0. Then the k th bit of the binary representation of the truth table is the LUT's output value, where k = V0*2^0 + V1*2^1 +V2*2^2 + ... + Vn*2^n.

Truth tables are a simple and straightforward way to encode boolean functions, however giventhe exponential growth in size as the number of inputs increase, they are not suitable for

functions with a large number of inputs. Other representations which are more memory efficientare text equations and binary decision diagrams.

Applications of truth tables in digital electronics

In digital electronics (and computer science, fields of engineering derived from applied logic andmath), truth tables can be used to reduce basic boolean operations to simple correlations of inputsto outputs, without the use of logic gates or code. For example, a binary addition can berepresented with the truth table:

A B | C R

1 1 | 1 0

1 0 | 0 1

0 1 | 0 1

0 0 | 0 0

where

A = First Operand

B = Second Operand

C = Carry

R = Result

This truth table is read left to right:

• Value pair (A,B) equals value pair (C,R).

• Or for this example, A plus B equal result R, with the Carry C.

Note that this table does not describe the logic operations necessary to implement this operation,rather it simply specifies the function of inputs to output values.

In this case it can only be used for very simple inputs and outputs, such as 1's and 0's, however if the number of types of values one can have on the inputs increases, the size of the truth table willincrease.

For instance, in an addition operation, one needs two operands, A and B. Each can have one of two values, zero or one. The number of combinations of these two values is 2x2, or four. So the

http://en.wikipedia.org/wiki/Digital_circuit


http://en.wikipedia.org/wiki/Bit

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http://en.wikipedia.org/wiki/Software


http://en.wikipedia.org/wiki/Array_data_structure

http://en.wikipedia.org/wiki/Exponential_growth

http://en.wikipedia.org/wiki/Binary_decision_diagram


http://en.wikipedia.org/wiki/Bit



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http://en.wikipedia.org/wiki/Array_data_structure

http://en.wikipedia.org/wiki/Exponential_growth

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result is four possible outputs of C and R. If one was to use base 3, the size would increase to3x3, or nine possible outputs.

The first "addition" example above is called a half-adder. A full-adder is when the carry from the previous operation is provided as input to the next adder. Thus, a truth table of eight rows would be needed to describe a full adder 's logic:

A B C* | C R0 0 0 | 0 0

0 1 0 | 0 1

1 0 0 | 0 1

1 1 0 | 1 0

0 0 1 | 0 1

0 1 1 | 1 0

1 0 1 | 1 0

1 1 1 | 1 1

Same as previous, but..

C* = Carry from previous adder

2.4 CIRCUIT MAKING

In order to play with TTL gates, you must have several pieces of equipment. Here's a list of what you will need topurchase:

• A breadboard • A volt-ohm meter (also known as a multimeter )• A logic probe (optional)• A regulated 5-volt power supply • A collection of TTL chips to experiment with• Several LEDs (light emitting diodes) to see outputs of the gates• Several resistors for the LEDs•

Some wire (20 to 28 gauge) to hook things together These parts together might cost between $40 and $60 or so, depending on where you get them.

Let's walk through a few details on these parts to make you more familiar with them:

• As described on the previous page, a breadboard is a device that makes it easy to wire up your circuits.• A volt-ohm meter lets you measure voltage and current easily. We will use it

to make sure that our power supply is producing the right voltage.• The logic probe is optional. It makes it easy to test the state (1 or 0) of a

wire, but you can do the same thing with an LED.• Of the parts described above, all are easy except the 5-volt power supply.

No one seems to sell a simple, cheap 5-volt regulated power supply. Youtherefore have two choices. You can either buy a surplus power supply fromJameco (for something like a video game) and use the 5-volt supply from it,or you can use a little power-cube transformer and then build the regulator yourself. We will talk through both options below.

• An LED (light emitting diode) is a mini light bulb. You use LEDs to see theoutput of a gate.

• We will use the resistors to protect the LEDs. If you fail to use the resistors,the LEDs will burn out immediately.

This equipment is not the sort of stuff you are going to find at the corner store.However, it is not hard to obtain these parts. You have a few choices when trying to purchase the components listedabove:

1. Radio Shack

A resistor and an LED

http://en.wikipedia.org/wiki/Full_adder


http://electronics.howstuffworks.com/led.htm



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http://electronics.howstuffworks.com/inside-transformer.htm




http://electronics.howstuffworks.com/light-bulb.htm

http://electronics.howstuffworks.com/framed.htm?parent=digital-electronics.htm&url=http://www.radioshack.com






http://electronics.howstuffworks.com/light-bulb.htm

http://electronics.howstuffworks.com/framed.htm?parent=digital-electronics.htm&url=http://www.radioshack.com

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2. A local electronics parts store - Most major cities have electronics parts stores, and many cities are blessedwith good surplus electronics stores. If you can find a good surplus store in your area that caters to peoplebuilding their own stuff, then you have found a goldmine.

3. A mail-order house like Jameco - Jameco has been in business for decades, has a good inventory and goodprices. (Be sure to download their PDF catalog or get a paper catalog from them -- it makes it much easier to traverse the Web site.)

The following table shows you what you need to buy, with Jameco part numbers listed.

Part Jameco #

Breadboard 20722

Volt-ohm meter 119212

Logic probe (optional) 149930

Regulated 5-volt power supply See below

7400 (NAND gates) 48979

7402 (NOR gates) 49015

7404 (NOT gates) 49040

7408 (AND gates) 49146

7432 (OR gates) 50235

7486 (XOR gates) 50665

5 to 10 LEDs 94529*

5 to 10 330-ohm resistors 30867

Wire (20 to 28 gauge) 36767

For the Power Supply (optional)

(See next section for details)

Part Jameco #

Transformer (7 to 12 volts, 300ma) 149964

7805 5-volt voltage regulator (TO-220 case) 51262

2 470-microfarad electrolytic capacitors 93817

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27632305-logic-gates

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