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Characterizationofa0.14m

SubmicronNMOSwith

SilvacoTCADSimulatorYeapKimHo1*,IbrahimAhmad2andMuhammadSuhaimiSulong3

1DepartmentofPhysicalSciences,ElectricalandElectronics,

UniversitiTunkuAbdulRahman.2DepartmentofElectrical,Electronics,andSystemsEngineering,

UniversitiKebangsaanMalaysia.3FacultyofElectricalandElectronicsEngineering,

UniversitiTunHusseinOnnMalaysia.

*Corresponding email: [email protected]

Abstract

A0.14mNMOSwassimulatedusingATHENAandATLASmodulesfrom

TCADsimulator.Theelectricalcharacteristicsofthesubmicrondevicewere

studied.Constanteldscalingwasappliedtothefollowingparameters:the

effective channel length, the density of the ion implantation for threshold

voltage(VTH)adjustment,andthegateoxidethickness(TOX).Additional

techniquesimplementedtoavoidshortchanneleffectsinsubmicrondeviceswereshallowtrenchisolation(STI),sidewallspacerdeposition,lightlydoped

drain(LDD)implantation,andretrogradewellimplantation.Theresultsshow

thatretrogradewellimplantationallowedthehighestdensityofthedopantto

fallbelowthesurfaceofthesubstrate.Withtheapplicationofsidewallspac-

erandLDDimplantation,alighterdopedregionwascreatedbeyondthen+

drain/sourcejunction.Asthelayersofmetallizationincreases,itwasobserved

thatdraincurrent(ID)increasedaswell.TheimportantparametersforNMOS

weremeasuredandvalidated.

Keywords:sidewallspacer,LDD,retrogradewell,metallization

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1 INTRODUCTION

ThedensityofachipinMOSVLSI(VeryLargeScaleIntegration)hasbeen

growingtremendously for thepastfewdecades. Oneofthereasonsis due

mainlytosizereductionofatransistor.

Startingoffwith50minthe1960s,thegatechannelofatransistor

hasshrunktolessthan0.18min2000(HongXiao2001).Inthispaper,a

0.14mNMOSwassimulatedand studied.Thedevice fabricationprocess

wasrstsimulatedusingtheATHENAmodulefromtheSilvacoVirtualWafer

Fab(VWF)TCADtools.Theelectricalpropertieswerethenvalidatedwiththe

ATLASmodule.

The performance of a 0.14 m NMOS, which falls within thesubmicronregimes,maybeseverelyaffectedbyshortchanneleffects.Thus,

besidesapplyingconstanteld scalingon theeffectivechannel length(Lg),

gateoxidethickness(TOX),andthresholdvoltage(VTH)adjustimplantation,

additional fabrication techniques have been implemented. Shallow Trench

Isolation (STI), sidewall spacer deposition, Lightly Doped Drain (LDD)

implantation,andretrogradewellimplantationweresomeofthetechniques

appliedtoensureproperoperationofthedevice(Slisheretal.2006).

2 SIMULATION PROCESS WALKTHROUGH

Thesimulationprocesscanbeclassiedinto5differentphases.Theyarewell

formation,deviceisolation,transistormaking,andinterconnection(HongXiao

2001). Initially,apwellistobeformedinthep-typesinglecrystalsilicon

(Si)wafer. Screen oxideis grownon the surfaceofthe substrate. This is

followedbyahighenergyimplantation.Thewaferistiltedandrotatedwhen

theimplantationprocessisperformed.

Theobjectiveofgrowingalayerofscreenoxideandtiltingthewafer

istominimizechannelingeffect;whereas,rotatingthewaferistominimize

shadowing effect. Soon after p well is formed, annealing and drive-in is

performedtorepairthelatticedamage(HongXiao2001).

Next,STIisemployedtoisolateneighbouringdevices.Alayerofpad

oxideisrstgrownviadryoxidation.SiliconNitride(Si3N4)isthendeposited

usingLiquidPlasmaChemicalVaporDeposition(LPCVD).Padoxideactsas

astressbufferwhichavoidscracksonSi3N4;whereas,Si3N4actsasamaskforetching.Photoresistisdepositedandphotolithographyisappliedtodene

theactiveregionofthedevice.Subsequently,Si3N4andpadoxideareetched.

Afterthephotoresistisstripped,ReactiveIonEtching(RIE)is implemented

toform trenchesat the2sidesof the active region. Athinlayerofbarrier

oxideis grownin the trenches.Thetrenches are lledupwithoxideusing

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Tetra-Ethyl-Oxy-Silane (TEOS)CVD process. The layerof barrier oxide

prevents impurities from diffusing into the substrate during TEOS CVD

process(HongXiao2001).Theoxideatthesurfaceofthesubstrateisremoved

usingChemicalMechanicalPolishing(CMP)process.STIiscompletedafter

annealingisperformedandSi3N4maskandpadoxideareetched.

Gate oxide is grown via dry oxidation. VTH adjust implantation

is then performed, afterwhich, the substrate undergoes annealing. Next,

polysilicongateis formedbydepositingandetchinga layerofpolysilicon.

The substrate is, again, annealed. LDD is then implanted to suppress hot

electroneffect(HongXiao2001).Subsequently,Si3N4isdepositedviaCVD

process.SidewallspacersareformedbyetchingtheSi3N4lm.Sourceanddrainjunctionsareimplantedonthe2sidesoftheactiveregionsandannealing

processisappliedtoactivatethedopants.Assoonasthebasicstructureofan

NMOSiscompleted,alayeroftitaniumisdepositedonthesubstratesurface.

RapidThermalAnnealing(RTA)isthenemployedtoformsilicideonthegate.

Atransistorisfabricatedsoonaftertheunreactedtitaniumisetched.

Interconnections in between transistors are to be performed with

metallization. A layer of Boron Phosphor Silicate Glass (BPSG) is rst

depositedtoformPremetalDielectric(PMD).PMDactsasaninsulatorfor

multilevelinterconnection(Quirk2001).Afterannealing,BPSGisetchedto

formsource/draincontacts.Therstlevelofmetallizationisdevelopedby

depositing and etching aluminum (Al) on the contacts.An almost similar

procedureistobeperformedonthesecondlevelofinterconnection.Anotherlayer of BPSG, known as Intermetal Dielectric (IMD) (Quirk 2001) is

deposited.ThesimulationprocessiscompletedwhentheredundantIMDis

etched.AsummaryoftheparametersusedinNMOSfabricationisshownin

Table1.

3 SIMULATION RESULTS AND DISCUSSION

A. The 0.14 m NMOS

Figure1showsthecompletecrosssectionofNMOS.Asclearlyshownby

thedopantdensitydistributions,retrogradewelltechniquehasresultedinthe

highestdopantdensityconcentratedacertaindepthbelowthesurfaceofthe

substrate.Itcanalsobeobservedthat,LDDimplantationformedarelatively

lighterndopedregionrightbeneaththesidewallspacers.

B. Retrograde Well

Ascomparedtoconventionalwellformation, inwhich, thehighestdopant

densityliesatthesurfaceofthesubstrate,retrogradewellsusehighenergy

implantationtoplacethehighestdopantdensityatacertaindesiredsubstrate

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depth.Figure2showstheboronconcentrationversusthesubstratedepthof

thesimulated0.14mNMOS.

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Asthechannellengthreduces,thedepletionregionencompassesthe

drainjunctiontendstoextendsfarthertowardsthesource.Atatime,ifthe

depletionregionsofbothdrainandsourcejunctionsmerge,aspuriouscurrent

pathisinevitablyformed.Thegatevoltagewillhavelostitscontroloverthe

currentowinbetweenthe2junctions.Suchphenomenonisknownaspunch

through(Sze1988).

Anincreaseofdopingconcentrationinthesubstrateusingretrograde

wellimplantationallows thedepletionregionsdrain/source junctionsto be

scaleddown.Hence,punchthroughcanbeavoidedwhenthedepletionre-

gionsstayatareasonabledistanceapart.

Figure1.0.14mNMOS.

Figure2.Borondensityversussubstratedepthofa0.14mNMOS.

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C. LDD Implantation

When the dimension of the device shrinks and the supply voltage remain

constant,theelectriceldgeneratedinthesubstratewillincrease.Asaresult,

theelectronsalongthechannelmightgainsufcientenergytobeinjectedonto

thegateoxide.Thechargingofthegateoxidecauseslongtermdegradationon

thedevice.Suchissueisknownashotelectroneffect(Sze1988).

In order to avoidthe electronsfrom gaining sufcient energy,the

electriceldalongthedrainregionistobereduced.Onewayofdoingsois

toimplantalighterndopantsurroundingthen+drain/sourceimplants.As

showninFigure3,thenetdopingofLDDimplantationbeneaththesidewall

spacersisrelativelyshallowcomparedtothedrain/sourceimplants.

D. NMOS Parameters

ImportantparameterssuchasVTH,TOX,andLgaremeasuredandextracted

fromtheATLASmodule. Theparameters arecomparedwith thestandard

parameters published by International Technology Roadmap for

Semiconductor(ITRS)andBerkeleyPredictiveTechnologyModel(BPTM)

(Berkeley2006). Sinceonlythestandardparametersfor 70nm,0.10m,

0.13m,and0.18mNMOSdevicewerepublishedinITRSandBPTM,

polynomial regression technique (using MATLAB tools) was applied to

acquire the required parameters for a 0.14 m NMOS. Table 2 shows a

comparisonbetweentheparametersextractedfromATLASandthestandard

parametersobtainedusingpolynomialregression.ItcanbeobservedthattheparametersextractedfromtheATLASmodulefallwithinthetolerancerange

ofthestandardparametersobtainedthroughregressiontechnique.Therefore,

thesimulationresultsarevalidated.

E. Electrical Characteristics

The ID-VD and ID-Vgelectrical characteristics curves were plotted using

ATLASmodule.

Figure 4 and 5 shows the NMOS ID-VD relationshipsbefore and

after metallization 2; whereas, Figure 6 and 7 shows the NMOS ID-Vg

relationshipsbeforeandaftermetallization2.ThedifferencesinIDbefore

and after second level interconnection were compared. The results are

summarizedinTable3and4.

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Figure3.LDDImplantation.

Figure4.NMOSID-VDrelationshipbeforemetallization2isdeposited.

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Figure5.NMOSID-VDrelationshipaftermetallization2isdeposited.

Figure6.NMOSID-Vgrelationshipbeforemetallization2isdeposited.

As can be seen from Figure 4 to Figure 7, the current- voltage

characteristic curves remain unchanged even though a second layer of

metallizationhasbeendepositedontothedevice.

Nevertheless, ID increases after metallization 2. Since power

consumption is directly proportional to ID, the simulation shows that by

increasingthelevelofmetallization,powerconsumptiontendtoincreaseas

well.

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Figure7.NMOSID-Vgrelationshipaftermetallization2isdeposited.

Table3ComparisonofIdbeforeandafterLevel2MetallizationinId-VdNMOS

Graph.

Table4ComparisonofIdbeforeandafterLevelMetallizationinId-VgNMOS

Graph.

4 CONCLUSION

A0.14msubmicronNMOShasbeensuccessfullysimulatedandvalidated.

The result shows that retrograde well technique controls the highest

concentration dopant at certain depth of the substrate; whereas, LDD

implantation reduces the concentration of n dopant beneath the sidewall

spacers.Thesetechniquesareeffectiveinminimizingshortchanneleffects.

The current-voltage characteristic curves also show that as the level of

interconnectionincreases,IDincreasesaswellwhichshouldresultinhigher

powerconsumption.

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REFERENCES

[1] Berkeley. (2006).Berkeley Predictive TechnologyModel (BPTM).

http://www-device.eecs.berkeley.edu/~ptm.

[2] Chen,C.K.,Chen,C.L.,Gouker,P.M.,Wyatt,P.W.,Yost,D.R.,

Burns,J.A.,V.Suntharalingam,Fritze,M.andKeast,C.L.(2001).

FabricationofSelfAligned90nmFullyDepletedSOICMOSSLOT

FETs.IEEEElectronDeviceLetters.Vol.22(7).pp.345-347.

[3] Hong Xiao. (2001). Introduction to SemiconductorManufacturing

Technology.NewJersey:PrenticeHall.

[4] Ponomarev,Y.V.,Stolk,P.A.,Dachs,C.J.J.,andMontree,A.H.

(2000). A 0.13 m Poly-SiGe Gate CMOS Technology for Low- VoltageMixedSignalApplications. IEEETrans. ElectronDevices.

Vol.47(7).pp.1507-1513.

[5] Quirk, M. & Serda, J. (2001). Semiconductor Manufacturing

Technology.NewJersey:PrenticeHall.

[6] Slisher,D.K.,Filippi,R.G.,Storaska,D.W.andGay,A.H.(2006).

ScalingofSiMOSFETsforDigitalApplications.http://nina.ecse.rpi.

edu/shur/advanced/examples

[7] Sze,S.M.(1988).VLSITechnology.SecondEdition.NewYork:Mc

GrawHill.

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