24-bit,192-khzsampling, enhanced multilevel, … .ti.com pcm1780, pcm1781, pcm1782 sles132b– march...

FEATURES APPLICATIONS

DESCRIPTION

PCM1780, PCM1781, PCM1782

SLES132B–MARCH 2005–REVISED AUGUST 2006

24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma,Audio Digital-to-Analog Converter

• A/V Receivers• 24-Bit Resolution• DVD Movie Players• Analog Performance (VCC = 5 V):• DVD Add-On Cards For High-End PCs– Dynamic Range: 106 dB• DVD Audio Players– SNR: 106 dB, Typical• HDTV Receivers– THD+N: 0.002%, Typical• Car Audio Systems

– Full-Scale Output: 3.9 Vp-p, Typical• Other Applications Requiring 24-Bit Audio

• 4×/8× Oversampling Digital Filter:– Stop-Band Attenuation: –50 dB– Pass-Band Ripple: ±0.04 dB The PCM1780/81/82 is a CMOS, monolithic,

• Sampling Frequency: 5 kHz to 200 kHz integrated circuit, which includes stereodigital-to-analog converters and support circuitry in a• System Clock: 128 fS, 192 fS, 256 fS, 384 fS,small 16-lead SSOP package. The data converters512 fS, 768 fS, 1152 fS With Autodetectuse TI’s enhanced multilevel delta-sigma architecture• Software Control (PCM1780, PCM1782): to achieve excellent dynamic performance and

– Accepts 16-, 18-, 20-, and 24-Bit Audio Data improved tolerance to clock jitter. ThePCM1780/81/82 accepts industry standard audio– Formats: Right-Justified, I2S, anddata formats with 16- to 24-bit data, providing easyLeft-Justifiedinterfacing to audio DSP and decoder chips.

– Digital Attenuation: Mode Selectable Sampling rates up to 200 kHz are supported. The• 0 dB to –63 dB, 0.5 dB/step PCM1780/82 provides a full set of

user-programmable functions through a three-wire• 0 dB to –100 dB, 1 dB/stepserial control port, which supports register write– Digital De-Emphasis functions. The PCM1781 provides a subset of

– Digital Filter Rolloff: Sharp or Slow user-programmable functions through four controlpins.– Soft Mute

– Zero Flags for Each Output The PCM1780 is pin-compatible with the PCM1680(8-channel DAC).– Open-Drain Output Zero Flag (PCM1782)

• Hardware Control (PCM1781):– I2S and 16-Bit Word, Right-Justified– Digital De-Emphasis– Soft Mute– Zero Flag for L-, R-Channel Common

Output• Power Supply: 5-V Single Supply• Small, 16-Lead SSOP Package (150 mil)• Pin-Compatible with PCM1680

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2005–2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PCM1780, PCM1781, PCM1782


This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage canrange from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible todamage because very small parametric changes could cause the device not to meet its published specifications.

over operating free-air temperature range (unless otherwise noted) (1)

PCM1780, PCM1781, PCM1782

Supply voltage VCC –0.3 V to 6.5 V

Input voltage –0.3 V to VCC + 0.3 V, < 6.5 V

Input current (any pins except supplies) ±10 mA

Ambient temperature under bias – 40°C to 125°C

Storage temperature – 55°C to 150°C

Junction temperature 150°C

Lead temperature (soldering) 260°C, 5 s

Package temperature (IR reflow, peak) 260°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

over operating free-air temperature range

MIN NOM MAX UNIT

Digital and analog supply voltage, VCC 4.5 5 5.5 V

Digital input logic family TTL

System clock 8.192 36.864 MHzDigital input clock frequency

Sampling clock 32 192 kHz

Analog output load resistance 5 kΩ

Analog output load capacitance 50 pF

Digital output load capacitance 20 pF

Operating free-air temperature, TA –25 85 °C

All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 24 Bits

DATA FORMAT

PCM1780, Right-justified, I2S,PCM1782 left-justifiedAudio data interface formatPCM1781 I2S, right-justified

PCM1780, 16-, 18-, 20-, 24-bitPCM1782 selectable

Audio data bit length16–24-bit I2S, 16-bitPCM1781 right-justified

Audio data format MSB-first, 2s complement

fS Sampling frequency 5 200 kHz

128 fS, 192 fS, 256 fS, 384 fS,System clock frequency 512 fS, 768 fS, 1152 fS

2 Submit Documentation Feedback




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PCM1780, PCM1781, PCM1782


ELECTRICAL CHARACTERISTICS (continued)All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data (unless otherwise noted)


DIGITAL INPUT/OUTPUT

Logic family TTL compatible

VIH 2Input logic level Vdc

VIL 0.8

IIH(1) VIN = VCC 10

IIL (1) VIN = 0 V –10Input logic current µA

IIH(2) VIN = VCC 65 100

IIL (2) VIN = 0 V –10

VOH(3) IOH = –1 mA 2.4

Output logic level VdcVOL

(4) IOL = 1 mA 0.4

DYNAMIC PERFORMANCE (5)

VOUT = 0 dB, fS = 48 kHz 0.002% 0.006%

VOUT = 0 dB, fS = 96 kHz, system 0.003%THD+N Total harmonic distortion + noise clock = 256 fSVOUT = 0 dB, fS = 192 kHz, system 0.004%clock = 128 fSEIAJ, A-weighted, fS = 48 kHz 100 106

A-weighted, fS = 96 kHz, system 104Dynamic range clock = 256 fS dB

A-weighted, fS = 192 kHz, system 102clock = 128 fSEIAJ, A-weighted, fS = 48 kHz 100 106

A-weighted, fS = 96 kHz, system 104SNR Signal-to-noise ratio clock = 256 fS dB

A-weighted, fS = 192 kHz, system 102clock = 128 fSfS = 48 kHz 97 103

Channel separation fS = 96 kHz, system clock = 256 fS 101 dB

fS = 192 kHz, system clock = 128 fS 100

DC ACCURACY

% ofGain error ±1 ±6 FSR

% ofGain mismatch, channel-to-channel ±1 ±6 FSR

Bipolar zero error V OUT = 49% of VCC at BPZ input ±30 ±80 mV

ANALOG OUTPUT

Output voltage Full scale (–0 dB) 0.78 VCC Vp-p

Bipolar zero voltage 0.49 VCC Vdc

Load impedance AC-coupled load 5 kΩ

DIGITAL FILTER PERFORMANCE

Filter Characteristics (Sharp Rolloff)

Pass band ±0.04 dB 0.454 fSStop band 0.546 fSPass-band ripple 0.04 dB

Stop-band attenuation Stop band = 0.546 fS –50 dB

(1) Pins 5, 6, 7, 8: SCK, DATA, BCK, LRCK(2) Pins 2, 3, 4: MS, MC, MD (PCM1780/PCM1782). Pins 1, 2, 3, 4: FMT, DEMP0, DEMP1, MUTE (PCM1781)(3) Pins 1, 16: ZEROL, ZEROR (PCM1780). Pin 16: ZEROA (PCM1781)(4) Pins 1, 16: ZEROL, ZEROR (PCM1780/PCM1782). Pin 16: ZEROA (PCM1781)(5) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™.

3Submit Documentation Feedback





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DEVICE INFORMATION

PIN ASSIGNMENTS

ZEROR/ZEROA

VOUTL

VOUTR

VCOM

AGND

VCC

NC

NC

16

15

14

13

12

11

10

9

ZEROL/NA

MS

MC

MD

SCK

DATA

BCK

LRCK

PCM1780/PCM1782(TOP VIEW)

1

2

3

4

5

6

7

8

ZEROA

VOUTL

VOUTR

VCOM

AGND

VCC

NC

TEST

16

15

14

13

12

11

10

9

FMT

DEMP0

DEMP1

MUTE

SCK

DATA

BCK

LRCK

PCM1781(TOP VIEW)

1

2

3

4

5

6

7

8

P0014-01

PCM1780, PCM1781, PCM1782


ELECTRICAL CHARACTERISTICS (continued)All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data (unless otherwise noted)


Filter Characteristics (Slow Rolloff, PCM1780/PCM1782)

Pass band ±0.5 dB 0.198 fSStop band 0.884 fSPass-band ripple ±0.5 dB

Stop-band attenuation Stop band = 0.884 fS –35 dB

Delay time 20/fS s

De-emphasis error ±0.1 dB

ANALOG FILTER PERFORMANCE

at 20 kHz –0.02Frequency response dB

at 44 kHz –0.07

POWER SUPPLY REQUIREMENTS

VCC Voltage range 4.5 5 5.5 Vdc

fS = 48 kHz 25 40

ICC Supply current fS = 96 kHz, system clock = 256 fS 30 mA


fS = 48 kHz 125 200

Power dissipation fS = 96 kHz, system clock = 256 fS 150 mW


TEMPERATURE RANGE

TA Operation temperature –25 85 °C

θJA Thermal resistance 115 °C/W






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PCM1780, PCM1781, PCM1782


DEVICE INFORMATION (continued)TERMINAL FUNCTIONS—PCM1780/PCM1782

TERMINALI/O DESCRIPTION

NAME NO.

AGND 12 – Ground

BCK 7 I Audio data bit clock input (1)

DATA 6 I Audio data digital input (1)

LRCK 8 I Audio data left and right clock input (1)

MC 3 I Mode control clock input (1) (2)

MD 4 I Mode control data input (1) (2)

MS 2 I Mode control select input (1) (2)

NC 9, 10 – No connection

SCK 5 I System clock input (1)

VCC 11 – Power supply, 5-V

VCOM 13 – Common voltage decoupling

VOUTL 15 O Analog output for L-channel

VOUTR 14 O Analog output for R-channel

ZEROL/NA 1 O Zero flag output for L-channel / No assign (3)

ZEROR/ZEROA 16 O Zero flag output for R-channel / Zero flag output for L- and R-channels(3)

(1) Schmitt-trigger input(2) Pulldown(3) Open-drain output (PCM1782)

TERMINAL FUNCTIONS—PCM1781

TERMINALI/O DESCRIPTION

NAME NO.

AGND 12 – Ground

BCK 7 I Audio data bit clock input (1)

DATA 6 I Audio data digital input (1)

DEMP0 2 I De-emphasis control (1) (2)

DEMP1 3 I De-emphasis control (1) (2)

FMT 1 I Data format select (1) (2)

LRCK 8 I Audio data left and right clock input (1)

MUTE 4 I Soft mute control (1) (2)

NC 10 – No connection

SCK 5 I System clock input (1)

TEST 9 – Test pin for factory use. Must be LOW or open (1) (2)

VCC 11 – Power supply, 5-V

VCOM 13 – Common voltage decoupling

VOUTL 15 O Analog output for L-channel

VOUTR 14 O Analog output for R-channel

ZEROA 16 O Zero flag output for L- and R-channels

(1) Schmitt-trigger input(2) Pulldown






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Power Supply

EnhancedMultilevel

Delta-SigmaModulator

VOUTL

4/8Oversampling

DigitalFilterWith

FunctionControl

AudioSerialPort

BCK

LRCK

DATA

SerialControl

Port

Zero Detect

(TEST)

SCK SystemClock

Manager

MC (DEMP1)

MS (DEMP0)

Output Ampand

Low-Pass Filter

MD (MUTE)

DAC

VCOM

System Clock

AG

ND

VC

C

ZE

RO

R/Z

ER

OA

(1)

(ZE

RO

A)

ZE

RO

L/N

A(1

)Output Amp

andLow-Pass Filter

DACVOUTR

B0030-01

(FMT)

PCM1780, PCM1781, PCM1782


Functional Block Diagram

(1) Open-drain output for the PCM1782

NOTE: Signal names in parentheses ( ) are for the PCM1781.






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TYPICAL PERFORMANCE CURVES

Digital Filter (De-Emphasis Off)

Frequency [ × fS]

−0.05

−0.04

−0.03

−0.02

−0.01

0.00

0.01

0.02

0.03

0.04

0.05

0.0 0.1 0.2 0.3 0.4 0.5

Am

plitu

de –

dB

G002Frequency [ × fS]

−140

−120

−100

−80

−60

−40

−20

0

0 1 2 3 4

Am

plitu

de –

dB

G001

Frequency [ × fS]

−140

−120

−100

−80

−60

−40

−20

0

0 1 2 3 4

Am

plitu

de –

dB

G003Frequency [ × fS]

−5

−4

−3

−2

−1

0

1

2

3

4

5

0.0 0.1 0.2 0.3 0.4 0.5

Am

plitu

de –

dB

G004

PCM1780, PCM1781, PCM1782


All specifications at TA = 25°C, VCC = 5 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted

FREQUENCY RESPONSE PASS-BAND FREQUENCY RESPONSE(SHARP ROLLOFF) (SHARP ROLLOFF)

Figure 1. Figure 2.

FREQUENCY RESPONSE TRANSITION CHARACTERISTICS(SLOW ROLLOFF) (SLOW ROLLOFF)

Figure 3. Figure 4.






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TYPICAL PERFORMANCE CURVES (Continued)

De-Emphasis Filter

f – Frequency – kHz

−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14

De-

Em

phas

is E

rror

– d

B

fS = 32 kHz

G006

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

0 2 4 6 8 10 12 14


De-

Em

phas

is L

evel

– d

B

fS = 32 kHz

G005


−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14 16 18 20

De-

Em

phas

is E

rror

– d

B

fS = 44.1 kHz

G008f – Frequency – kHz

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

0 2 4 6 8 10 12 14 16 18 20

De-

Em

phas

is L

evel

– d

B

fS = 44.1 kHz

G007

PCM1780, PCM1781, PCM1782



DE-EMPHASIS DE-EMPHASIS ERROR

Figure 5. Figure 6.


Figure 7. Figure 8.






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−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14 16 18 20 22

De-

Em

phas

is E

rror

– d

B

fS = 48 kHz

G010f – Frequency – kHz

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0

0 2 4 6 8 10 12 14 16 18 20 22

De-

Em

phas

is L

evel

– d

B

fS = 48 kHz

G009

Analog Filter

−70

−60

−50

−40

−30

−20

−10

0

10

f − Frequency − kHz

Am

plitu

de −

dB

1 100 1k 10k

G011

10

PCM1780, PCM1781, PCM1782




Figure 9. Figure 10.

ANALOG FILTER PERFORMANCE

Figure 11.






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Analog Dynamic Performance

Supply Voltage Characteristics

VCC − Supply V oltage − V

4.50 4.75 5.00 5.25 5.50

TH

D+N

− T

otal

Har

mon

ic D

isto

rtion

+ N

oise

− %

G012

0.001

0.01

VCC – Supply Voltage – V

96

98

100

102

104

106

108

110

4.50 4.75 5.00 5.25 5.50

Dyn

amic

Ran

ge

– d

B

G013

VCC – Supply V oltage – V

96

98

100

102

104

106

108

110

4.50 4.75 5.00 5.25 5.50

SN

R −

Sig

nal-t

o-N

oise

Rat

io –

dB

G014VCC – Supply Voltage – V

96

98

100

102

104

106

108

110

4.50 4.75 5.00 5.25 5.50

Ch

ann

el S

epar

atio

n –

dB

G015

PCM1780, PCM1781, PCM1782



THD+N DYNAMIC RANGEvs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE


SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE







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Temperature Characteristics

TA − Free-Air T emperature − °C−25 0 25 50 75

TH

D+N

− T

otal

Har

mon

ic D

isto

rtion

+ N

oise

− %

G016

0.001

0.01

TA − Free-Air T emperature − °C

96

98

100

102

104

106

108

110

−25 0 25 50 75

Dyn

amic

Ran

ge –

dB

G017

TA − Free-Air T emperature − °C

96

98

100

102

104

106

108

110

−25 0 25 50 75

SN

R −

Sig

nal-t

o-N

oise

Rat

io –

dB

G018TA − Free-Air T emperature − °C

96

98

100

102

104

106

108

110

−25 0 25 50 75

Cha

nnel

Sep

arat

ion

– dB

G019

PCM1780, PCM1781, PCM1782



THD+N DYNAMIC RANGEvs vs

TEMPERATURE TEMPERATURE


SIGNAL-TO-NOISE RATIO CHANNEL SEPARATIONvs vs

TEMPERATURE TEMPERATURE







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SYSTEM CLOCK AND RESET FUNCTIONS

System Clock Input

tw(SCKH)

System Clock

tw(SCKL)

2 V

0.8 V

H

LSystem ClockPulse Cycle

Time(1)

T0005A08

PCM1780, PCM1781, PCM1782


The PCM1780/81/82 requires a system clock for operating the digital interpolation filters and multileveldelta-sigma modulators. The system clock is applied at the SCK input (pin 5). Table 1 shows examples ofsystem clock frequencies for common audio sampling rates.

Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important touse a clock source with low phase jitter and noise. TI’s PLL170x family of multiclock generators is an excellentchoice for providing the PCM1780/81/82 system clock.

Table 1. System Clock Frequencies for Common Audio Sampling Frequencies

SAMPLING SYSTEM CLOCK FREQUENCY (fSCK), MHzFREQUENCY 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1152 fS

8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216

16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432

32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864

44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 – (1)

48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 – (1)

88.2 kHz 11.2896 16.9344 22.5792 33.8688 – (1) – (1) – (1)

96 kHz 12.288 18.432 24.576 36.864 – (1) – (1) – (1)

192 kHz 24.576 36.864 – (1) – (1) – (1) – (1) – (1)

(1) This system clock frequency is not supported for the given sampling frequency.

(1) 1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS

PARAMETER MIN TYP MAX UNIT

tw(SCKH) System clock pulse duration, HIGH 7 ns

tw(SCKL) System clock pulse duration, LOW 7 ns

Figure 20. System Clock Input Timing






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Power-On-Reset Functions

Reset Reset Release

VCC

3.7 V3 V

2.2 V

Internal Reset

System Clock

T0014-06

0 V

Don’t Care 3072 System Clocks

Audio Serial Interface

Audio Data Formats and Timing

PCM1780, PCM1781, PCM1782


The PCM1780/81/82 includes a power-on-reset function. Figure 21 shows the operation of this function. With thesystem clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. Theinitialization sequence requires 3072 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V). After theinitialization period, the PCM1780/82 is set to its reset default state, as described in the Mode Control Registersection of this data sheet.

During the reset period (3072 system clocks), the analog output is forced to the common voltage (VCOM), orVCC/2. After the reset period, the internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCKare provided continuously, the PCM1780/81/82 provides the proper analog output with a group delaycorresponding to the input data.

Figure 21. Power-On-Reset Timing

The audio serial interface for the PCM1780/81/82 consists of a three-wire synchronous serial port. It includesLRCK (pin 8), BCK (pin 7), and DATA (pin 6). BCK is the serial audio bit clock, and it is used to clock the serialdata present on DATA into the serial shift register of the audio interface. Serial data is clocked into thePCM1780/81/82 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latchserial data into the internal registers of the serial audio interface.

Both LRCK and BCK should be synchronous with the system clock. Ideally, it is recommended that LRCK andBCK be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can beoperated at 32, 48, or 64 times the sampling frequency.

Internal operation of the PCM1780/81/82 is synchronized with LRCK. Accordingly, internal operation of thedevice is suspended when the sampling rate clock, LRCK, is changed or SCK and/or BCK is interrupted at leastfor three bit-clock cycles. If SCK, BCK, and LRCK are provided continuously after this suspended condition, theinternal operation is resynchronized automatically within a period of less than 3/fS. External resetting is notrequired.

The PCM1780/82 supports industry-standard audio data formats, including right-justified, I2S, and left-justified.The PCM1781 supports I2S and 16-bit-word, right-justified. The data formats are shown in Figure 22. Dataformats are selected for the PCM1780/82 using the format bits, FMT[2:0], located in control register 20, and areselected for the PCM1781 using the FMT pin. The default data format is 24-bit, left-justified. All formats requirebinary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audiointerface.






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LRCK

(2) I2S Data Format; L-Channel = LOW , R-Channel = HIGH

MSB LSB

1/fS

(= 32 fS, 48 fS, or 64 fS)

18-Bit Right-Justified, BCK = 48 fS or 64 fS

1/fS

(1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW

(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW

MSB LSB


MSB LSB


1/fS

(= 32 fS, 48 fS or 64 fS)

(= 32 fS, 48 fS, or 64 fS)

LSB


16-Bit Right-Justified, BCK = 32 fS

LSB

L-Channel R-Channel

BCK

DATA 14 15 16 14 15 16

14 15 16 14 15 16

16 17 18

DATA

DATA

DATA

DATA

1 2 3 16 17 18

18 19 20 1 2 3 18 19 20

22 23 24 1 2 3

MSB LSB

MSB LSB

LSB

MSB LSB

1 2 3 14 15 16

14 15 16

1 2 3 16 17 18

1 2 3 18 19 20

22 23 24

MSB LSB

1 2 3 22 23 24

L-Channel R-ChannelLRCK

BCK

DATA 1 2 3 1 2

MSB

N–2 NN–1

LSB

1 2 3

MSB

N–2 NN–1

LSB

L-Channel R-ChannelLRCK

BCK

DATA 1 2 3 N–2 NN–1 1 2 3 N–2 NN–1 1 2

MSB LSB LSBMSB

T0009-02

MSB

1 2 3

MSB

1 2 3

MSB

1 2 3

PCM1780, PCM1781, PCM1782


Figure 22. Audio Data Input Formats






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t(BCH)

DATA

t(BCL)t(LS)

t(BCY) t(LH)

t(DH)

t(DS)

LRCK

BCK

T0010-03

PCM1780, PCM1781, PCM1782


PARAMETER MIN UNIT

t(BCY) BCK pulse cycle time 1/(32 fS), 1/(48 fS), 1/(64 fS)(1)

t(BCH) BCK pulse duration, HIGH 35 ns

t(BCL) BCK pulse duration, LOW 35 ns

t(LS) LRCK setup time to BCK rising edge 10 ns

t(LH) LRCK hold time to BCK rising edge 10 ns

t(DS) DATA setup time 10 ns

t(DH) DATA hold time 10 ns

(1) fS is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).

Figure 23. Audio Interface Timing






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OVERSAMPLING RATE CONTROL

ZERO FLAGS (PCM1780/82)

Zero-Detect Condition

Zero-Flag Outputs

ZERO FLAG (PCM1781)

HARDWARE CONTROL (PCM1781)

PCM1780, PCM1781, PCM1782


The PCM1780/81/82 automatically controls the oversampling rate of the delta-sigma D/A converters with thesystem clock frequency. The oversampling rate is set to 64× oversampling with an 1152-fS, 768-fS, or 512-fSsystem clock, to 32× oversampling with a 384-fS or 256-fS system clock, or to 16× oversampling with a 192-fS or128-fS system clock.

Zero detection for each output channel is independent from the other. If the data for a given channel remains ata 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.

Each channel has a corresponding zero-flag pin, ZEROL (pin 1) or ZEROR (pin 16). Given that a zero-detectcondition exists for one or more channels, the zero-flag pins for those channels are set to a logic-1 state. Thezero-flag pins can be used to operate external mute circuits, or used as status indicators for a microcontroller,audio signal processor, or other digitally controlled function.

The active polarity of the zero-flag outputs can be inverted by setting the ZREV bit of control register 22 to 1.The reset default is active-high output, or ZREV = 0.

The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register 22to 1. The reset default is for independent L-channel and R-channel zero flags, or AZRO = 0.

On the PCM1782, ZEROL and ZEROR are open-drain outputs.

The PCM1781 has a zero-flag pin, ZEROA (pin 16). ZEROA is the L-channel and R-channel common zero-flagpin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clockperiods), ZEROA is set to a logic-1 state.

The digital functions of the PCM1781 are capable of hardware control. Table 2 shows selectable formats,Table 3 shows de-emphasis control, and Table 4 shows muting control.

Table 2. Data Format Selection

FMT (PIN 1) DATA FORMAT

LOW 16- to 24-bit, I2S format

HIGH 16-bit right-justified

Table 3. De-Emphasis Control

DEMP1 (PIN 3) DEMP0 (PIN 2) DE-EMPHASIS FUNCTION

LOW LOW OFF

LOW HIGH 48-kHz de-emphasis ON

HIGH LOW 44.1-kHz de-emphasis ON

HIGH HIGH 32-kHz de-emphasis ON

Table 4. Mute Control

MUTE (PIN 4) MUTE STATUS

LOW Mute OFF

HIGH Mute ON






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SOFTWARE CONTROL (PCM1780/82)

Register Write Operation

MSB

0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D000

LSB

Register Index (or Address) Register Data

R0001-01

IDX0 D7 D6 D4D5 D3 D2 D1 D00

MS

MC

MD X 0 IDX6XIDX1IDX2IDX3IDX4IDX5IDX6X

T0048-01

Control Interface Timing Requirements

PCM1780, PCM1781, PCM1782


The PCM1780/82 has many programmable functions that can be controlled in the software control mode; thefunctions are controlled by programming the internal registers using MS, MC, and MD.

The serial control interface is a 3-wire serial port which operates asynchronously to the audio serial interface.The serial control interface is used to program the on-chip mode registers. The control interface includes MD(pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the

serial bit clock, used to shift data into the control port. MS is the select input, used to enable the mode controlport.

All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data wordformat. The most significant bit must be a 0. Seven bits, labeled IDX[6:0], set the register index (or address) forthe write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specifiedby IDX[6:0].

Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 stateuntil a register needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are thenprovided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle hascompleted, MS is set to logic 1 to latch the data into the indexed mode control register.

Figure 24. Control Data Word Format for MD

Figure 25. Register Write Operation

Figure 26 shows a detailed timing diagram for the serial control interface. These timing parameters are criticalfor proper control port operation.






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t(MCH)

MS

t(MSS)

LSB

t(MCL)

t(MHH)

t(MSH)

t(MCY)

t(MDH)

t(MDS)

MC

MD

T0013-03

PCM1780, PCM1781, PCM1782


PARAMETER MIN UNIT

t(MCY) MC pulse cycle time 100 ns

t(MCL) MC low-level time 50 ns

t(MCH) MC high-level time 50 ns

t(MHH) MS high-level time 3/(256 × fS)(2) ns

t(MSS) MS falling edge to MC rising edge 20 ns

t(MSH) MS hold time(1) 20 ns

t(MDH) MD hold time 15 ns

t(MDS) MD setup time 20 ns

(1) MC rising edge for LSB to MS rising edge

(2) fS: sampling rate

Figure 26. Control Interface Timing






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MODE CONTROL REGISTERS (PCM1780/82)

User-Programmable Mode Controls

Register Map

PCM1780, PCM1781, PCM1782


The PCM1780/82 includes a number of user-programmable functions, which are accessed via control registers.The registers are programmed using the serial control interface, which was previously discussed in the SoftwareControl section of this data sheet. Table 5 lists the available mode control functions, along with their resetdefault conditions and associated register index.

The mode control register map is shown in Table 6. Each register includes an index (or address) indicated bythe IDX[6:0] bits.

Table 5. User-Programmable Mode Controls

FUNCTION RESET DEFAULT REGISTER BIT(S)

Digital attenuation control, 0 dB to –63 dB in 0.5-dB 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]steps

Soft mute control Mute disabled 18 MUT[2:0]

Oversampling rate control ×64, ×32, ×16 18 OVER

Soft reset control Reset disabled 18 SRST

DAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]

De-emphasis function control De-emphasis disabled 19 DM12

De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]

Audio data format control 24-bit, left-justified 20 FMT[2:0]

Digital filter rolloff control Sharp rolloff 20 FLT

Digital attenuation mode select 0 to –63 dB, 0.5 dB/step 21 DAMS

Output phase select Normal Phase 22 DREV

Zero-flag polarity select High 22 ZREV

Zero-flag function select L-, R-channels independent 22 AZRO

Table 6. Mode Control Register MapIDX REGIST B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(B8–B14) ER

10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10

11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20

12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1

13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1

14h 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0

15h 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV DAMS

16h 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV 0 AZRO ZREV DREV






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Register Definitions

PCM1780, PCM1781, PCM1782


B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10


REGISTER 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20

ATx[7:0]: Digital Attenuation Level Setting

Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2)

Default value: 1111 1111b

ATx[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING

DAMS = 0 DAMS = 1

1111 1111b 255 0 dB, no attenuation (default) 0 dB, no attenuation (default)

1111 1110b 254 –0.5 dB –1 dB

1111 1101b 253 –1 dB –2 dB

: : : :

1001 1100b 156 –49.5 dB –99 dB

1001 1011b 155 –50 dB –100 dB

1001 1010b 154 –50.5 dB Mute

: : :

1000 0010b 130 –62.5 dB Mute

1000 0001b 129 –63 dB Mute

1000 0000b 128 Mute Mute

: : : :

0000 0000b 0 Mute Mute

Each DAC channel (VOUTL or VOUTR) includes a digital attenuation function. The attenuation level can be setfrom 0 dB to R dB, in S-dB steps. Changes in attenuator levels are made by incrementing or decrementing byone step (S dB) every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, theattenuation level can be set to infinite attenuation (or mute).

R (range) and S (step) are –63 and 0.5 for DAMS = 0 and –100 and 1 for DAMS = 1, respectively. The DAMSbit is defined in register 21.

The attenuation data for each channel can be set individually. The attenuation level can be calculated using thefollowing formula:

Attenuation level (dB) = S • (ATx[7:0]DEC – 255)

where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128 with DAMS = 0, or for ATx[7:0]DEC = 0through 154 with DAMS = 1, the attenuation level is set to infinite attenuation (mute).






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PCM1780, PCM1781, PCM1782



REGISTER 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST OVER RSV RSV RSV RSV MUT2 MUT1

NOTE: RSV indicates a reserved bit that should be set to 0.

MUTx: Soft Mute Control

Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).

Default value: 0

MUTx = 0 Mute disabled (default)

MUTx = 1 Mute enabled

The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DACoutputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute isdisabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, thedigital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, oneattenuator step (S dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. The step size,S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1.

By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmedattenuation level.

OVER: Oversampling Rate Control

Default value: 0

System clock frequency = 512 fS, 768 fS, or 1152 fSOVER = 0 ×64 oversampling (default)

OVER = 1 ×128 oversampling (applicable only if sampling clock frequency ≤ 24 kHz)

System clock frequency = 256 fS or 384 fSOVER = 0 ×32 oversampling (default)


System clock frequency = 128 fS, 192 fSOVER = 0 ×16 oversampling (default)


The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters.

Setting OVER = 1 is recommended under the following conditions:• System clock frequency = 512 fS, 768 fS, or 1152 fS, and sampling clock frequency ≤ 24 kHz• System clock frequency = 256 fS or 384 fS and sampling clock frequency ≤ 48 kHz• System clock frequency = 128 fS or 192 fS and sampling clock frequency ≤ 96 kHz

SRST: Reset

Default value: 0

SRST = 0 Reset disabled (default)

SRST = 1 Reset enabled

The SRST bit is used to enable or disable the soft reset function. The operation is the same as for thepower-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRSTfunction. All registers are initialized.






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PCM1780, PCM1781, PCM1782



REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1


DACx: DAC Operation Control

Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).

Default value: 0

DACx = 0 DAC operation enabled (default)

DACx = 1 DAC operation disabled

The DAC operation controls are used to enable and disable the DAC outputs, VOUTL and VOUTR. WhenDACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATApin. When DACx = 1, the corresponding output is set to the dc common voltage (VCOM), equal to VCC/2.

DM12: Digital De-Emphasis Function Control

Default value: 0

DM12 = 0 De-emphasis disabled (default)

DM12 = 1 De-emphasis enabled

The DM12 bit is used to enable or disable the digital de-emphasis function. Refer to the plots shown in theTypical Performance Curves section of this data sheet.

DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function

Default value: 00

DMF[1:0] De-Emphasis Sample Rate Selection

00 44.1 kHz (default)

01 48 kHz

10 32 kHz

11 Reserved

The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it isenabled.






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PCM1780, PCM1781, PCM1782



REGISTER 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0


FMT[2:0]: Audio Interface Data Format

Default value: 101

FMT[2:0] Audio Data Format Selection

000 24-bit right-justified format, standard data




100 I2S format, 16 to 24 bits

101 Left-justified format, 16 to 24 bits (default)

110 Reserved

111 Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface. The preceding table showsthe available format options.

FLT: Digital Filter Rolloff Control

Default value: 0

FLT = 0 Sharp rolloff (default)

FLT = 1 Slow rolloff

The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloffselections are available: sharp and slow. The filter responses for these selections are shown in the TypicalPerformance Curves section of this data sheet


REGISTER 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV DAMS


DAMS: Digital Attenuation Mode Select

Default value: 0

DAMS = 0 Fine step, 0.5 dB/step for 0 to –63 dB range (default)

DAMS = 1 Wide range, 1 dB/step for 0 to –100 dB range

The DAMS bit is used to select the digital attenuation mode.






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PCM1780, PCM1781, PCM1782



REGISTER 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV 0 AZRO ZREV DREV


DREV: Output Phase Select

Default value: 0

DREV = 0 Normal output (default)

DREV = 1 Inverted output

The DREV bit allows the user to control the phase of the analog output signal.

ZREV: Zero-Flag Polarity Select

Default value: 0

ZREV = 0 Zero-flag pins HIGH at a zero detect (default)

ZREV = 1 Zero-flag pins LOW at a zero detect

The ZREV bit allows the user to select the polarity of the zero-flag pins.

AZRO: Zero Flag Function Select

Default value: 0

AZRO = 0 Pin 1: ZEROL; zero-flag output for L-channel

Pin 16: ZEROR; zero-flag output for R-channel

AZRO = 1 Pin 1: NA; not assigned

Pin 16: ZEROA; zero-flag output for L-/R-channel

The AZRO bit allows the user to select the function of zero-flag pins.






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ANALOG OUTPUTS

VCOM Output

–

–

VCOM

OPA337

+

10 µF+

PCM1780/81/82

Buffered V COM

VCC

VOUTX†

+

PCM1780/81/82

AV 1, where A VR2R1

VCOM

† X = L or R

1/2OPA2353

+

VCC

2

31

C1

R3

R2

C2

R1

10 µF+

(a) Using V COM to Bias a Single-Supply Filter Stage

(b) Using a V oltage Follower to Buffer V COM When Biasing Multiple NodesS0054-01

R4

R5

PCM1780, PCM1781, PCM1782


The PCM1780/81/82 includes two independent output channels, VOUTL and VOUTR. These are unbalancedoutputs, each capable of driving 3.9 Vp-p typical into a 5-kΩ ac-coupled load. The internal output amplifiers forVOUTL and VOUTR are biased to the dc common voltage, equal to 0.5 VCC.

The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energypresent at the DAC outputs due to the noise-shaping characteristics of the PCM1780/81/82 delta-sigma D/Aconverters. The frequency response of this filter is shown as ANALOG FILTER in the Typical PerformanceCurves section. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level formany applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Furtherdiscussion of DAC post-filter circuits is provided in the Application Information section of this data sheet.

One unbuffered common voltage output pin, VCOM (pin 13), is brought out for decoupling purposes. This pin isnominally biased to the dc common voltage, equal to VCC/2. This pin can be used to bias external circuits.Figure 27 shows an example of using the VCOM pin for external biasing applications.

Figure 27. Biasing External Circuits Using the VCOM Pin






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APPLICATION INFORMATION

Connection Diagrams

ZEROL/NA 16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

MS

MC

MD

SCK

DATA

BCK

LRCK

ZEROR/ZEROA

NC

VOUTL

VOUTR

VCOM

AGND

NC

VCC

PCM1780PCM1782

Mode Control

L-Ch OUT

R4

R3

R2

R1

PCM Audio Data

System Clock

Zero Mute Control

+

Post LPFC4

R-Ch OUT

+

Post LPF

C3

+

C20 V

5 V+

C1

FMT 16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

DEMP0

DEMP1

MUTE

SCK

DATA

BCK

LRCK

ZEROA

TEST

VOUTL

VOUTR

VCOM

AGND

NC

VCC

PCM1781

De-EmphasisL-Ch OUT

R4

R3

R2

R1

PCM Audio Data

System Clock

Zero Mute Control+

Post LPFC4

R-Ch OUT

+

Post LPF

C3

+

C20 V

5 V+

C1

S0055-01

Format

Mute

C1: 0.1-µF Ceramic and 10- µF ElectrolyticC2: 10-µF ElectrolyticC3, C4: 4.7-µF to 10-µF ElectrolyticR1−R4: 22 Ω to 100 Ω

PCM1780, PCM1781, PCM1782


A basic connection diagram is shown in Figure 28, with the necessary power supply bypassing and decouplingcomponents. TI recommends using the component values shown in Figure 28 for all designs.

The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. Theseries resistor combines with the stray PCB and device input capacitance to form a low-pass filter which reduceshigh-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.

Figure 28. Basic Connection Diagram






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Power Supplies and Grounding

D/A Output Filter Circuits

–2

31

OPA2134

+VOUT

R4

C2

C1R3

R2

R1

VIN

AV R2R1

S0053-01

PCB LAYOUT GUIDELINES

PCM1780, PCM1781, PCM1782


APPLICATION INFORMATION (continued)

The PCM1780/81/82 requires a 5-V supply for VCC.

Proper power supply bypassing is shown in Figure 28. The 0.1-µF ceramic capacitor and the 10-µF electrolyticcapacitor are recommended.

Delta-sigma D/A converters use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR)performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. Theout-of-band noise must be low-pass filtered in order to provide optimal converter performance. This isaccomplished by a combination of on-chip and external low-pass filtering.

Figure 27(a) and Figure 29 show the recommended external low-pass active filter circuits for single- anddual-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB)circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature.For more information regarding MFB active filter design, see Dynamic Performance Testing of Digital Audio D/AConverters (SBAA055), available from the TI Web site at http://www.ti.com.

Figure 29. Dual-Supply Filter Circuit

A typical PCB floor plan for the PCM1780/81/82 is shown in Figure 30. A ground plane is recommended, withthe analog and digital sections being isolated from one another using a split or cut in the circuit board. ThePCM1780/81/82 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short,direct connections to the digital audio interface and control signals originating from the digital section of theboard.

Separate power supplies are recommended for the digital and analog sections of the board. This prevents theswitching noise present on the digital supply from contaminating the analog power supply and degrading thedynamic performance of the PCM1780/81/82. In cases where a common 5-V supply must be used for theanalog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog anddigital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 31shows the recommended approach for single-supply applications.





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Digital Logicand

AudioProcessor

Digital Power

+VD DGND

Digital Section Analog Section

Return Path for Digital Signals

Analog Power

+VSAGND –VS+5VA

DigitalGround

AnalogGround

OutputCircuits

PCM1780/81/82

AGND

VCC

B0031-01

VDD

Digital Section Analog Section

RF Choke or Ferrite BeadPower Supplies

CommonGround

OutputCircuits

AGND

VCC

+VS+5V –VSAGND

PCM1780/81/82

B0032-01

Digital Logicand

AudioProcessor

PCM1780, PCM1781, PCM1782


APPLICATION INFORMATION (continued)

Figure 30. Recommended PCB Layout

Figure 31. Single-Supply PCB Layout






PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

PCM1780DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -20 to 85 PCM1780

PCM1780DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS& no Sb/Br)


PCM1780DBQR ACTIVE SSOP DBQ 16 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM PCM1780



PCM1781DBQG4 ACTIVE SSOP DBQ 16 75 Green (RoHS& no Sb/Br)








(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

http://www.ti.com/product/PCM1780?CMP=conv-poasamples#samplebuy








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PACKAGE OPTION ADDENDUM

www.ti.com 24-Apr-2015

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

PCM1780DBQR SSOP DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1



PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCM1780DBQR SSOP DBQ 16 2000 367.0 367.0 35.0

PCM1781DBQR SSOP DBQ 16 2000 367.0 367.0 35.0

PCM1782DBQR SSOP DBQ 16 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

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PACKAGE OUTLINE

C

TYP-.244.228-6.195.80[ ]

.069 MAX[1.75]

14X .0250[0.635]

16X -.012.008-0.300.21[ ]

2X.175[4.45]

TYP-.010.005-0.250.13[ ]

0 - 8-.010.004-0.250.11[ ]

(.041 )[1.04]

.010[0.25]

GAGE PLANE

-.035.016-0.880.41[ ]

A

NOTE 3

-.197.189-5.004.81[ ]

B

NOTE 4

-.157.150-3.983.81[ ]

SSOP - 1.75 mm max heightDBQ0016ASHRINK SMALL-OUTLINE PACKAGE

4214846/A 03/2014

NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MO-137, variation AB.

116

.007 [0.17] C A B

98

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

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EXAMPLE BOARD LAYOUT

.002 MAX[0.05]ALL AROUND

.002 MIN[0.05]ALL AROUND

(.213)[5.4]

14X (.0250 )[0.635]

16X (.063)[1.6]

16X (.016 )[0.41]


4214846/A 03/2014

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

OPENINGSOLDER MASK METAL

SOLDER MASKDEFINED

LAND PATTERN EXAMPLESCALE:8X

SYMM

1

8 9

16

SEEDETAILS

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EXAMPLE STENCIL DESIGN

16X (.063)[1.6]

16X (.016 )[0.41]

14X (.0250 )[0.635]

(.213)[5.4]


4214846/A 03/2014

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:8X

SYMM

SYMM

1

8 9

16

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