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ABSTRACT

Complementary Metal Oxide Silicon (CMOS) plays an increasingly important role in the

global integrated circuit industry. Whether systems are high speed, high density, low

power or low cost, CMOS technology finds ubiquitous use in the majority of leading

edge commercial applications. Design and simulation of CMOS integrated circuits is

supported by well developed design tools. A significant task to be mastered in todays

world is to take a specification, turn it into a design, enter the design into a CAD system

and test it.

Our project deals with the design and simulation of an integrated circuit at physical

description level. The project started off with an extensive study to gain a firm

understanding of CMOS technology, circuit design and layout. The application and

verification of these concepts was seen for some basic gates and simple logic circuits at

the logic level as well as layout level with the help of the backend PC tools Dsch3 and

Microwind3. With this background, we went ahead with the design and optimization of

an Arithmetic Logic Unit (ALU).

The report that we are presenting is quite in accordance with the flow of our project.

The first chapter presents some information illustrating the technology scale down. The

second chapter discusses the MOS technology which serves as the basis of the CMOS

technology, which is discussed in the next chapter, which also gives an insight into the

fabrication techniques. Chapter 4 includes actual gates and small circuits implemented

and optimized using the Microwind tool. The role of interconnects in integrated circuit

performance has considerably increased with the technology scale down. The resistance

and capacitance effects associated with interconnects and the methods and steps

implemented to minimize the area of the layout are put forth in chapter 6. Chapter 7

deals with power consumption and dissipation of CMOS circuits. The methods we haveimplemented to minimize power dissipation in our chip are explained.

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Mode select inputs Active low inputs and outputs

H = high voltage

L = low voltage

* Each bit shifted to next more significant position

Arithmetic operations expressed in twos compliment notation

5.2 ARITHMETIC LOGIC UNITS

When the mode control input (M) is High, all internal carriers are inhibited and the

device performs logic operations on the individual bits as listed. When the Mode Control

Input is LOW, the carriers are enabled and the device performs arithmetic operations on

the two 4-bit words. The device incorporates full internal carry lookahead and provides

for either ripple carry between devices using Cn+4 output, or for carry lookahead between

packages using signals P (Carry Propagate) and G (Carry Generate). P and G are notaffected by carry in. When speed requirements are not stringent it can be used in a simple

ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of

the next unit. For high-speed operation the device is used in conjunction with the 182

carry lookahead circuit. One carry lookahead package is required for each group of four

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181 devices. Carry lookahead can be provided at various levels and offers high-speed

capability over extremely long word lengths.

The A=B output from the device goes HIGH when all four F/ outputs are high and can be

used to indicate logic equivalence over 4 bits when the unit is in subtract mode. The A=B

output is open collector and can be wired AND with other A=B outputs to give a

comparison for more than 4 bits. The A=B signal can also be used with the Cn+4 signal to

indicate A>B and A

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