(2.1 protocol driven interface validation based on ... · 11/22/2011 · 1 2 3 4 test forum 2011...

© GOEPEL electronic 2011

TEST FORUM 2011Nov 22-23, 2011, Tuusula, Finland

Protocol Driven Interface Validation

Based On

Processor Emulation Test

Presenter: Jan Heiber ([email protected])

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NTF 201111/22/2011 2

1

2

3

Status of Bus Interface Testing

Intro - µP Assisted Procedures

Available System Solutions

Presentation Contents

4 Summary and Outlook

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Facts on Interface Testing using BScan

Boundary Scan is well proven for testing digital edge connector signals

Boundary Scan resources are required on both ends, directly or buffered

Mature ATPG and Pin-Level diagnostic tools are available

AC coupled and serial high speed interfaces are testable by IEEE1149.6

Boundary Scan must be implemented on chip and board level

Static/slow speed testing only, limited coverage for dynamic faults

Background Information

1

TAP

I/F Signals

BScan

IC

IEEE1149.1/.6 Signals

Edge connector

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Paradigm change for I/F technologies …

1

Rapid growing GBit bus applications for high speed Communication

Bus speed is doubling every 36 months average

On-Chip Bus I/F with limited low level protocol access and no dot6

External PHY typically doesn’t support dot6

2000 - 2015

Bu

s s

peed

[G

Bit

]

0,1

1

10

100

#G

Bit

ap

plicati

on

s

PCIe 4.0

Thunderbolt

10GigE

USB3.0

PCIe1.0

1GigE

USB2.0

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Fault Coverage trends via IEEE 1149.1/.6

Fault coverage for Bus I/F test on modern boards via IEEE1149.1/.6 is declining continuously.

This is caused by growing use of GBit I/F

200x199x 201x

Average real world BScan Fault coverage quality for digital bus I/F

Critical Trend

Situation

Fau

lt c

overag

e

1

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Searching for answers…

Current Test Problems

1

Substitution of parallel bus I/F by serial wire architectures

Continuously growing speed in the domain of GBit transfers

Routing and testing of GBit signals becomes critical like RF signals

Digital failure models getting non effective due to analogue failure nature

Boundary Scan via dot6 is typically not available

New IEEE standards could solve the problem but they are not available yet

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Some Thoughts …

Conclusions

Testing of modern I/F with serial GBit architecture via BScan is typically impossible

Key challenges are the high speed and the analogue nature of signal connections

Features like predictive fault coverage, ATPG and precise diagnostics are needed

1

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2 Intro - µP Assisted Procedures

2

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Boundary Scan vs. Processor Emulation

µP Emulation I/F

2

Boundary Scan I/F

• Static pin electronics • BScan cells define vectors• Serially controlled pin interface • Scalable number of pins• Arbitrary static signal timing• Arbitrary vector definition per pin

• Dynamic pin electronics• µP defines vectors• Parallel controlled pin interface• Fixed number of pins• Rigid dynamic signal timing• just Address / Data bus controllable

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Interconnection of µP Core and Bus I/F

Test Access ready by design

No special DfT rules necessary

Real Time functional Test via protocol

Advanced diagnostics tests possible

External Loop back or dedicated H/W

Pro‘s

2

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

H/S Bus I/F

Legacy Bus I/F

Legacy I/O PortsSystem Bus I/F

External Bus Devices

Flash Components

SRAM / DRAM

Peripheral I/O Ports

H/S Bus I/F

Aux Resources

Control Hardware

External Loop back

Bus I/F Test

Hardware

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Method by emerging standard IEEEP1687

IEEE1149.1 / IEEE1687 Access

IEEE 1687 controlled Bit Error Rate Tester (BERT) as a embedded Instument

Signal validation and Interconnection Test of Interface by embedded Test Instrumentation

compliant to IEEE1687

TAP

2

I/F Signals

Edge connector

External Loop back

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Progress with handicaps …

Conclusions

Emulation Test offers the needed test speed but need handling of protocol layers

Potential fault coverage is higher than BScan Test but diagnostics quality is lower

Need for System solutions to support advanced Emulation Test and emerging standards

2

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3 Available System Solutions

3

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Solution #1: Special coded Test Routine

3

JTAG Emulator

Executable

Test Routine Development with native s/w Tool chain

Debugging of s/w and h/w via Emulator

Download into Flash and Program Execution

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

H/S Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


H/S Bus I/F

Aux Resources

External Loop back

O/S and PC with O/S and Bus I/F

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Solution #2: Use of native Firmware + HIL

3

JTAG Emulator

Executable

Firmware Development with native s/w Tool chain

Hardware In the Loop Test via external ATE

Download into Flash and Program Execution

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

H/S Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


H/S Bus I/F

Aux Resources

ATE for HIL test

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Solution #3: Advanced I/F test with ATPG

3

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

H/S Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


H/S Bus I/F

Aux Resources

protocol Externalprotocol

test H/W

Test Program

ATPG for protocol Test Generation

Failure diagnostics on Pin group level by system

software

Program Execution using the µP Core and external

H/W in interaction

Advanced JTAG/BScan Hardware

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Comparison of System Solutions Placeholder

Features

Unified BScan/Emulation test commands

True Interlaced BScan/Emulation operations

Predictive Fault coverage calculation

Automated Test Program Generation

Use of native MCU tool chain

Manually s/w Source coding

Full control of protcol layer tests

Automated Pin group level Diagnostics

Unified hardware for BScan and Emulation

Total Programming and Test execution time

Flash firmware programming needed

System class

Special coded Test Routine

ATPGNative Firm-ware + HIL

no

no

yes

yes

no

no

no

no

High

yes

no

yes

yes

no

no

possible

possible

yes

yes

low

no

yes

possible for HIL Tests

no

yes

yes

no

no

no

no

High

yes

no

3

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4 Summary and Outlook

4

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Higher Test Quality …

Boundary Scan + Emulation Test

Project Development Time

Test

Co

verag

e

Digital Interconnections

Functional Real Time test ofGbit interconnections

4

Processor Emulation enables higher fault coverage and pin group level diagnostics

Boundary Scan

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NTF 201111/22/2011 20

Quo Vadis Interface Testing…

Conclusions and forecast

Testing of GBit I/F via BScan IEEE1149.1/.6 is problematic due to high signal speed

Emulation Test enables high fault coverage but has limits in diagnostics precision

New standard IEEEP1687 will drive forward further test methodologies like BERT

4

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More Information…

Further readings and references

[1] Jan Heiber – Boundary Scan versus Emulation Test Proceedings of the Nordic Test Forum 2008, Tallinn

[2] Heiko Ehrenberg and Thomas Wenzel – Combining Boundary Scan and JTAG Emulation for advanced structural test and diagnostics

White Paper, GOEPEL electronics, 2009

[3] IEEE P1687 – Access and Control of InstrumentationEmbedded within a Semiconductor Device.

4

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Thank you for your attention.

Any questions?

For further information please use

following contact information

Jan Heiber [email protected] www.goepel.com

Scandinavia +45-8748-0608

Germany +49-3641-6896-0

(2.1 protocol driven interface validation based on ... · 11/22/2011 · 1 2 3 4 test forum 2011...

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