2019 nepp etw: examination of reliability and single event ... - berg... · to be presented by...

To be presented by Melanie D. Berg at the NASA Electronic Parts and Packaging Program (NEPP) Electronics Technology Workshop (ETW), NASA Goddard Space Flight Center in Greenbelt, MD, June 17-20, 2019 and published on nepp.nasa.gov .

Examination of Reliability and Single Event Effects in Field Programmable Gate Array Devices: Microsemi RT4G150-CG1657M

(RTG4) Update 2019

Melanie Berg: SSAI Inc. in support of the NEPP Program and NASA/[email protected]

Michael Campola: NASA/GSFCHak Kim: SSAI Inc.

Anthony Phan: SSAI Inc.Scott Stansberry: SSAI Inc.

National Aeronautics and Space Administration

NEPP Electronics Technology WorkshopJune 17-20, 2019

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Acronyms

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Acronym Definition 1MB 1 Megabit3D Three Dimensional 3DIC Three Dimensional Integrated CircuitsACE Absolute Contacting EncoderAHB Advanced high performance busADC Analog to Digital Converter AEC Automotive Electronics CouncilAES Advanced Encryption StandardAMD Advanced Micro Devices IncorporatedAMS Agile Mixed SignalARM Acorn Reduced Instruction Set Computer MachineAXI Advanced extensible interfaceBGA Ball Grid ArrayBRAM Block Random Access MemoryBTMR Block triple modular redundancyCAN Controller Area NetworkCBRAM Conductive Bridging Random Access MemoryCCC RTG4 clock conditioning circuitCCI Correct Coding InitiativeCGA Column Grid ArrayCMOS Complementary Metal Oxide Semiconductor

CN Xilinx ceramic flip-chip (CF and CN) packages are ceramic column grid array (CCGA) packages

COTS Commercial Off The Shelf CRC Cyclic Redundancy CheckCRÈME Cosmic Ray Effects on Micro ElectronicsCRÈME MC Cosmic Ray Effects on Micro Electronics Monte CarloCSE Crypto Security EngineerCU Control UnitDC Direct currentDCU Distributed Control UnitDDR Double Data Rate (DDR3 = Generation 3; DDR4 = Generation 4)DFF Flip-flopDMM Digital MultimeterDMA Direct Memory AccessDSP Digital Signal ProcessingDSPI Dynamic Signal Processing InstrumentDTMR Distributed triple modular redundancyDual Ch. Dual ChannelDUT Device under testECC Error-Correcting CodeEDAC Error detection and correctionEEE Electrical, Electronic, and Electromechanical EMAC Equipment Monitor And ControlEMIB Multi-die Interconnect BridgeEPCS Extended physical coding layerESA European Space AgencyeTimers Event TimersETW Electronics Technology Workshop FCCU Fluidized Catalytic Cracking UnitFeRAM Ferroelectric Random Access MemoryFinFET Fin Field Effect TransistorFIR Finite impulse response filterFPGA Field Programmable Gate Array FPU Floating Point UnitFY Fiscal Year Gb GigabitGbps Gigabit per secondGCR Galactic Cosmic Ray GEO geostationary equatorial orbitGIC Global Industry ClassificationGOMACTech Government Microcircuit Applications and Critical Technology ConferenceGPIO General purpose input/outputGPIB General purpose interface busGPU Graphics Processing UnitGRC NASA Glenn Research CenterGSFC Goddard Space Flight Center

Acronym Definition GSN Goal Structured NotationGTH/GTY Transceiver TypeGTMR Global TMRHALT Highly Accelerated Life Test HAST Highly Accelerated Stress TestHBM High Bandwidth MemoryHDIO High Density Digital Input/OutputHDR High-Dynamic-RangeHiREV High Reliability Virtual Electronics CenterHMC Hybrid Memory CubeHPIO High Performance Input/OutputHPS High Pressure SodiumHSTL High speed transceiver logicI/F interfaceI/O input/outputI2C Inter-Integrated Circuiti2MOS Microsemi second generation of Rad-Hard MOSFETIC Integrated CircuitI-Cache independent cacheJFAC Joint Federated Assurance CenterJPEG Joint Photographic Experts GroupJPL Jet propulsion laboratory

JTAG Joint Test Action Group (FPGAs use JTAG to provide access to their programming debug/emulation functions)

KB Kilobyte

L2 Cache independent caches organized as a hierarchy (L1, L2, etc.)

LCDT NEPP low cost digital tester

LEO Low Earth Orbit

LET Linear energy transferL-mem Long-MemoryLANL Los Alamos National LaboratoryLP Low PowerLUT Look-up tableLVCMOS Low-voltage Complementary Metal Oxide Semiconductor LVDS Low-Voltage Differential SignalingLVTTL Low –voltage transistor-transistor logicLTMR Local triple modular redundancyLW HPS Lightwatt High Pressure SodiumM/L BIST Memory/Logic Built-In Self-TestMil-STD Military standardMAPLD Military Aerospace Programmable Logic DeviceMFTF Mean fluence to failureμPROM Micro programmable read-only memoryμSRAM Micro SRAMMil/Aero Military/AerospaceMIPI Mobile Industry Processor InterfaceMMC MultiMediaCardMOSFET Metal-Oxide-Semiconductor Field-Effect TransistorMP MicroprocessorMP MultiportMPFE Multiport Front-EndMPSoC Multiprocessor System on a chipMPU Microprocessor UnitMsg messageMTTF Mean time to failureNAND Negated AND or NOT ANDNASA National Aeronautics and Space Administration NEPP NASA Electronic Parts and Packaging NOR Not OR logic gateOCM On-chip RAMOSC-TMR-PLL Embedded triple modular redundant phase locked loopOSC Oscillator

PC Personal ComputerPCB Printed Circuit Board

Acronym Definition PCIe Peripheral Component Interconnect Express

PCIe Gen2 Peripheral Component Interconnect Express Generation 2Pconfiguration SEU cross-section of configurationPfunctional_logic SEU cross-section of functional logic

PHY Physical layerPLL Phase Locked LoopPLOL Phase Locked Loop loss of lockPMA Physical Medium AttachmentPOR Power on resetPPM Parts per millionProc. ProcessingPS-GTR High Speed Bus InterfacePSEFI SEU cross-section from single event functional interruptsPsystem System SEU cross-sectionQDR quad data rateQFN Quad Flat Pack No LeadQML Qualified manufactures listQSPI Serial Quad Input/OutputRC Resistor capacitorR&M Reliability and MaintainabilityRAM Random Access MemoryReRAM Resistive Random Access MemoryRGB Red, Green, and BlueRH Radiation HardenedRT Radiation TolerantRTG4FCCC_0 RTG4 Phase lock loop CoreSATA Serial Advanced Technology AttachmentSCU Secondary Control UnitSD Secure DigitalSD/eMMC Secure Digital embedded MultiMediaCardSD-HC Secure Digital High CapacitySDM Spatial-Division-M ultiplexingSEE Single Event EffectSEFI Single Event Functional InterruptSEL Single event latchupSERDES Serializer/deserial izerSET Single event transientSEU Single event upsetSi Silicon SK Hynix SK Hynix Semiconductor CompanySMDs Selected Item DescriptionsSMMU System Memory Management UnitSOA Safe Operating AreaSOC Systems on a Chip SPI Serial Peripheral InterfacesRIO Serio Rapid I/OSSTL Sub series terminated logicTBD To Be DeterminedTemp TemperatureTHD+N Total Harmonic Distortion Plus NoiseTMR Triple Modular RedundancyT-Sensor Temperature-SensorTSMC Taiwan Semiconductor Manufacturing CompanyUART Universal Asynchronous Receiver/Transmitter

UltraRAM Ultra Random Access MemoryUSB Universal Serial BusVNAND Vertical NAND WDT Watchdog TimerWSR Windowed shift registerXAUI Extended 10 Gigabit Media Independent InterfaceXGXS 10 Gigabit Ethernet Extended SublayerXGMII 10 Gigabit Media Independent Interface)

To be presented by Melanie D. Berg at the NASA Electronic Parts and Packaging Program (NEPP) Electronics Technology Workshop (ETW), NASA Goddard Space Flight Center in Greenbelt, MD, June 17-20, 2019 and published on nepp.nasa.gov . 3

Microsemi RTG4 (RT4G150-CG1657M)FPGA SEE Heavy-ion Experiments:

SpaceWire and RapidIO

Single event effects (SEE)Field programmable gate array (FPGA)


• The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of high-speed data transmission protocols implemented in the Microsemi RTG4 FPGA device.

• The RTG4 DUT was configured to have the following test structures: – SpaceWire (NASA/GSFC core) and– Serial RapidIO (sRIO NASA/GSFC core) with embedded TMR PLL.

• Design/Device susceptibility was determined by monitoring the DUT for SET and SEU induced faults by exposing the DUT to a heavy-ion beam.

• Potential SEL was checked throughout heavy-ion testing by monitoring device current.

• This work is a follow-on to previous RTG4 testing performed by NASA Electronic Parts and Packaging (NEPP).

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Purpose and Overview Single Event Transient (SET) Single Event Upset (SEU) Single Event Latch-up (SEL)

Device Under Test (DUT) NASA Electronic Parts and Packaging (NEPP


Impact to CommunityMicrosemi RTG4 FPGA

• Space-grade FPGA product; Qualified to MIL-STD-883 Class B, and Microsemi will seek QML Class Q and Class V qualification.

• Bulk UMC 65 nm CMOS process with an epitaxial layer.

• I/O interfaces are significantly more robust versus prior Microsemi space-grade FPGAs devices.

• Embedded mitigation, packaging, and qualification process makes this device space-grade.– Flash based configuration –

hence configuration is essentially SEU immune.

– Embedded flip-flop (DFF) SEU hardening.

Hardened configuration flash cell 5


DUT Preparation for Heavy-Ion SEE Testing

• NEPP populated four boards with Rev C RT4G150-CG1657M devices.

• The DUTs were thinned using mechanical etching via an Ultra Tec ASAP-1 device preparation system.

• The parts were successfully thinned to 90 um – 100 um.

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Top Side of DUT

Bottom Side of DUTUltra Tec ASAP-1


Test System

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Motherboard (LCDT3) connected to daughterboard (DUT)

DUT: device under test (RTG4)

LabVIEW GUI: Send Commands and Receive Data LabVIEW GUI:

Monitor power and configure tester

Logic Analyzer and configure DUT


• Facility: Lawrence Berkeley National Laboratories 88 inch Cyclotron, 16 MeV/amu tune.

• Flux: 1.0x104 to 1.0x105 particles/cm2/s• Fluence: All tests will be run to 1 x 107 particles/cm2 or until

destructive or functional events occurred.• Test Temperature: Room Temperature.• Power Supply Voltage: Vcc = 1.2V; VIO = 2.5V

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Heavy-Ion Test Facility and Test Conditions

Ion Energy (MeV/Nucleon)

LET MeVcm2/mg0°

LET MeVcm2/mg60°

N 16 1.16 2.32Ne 16 2.39 4.78Si 16 4.35 8.70Ar 16 7.27 14.54

We lost a significant amount of test time because of beam tuning to 16MeV Linear energy transfer (LET)


Summary DUT Test Structures

Test Structure Frequency Range SEU Flow-Through (Flushable)

SpaceWire (two) no SET filter

156.25MHz No

SpaceWire (two) with SET filter

156.25MHz No

RapidIO (one- self-loopback) + TMR PLL

3GHz No


• Two SpaceWire Cores were connected internally (in the DUT).• SpaceWire Core signals were extracted and sent to the

motherboard for monitoring.• Upon an unexpected DUT event, motherboard creates a packet with

a timer and information then forwards the packet to Host PC.

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SpaceWire Testing

𝝈𝝈= #𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒇𝒇𝒇𝒇𝒖𝒖𝒖𝒖𝒇𝒇𝒇𝒇𝒖𝒖

= 𝟏𝟏𝑴𝑴𝑴𝑴𝑴𝑴𝑴𝑴

Fluence: # particles/cm2

σ: SEU cross sectionMFTF: mean fluence to failure

Experiments do not stop at bit-flips. We test until the DUT fails (links go down and do not return)


Error Packet from Motherboard Used for Data Post-processing

RecordBit Position

Data Field

0 rising link SpaceWire 11 falling link SpaceWire 12 rising link SpaceWire 23 falling link SpaceWire 229 … 4 debug signals39 … 30 receive data SpaceWire 149 … 40 receive data SpaceWire 2177:146 Timer – clock cycles (granularity of 1 timer clock cycle is

equal to DUT operational speed)

Although information is automated, some signals are also displayed on a logic analyzer during testing for real time manual

inspection and potential test intervention.


SpaceWire SEU Cross Sections: LET= 4.35 MeVcm2/mg

0.00E+00

1.00E-07

2.00E-07

3.00E-07

4.00E-07

5.00E-07

6.00E-07

7.00E-07

SEU

Cro

ss S

ectio

n (c

m2 /S

pace

Wire

)

SpaceWire no SET FilterSpaceWire with SET

SET filter does not seem to have a significant impact on cross section at relatively low LETs for the SpaceWire design.


• Packet reporting is the same as SpaceWire ; However, extracted signals differ between SpaceWire Core and sRIOCore

• One sRIO Core is instantiated with external loopback.• sRIO Core signals were extracted and sent to the motherboard for

monitoring.• Upon an unexpected DUT event, motherboard creates a packet with

a timer and information and forwards the packet to Host PC.

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RTG4 sRIO Testing

𝝈𝝈= #𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒖𝒇𝒇𝒇𝒇𝒖𝒖𝒖𝒖𝒇𝒇𝒇𝒇𝒖𝒖

= 𝟏𝟏𝑴𝑴𝑴𝑴𝑴𝑴𝑴𝑴

We test until the DUT fails (links go down and do not return)

DUT


• sRIO design contained embedded TMR PLL with auto-reset (OSC-TMR-PLL); as a design choice – it is not part of the SERDES Core.

• Auto-reset circuit uses the embedded 50MHz oscillator (50MHz OSC) circuit.

• 50MHz OSC has proven to be significantly more susceptible than other RTG4 components.

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Warning


RapidIO with OSC-TMR-PLLSEU Cross Sections

1.00E-07

1.00E-06

1.00E-05

1.00E-04

0 1 2 3 4 5 6 7

SEU

Cros

s Se

ctio

n (c

m2 /d

esig

n)

LET MeVcm2/mg

Low onset LET (<1 MeVcm2/mg): due to OSC-TMR-PLL not sRIO.Additional testing required.

Depending on the target environment this could result in an upset once every 2 years or so (versus 10’s of years).


Microsemi RT4G150-CG1657M (RTG4) Reliability Testing across Mil-Aero

Temperature Standard: -55°c to 125°c


• During test and integration (for a variety of missions) unexpected failure modes were traced back to a Microsemi RTG4 PLL loss of lock (PLOL) event.

• PLOL condition: Device reset or power-up is forced at a low device temperature, as temperature rises, PLOL might occur.

• PLOL Implication: system halt, loss of data, or metastability/chaotic state-space transitions.

• Microsemi has identified the root cause: – Upon reset, the embedded PLL goes through calibration.– PLL calibration that occurs at low temperatures is not accurate for high

temperature operation.– Only a problem if reset occurs at a low temperature. High temperature

calibrations are accurate for operation at all temperatures.• This study was conducted in parallel with Microsemi’s PLL study to

gain independent product knowledge.• The purpose of this investigation is to characterize the RTG4 phase

locked loop (PLL) components over the following stress conditions: temperature, frequency, and dose degradation.

Problem Statement and Purpose

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• What is the range of temperatures that a reset can occur and the PLL will lose lock? (cold start temperatures).

• Given a temperature that PLOL will occur, what is its temperature range of reliable operation before we lose lock?

• Is delay from reference clock of the PLL to its outputs affected?

• Is there cycle to cycle jitter?

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Experiments Focus on A Set of Events


Overview of DUT Designs Reference Design CommentsA 2-PLLs 2 identical PLLs with Single leg outputsB 4-PLLs 4 separate PLLs with 4 output legsC EPCS SERDES 1 2 Lane Serial Rocket I/O on SERDES 1 with

Controlling Triple Modular Redundant (TMR) PLL

D XAUI SERDES 2 Lane XAUI on SERDES 5E Single PLL 1 single output leg 50 MHz in 100MHz outputF Single PLL 1 single output leg 200 MHz in 200MHz output

Extended physical coding layer (EPCS)Extended 10 Gigabit Media Independent Interface (XAUI)Serializer De-serializer (SERDES)Phase locked loop (PLL)

Most DUT designs did not contain TMR PLLs because of their poor SEE response observed during heavy-ion testing.

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Test System A: 2PLLs

50MHz output … 100MHz output 50MHz output … 100MHz output

RTG4 PLL Core: RTG4FCCC_0Clock Conditioning Circuit: CCC

Identical structures yet different physical locations.

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Test System B: 4PLLs

250MHz input

250MHz input

50MHz input

10MHz input

400MHz output133.33MHz output50MHz output10MHz output

400MHz output133.33MHz output100MHz output50MHz output

400MHz output133.33MHz output200MHz output40MHz output 400MHz output

• Multiple leg outputs versus single leg outputs. • Frequency variations

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Test System F: Single Leg Output

200MHz input 400MHz output

200MHz output to Tester

Moving towards experiments that closely match Microsemi reliability tests.

Motherboard BERT counts edges: a missed edge is an event

Divide by 2

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Test Samples• Microsemi provided 4 pre-screened RTG4 test samples; NEPP

populated three new boards with 3 out of the 4 new devices.• In addition, NEPP tested 2 old RTG4 devices.

– Devices were thinned and had been to heavy-ion testing. – Experiments with irradiated devices were performed to flush out test system

anomalies and procedure. However, experimental data are compared.

RTG4 Daughterboard with ball grid package

Interface to motherboard

# Usage StateDUT 1 Previously IrradiatedDUT 2 Previously IrradiatedDUT 3 NewDUT 4 NewDUT 5 New

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Test System and Procedure:Reuse of a robust system!!!!!

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Test System Lab Setup

Motherboard is full of COTS components and cannot survive temperature chamber extreme temperatures.

ThermoJet ES

DUT Board

Mother Board 25


Temperature Forcing• Observed from testing: PLL loss of

lock is not dependent on temperature ramp rate.

• Temperature forcing machine can be used to force DUT temperature.

• DMM monitors DUT temperature across DUT diode.

• DMM sends data to PC#3.• Additional RS232 connection from

the PC#3 to the LCDT3.• PC#3 sends all temperature

readings (in the order of ms) to the LCDT3.

• LCDT3 synchronizes DUT temperature and events for packetizing and reporting.

DUT isolation to temperature exposure is key.

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JTAG: joint test access groupRS232: Recommended Standard 232USB: Universal Serial BusDMM: Digital multi-meterGPIB: general purpose interface bus


Uniqueness• Automated measurement of DUT temperature diode.

– DMM to PC#3 and PC#3 to Motherboard.– Motherboard synchronizes current temperature to events in

logging packets.– Can more accurately monitor DUT temperature.

• High-speed experiments can be performed because of LCDT-DUT test system automation (in the granularity of ns).

• Motherboard has custom built-in BERT tester (oversampling rate at 450MHz).– Only used on the single leg PLLs (Test Systems E and F).– Counts the reference clock input rising edges and the DUT

output rising edges.

BERT count and compare performed in motherboard

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Experiment Packet Creation

Design Output signals (current cycle)

Design Output signals (prior cycle)

Packet indicator (reset, rising lock, falling lock, etc…)Current temperature

Cold start temperature

Timer

Will invoke a packet if data are not expected values

Indicates the event that caused the packet creation

Timer is a Motherboard Counter with the granularity of 5 ns.

Tester monitors DUT data, lock, and reset events. Upon event, tester packetizes information and transmits to the host PC.

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• Measure device electrical characteristics to determine if the device is operational as specified in the device data sheet and record results.– Measure RTG4 leakage current.– Measure RTG4 operational voltages.– Inspect DUT board voltage regulators (to guarantee

that the RTG4 is receiving expected voltages).

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Test Procedure: Prior to Experiments


• Select a cold start temperature (e.g., -55°c, -30°c, -10°c, 0°c, 10°c).• Reset the tester and reset the DUT.• Check logic analyzer that the DUT lock signal goes to logic zero

(low state).• Turn on the data logging for PC#1 (daughterboard to motherboard

reporting bit file will be saved at the end of the experiment).• Set the Thermal Jet temperature forcing machine to the selected

cold start temperature:– PC#3 displays DUT diode temperature reading.– Wait until the device’s thermal coupler has a reading equal to

the set cold start temperature.

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Test Procedure: Initialize Experiment


• Once the cold start has been reached take the DUT out of reset and start monitoring activity:– Check logic analyzer that the DUT lock signal goes to logic one

(high state).• Start custom motherboard BERT (if Test E or Test F).• Increase the setting for the temperature forcing jet.

– Dwell at increments of 10°c for 3-minutes.– At all times (during temperature increase and during dwell

times), lock signals and BERT readings are monitored (visually and by the motherboard).

– Manually take and record delay measurements.– Record current and voltage readings (DUT electrical

parameters).

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Test Procedure: Operational DUT and Temperature Increase


Results

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Summary of NASA/GSFC Experimental Data

• Roughly 300 experiments have been performed by GSFC-NEPP.• Tests were run using nominal Voltage (3.3V) and a PLL setting of

6000ppm (PLL default).

ResetTemperature

Loss of PLL Lock Temperature

-50°c 90°c and above



-10°c 100°c and above (marginal)

0°c No loss of lock

10°c No loss of Lock

Warnings:• In a system, the board can read

cooler than the DUT… e.g.: board at 70°c, yet the DUT could be operating at 95°c.

• NEPP data differ from Microsemi. Assuming test setup makes the difference; GSFC-NEPP clock inputs are sharp (because they originate from another FPGA); and voltage droop could not investigated because of on-board voltage regulators.

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NASA/GSFC XAUI Data• DUT 4 – raw ; DUT 2 and DUT 1 - irradiated

ResetTemperature

Loss of PLL Lock DUT 4



-50c 115c 107c 105c

-40c 115c 108c 105c

-30c 115c 108c 105c

-20c 115c 108c No loss

-10c No loss No loss No loss

0c No loss No loss No loss

10c No loss of Lock No loss of Lock No loss of Lock34


BERT Reporting

Error Packet Fields (subset)

Design lock signals (current cycle)

Design lock signals (prior cycle)

Current temperature

Ref clock count

PLL clock count

Prior two cycles of Ref clock count

Prior two cycles of PLL clock count

Time stamp

Tester monitors DUT data, lock, and rising edge clock events. Upon unexpected event, tester packetizes information and transmits to the host PC.

If Ref clock differs from PLL clock by more than one cycle, then a package is generated.

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Lock Loss Report (start temp = -30c)Points at temp=83c, 93c, and 104c are manfully forced to report state of operation (no errors were reported by motherboard – simply checking DUT state).

No erroneous behavior until 106c. At 106: PLOL… but No BERT Error

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Loss of a PLL Clock (start temp = -30c)PLOL at 106c with no BERT error. BERT error occurs at 114c.

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• NEPP experiments: Delay only measured with 200MHz input clock and 200MHz output eye_regs.

• Delay increases with temperature variation.• Phase difference maxed at 250° (3.5 ns out of a 5 ns clock cycle). • Consistent across our tests and devices.• Not sure if consistent across variation of frequencies.• Bottom line!:

– There is drift across temperature.– However, this does not affect jitter (i.e., if all is contained on the same

clock tree, the design is safe against drift… proven with 400MHz circuit).– Do not use the PLL as a synchronizer.

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Notes on Output Drift from Reference Input Clock


• The purpose of this test was to characterize the Microsemi RT4G150-CG1657M’s parametric degradation and its impact on the embedded PLLs’ integrity for total ionizing dose (TID) device stress.

• In the experiments, the devices were exposed to high dose rate (HDR) irradiations using gamma radiation.

• General test procedures (irradiation through characterization) were in accordance with MIL-STD-883, Method 1019, Condition E.

• This is not an experiment to determine if reliability degrades post the DUT’s manufacturer TID rating (125 krads).

• Device parametrics such as leakage currents, embedded PLL performance, and overall chip and die health were investigated prior to and after each DUT exposure.

• Test Samples: DUT2 (previously irradiated) and DUT 5 (fresh part) were selected for TID tests.

• Samples were biased with a 12V supply during exposure.

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Total Ionizing Dose Impact to RTG4 Reliability


Total Ionizing Dose Testing

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Lead Block Shielding

DUT with Shielding and 12V Bias Cabling


• Perform reliability tests and measure DUT parametrics.

• First DUT (DUT 2): – irradiate to 50 krads.– Perform reliability tests and measure

DUT parametrics. No change in measurements and PLOL were observed.

– Irradiate to 75 krads (+25 krads).– Perform reliability tests and measure

DUT parametrics. No change in measurements and PLOL were observed.

– Assumption: annealing is occurring because of high temperature reliability testing. Subsequently – irradiate with an additional 100 krads.

– Perform reliability tests and measure DUT parametrics. No change in measurements and PLOL were observed.

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Procedure and Results

• Second DUT (DUT 5) Perform reliability tests and measure DUT parametrics.

• Irradiate to 100 krads.– Perform reliability tests and

measure DUT parametrics. No change in measurements and PLOL were observed.


Thank YouQuestions?

2019 nepp etw: examination of reliability and single event ... - berg... · to be presented by...

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