2015-2016 ieee vlsi project titles-wingz technologies

WINGZ TECHNOLOGIES Cell:9840004562www.wingztech.com, www.finalyearproject.co.in [email protected],[email protected]

2015 – 2016 IEEE Software [ Dotnet –Java – NS2 – Matlab - Android] | VLSI | Embedded |Power Electronics | Power System | Mechanical | Civil and etc..

Project List Available Android App - https://play.google.com/store/apps/details?id=com.wingztech

Plot No 18, Ground Floor ,New Colony, 14th Cross Extension, Elumalai Nagar, Chromepet, Chennai –600044,Mobile : 9840004562. Ph : 044 – 65622200, Tamilnadu, India.

Website: www.wingztech.com - [email protected],[email protected]

VLSI Project Titles

IEEE / Non IEEE / Real Time Project for B.E / B.Tech /M.E / M.Tech / BCA / MCA / M.Sc / MBA / Ph.D and etc…

IEEE 2015 VLSI TITLES

***Document Format***

Abstract: Introduction: Literature Survey:

System Analysis: Existing System: Disadvantages:

Proposed System: Advantages: System Requirements:

Block Diagram: Circuit Diagram: Workflow Diagrams:

Implementation: Modules Description: System Study:

System Testing: Software Description: Sample code:

Conclusion: Future Enhancement: References:

***Complete Document ***

http://www.wingztech.com/

http://www.finalyearproject.co.in/

https://play.google.com/store/apps/details?id=com.wingztech






VLSI Project Titles


2015 -2016 VLSI PROJECT TITLES YEAR

Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits MAR/2015

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and

Sequential Circuits

MAR/2015

Ultralow-Energy Variation-Aware Design: Adder Architecture Study MAY/2015

Low-Cost High-Performance VLSI Architecture for Montgomery Modular

Multiplication

MAR/2015

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect

Protocols

MAY/2015

Median Filter Architecture by Accumulative Parallel Counters JUN/2015

A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM APR/2015

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply

Voltage Levels

MAR/2015

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-

HD HEVC Video Encoding

MAR/2015

A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for

Multipurpose Electronic Devices

JUN/2015

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation JUN/2015

Further Desensitized FIR Halfband Filters JUL/2015

Implementation of Arithmetic Operations with Time-free Spiking Neural P Systems JUN/2015

A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector

Characteristics and a Built-in Jitter Monitor

JUN/2015

Early Skip Mode Decision for HEVC Encoder With Emphasis on Coding Quality APR/2015

Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters MAY/2015

Energy Consumption of VLSI Decoders JUN/2015

Timing Error Tolerance in Small Core Designs for SoC Applications APR/2015









VLSI Project Titles


Design and Analysis of Inexact Floating-Point Adders MAR/2015

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers MAR/2015

Low-Cost High-Performance VLSI Architecture for Montgomery ModularMultiplication MAR/2015

Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration

Implemented in 40 nm FPGA

MAR/2015

A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory APR/2015

Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent

Reception

APR/2015

Synthesis of Genetic Clock with Combinational Biologic Circuits APR/2015

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended

Double Base Number Systems

JAN/2015

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional

Probability

JAN/2015

Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter

Architecture for Multi-Standard SDR Applications

JAN/2015

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications APR/2015

Low-Power and Area-Efficient Shift Register Using Pulsed Latches JUN/2015

Array-Based Approximate Arithmetic Computing: A General Model and Applications to

Multiplier and Squarer Design

APR/2015

Recursive Approach to the Design of a Parallel Self-Timed Adder JAN/2015

Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq JAN/2015

An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common

Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

APR/2015

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable

Orthogonal Approximation of DCT

JAN/2015

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator MAY/2015









VLSI Project Titles


A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT MAY/2015

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes MAY/2015

Design of Efficient Content Addressable Memories in High-Performance FinFET Technology MAY/2015

A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive

Slope Generator With Hysteresis Voltage Comparison Techniques

MAY/2015

Obfuscating DSP Circuits via High-Level Transformations MAY/2015

Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms MAY/2015

Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging FEB/2015

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs MAR/2015

All Digital Energy Sensing for Minimum Energy Tracking APR/2015

Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications MAR/2015

Algorithm and Architecture Design of the H.265/HEVC Intra Encoder MAY/2015

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding MAY/2015

A Novel Photosensitive Tunneling Transistor for Near-Infrared Sensing Applications: Design,Modeling, and Simulation

APR/2015

High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques &Dynamic Multi-Frame Processing Schedule

MAY/2015

A New Parallel VLSI Architecture for Real-time Electrical Capacitance Tomography MAR/2015

Graph-Based Transistor Network Generation Method for Supergate Design MAR/2015

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate MachineVision Imaging Applications

JUL/2015

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-TimeVideo Applications

JUN/2015

A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders JUN/2015

Comparative Performance Analysis of the Dielectrically Modulated FullGate and Short-GateTunnel FET-Based Biosensors

FEB/2015

VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm JAN/2015

Fine-Grained Access Management in Reconfigurable Scan Networks JUN/2015

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors MAR/2015

Partially Parallel Encoder Architecture for Long Polar Codes MAR/2015









VLSI Project Titles


One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes JAN/2015

A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications APR/2015

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, andImplementations

FEB/2015

Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRCApplications

JAN/2015

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm forthe Successive-Approximation Register

MAR/2015

A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply MAR/2015

A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT FEB/2015

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation MAR/2015

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methodsin Communication Systems

JAN/2015

Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks MAR/2015

The Diffusion Network in Analog VLSI Exploiting Noise-Induced Stochastic Dynamics toRegenerate Various Continuous Paths

JUN/2015

Nonsmooth Optimization Method for VLSI Global Placement APR/2015

Low-Power VLSI Architectures for DCT/DWT: Precision vs Approximation for HD Video,Biomedical, and Smart Antenna Applications

FEB/2015

VLSI Design for SVM-Based Speaker Verification System JUL/2015

An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation JUN/2015

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach MAY/2015

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors MAR/2015

Ultra-High-Throughput VLSI Architecture of H.265 HEVC CABAC Encoder for UHDTVApplications

MAR/2015

Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI MAY/2015

A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training andClassification

AUG/2015

Reconfiguration-Based VLSI Design for Security MAR/2015

Depth-Reliability-Based Stereo-Matching Algorithm and Its VLSI Architecture Design JUN/2015

Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs APR/2015

A Bio-Realistic Analog CMOS Cochlea Filter With High Tunability and Ultra-Steep Roll-Off JUN/2015









VLSI Project Titles


Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection JAN/2015

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes OverGF (2^{m})

AUG/2015

Multilayer Obstacle-Avoiding X-Architecture Steiner Minimal Tree Construction Based onParticle Swarm Optimization

MAY/2015

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

AUG/2015

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip JAN/2015

A Novel Hardware Architecture of the Lucas-Kanade Optical Flow for Reduced Frame MemoryAccess

MAY/2015

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NANDFlash Memory Systems

JUL/2015

Detailed Routing Algorithms for Advanced Technology Nodes APR/2015

A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video

APR/2015

Fast Motion Estimation Algorithm And Design For Real Time QFHD High Efficiency VideoCoding

JAN/2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion JAN/2015

A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures JAN/2015

A Power-Efficient Adaptive Fuzzy Resolution Control System for Wireless Body SensorNetworks

JUN/2015

Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing FEB/2015

Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low-Power Test Set FEB/2015

Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline JAN/2015

New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies JUL/2015

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning JUL/2015




2015-2016 ieee vlsi project titles-wingz technologies

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