2014-2-27 john lazzaro (not a prof - “john” is always ok)

UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory

2014-2-27

John Lazzaro(not a prof - “John” is always OK)

CS 152Computer Architecture and Engineering

www-inst.eecs.berkeley.edu/~cs152/

TA: Eric Love

Lecture 12 -- Virtual Memory

Play:

UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory

Today’s Lecture - Virtual Memory

Virtual address spaces

Page table layout

TLB design options

Virtual machines

Exceptions and interrupts


The Limits of Physical Addressing

CPU Memory

A0-A31 A0-A31

D0-D31 D0-D31

“Physical addresses” of memory locations

Data

All programs share one address space: The physical address space

No way to prevent a program from accessing any machine resource

Machine language programs must beaware of the machine organization

Where we are in CS 152 ...


Apple II: A physically addressed machine

Apple ][ (1977)

Steve WozniakSteve

Jobs

CPU: 1000 ns

DRAM: 400 ns

CS 152 L15: Virtual Memory UC Regents Fall 2006 © UCB

Apple II: A physically addressed machine

Apple ][ (1977)


The Limits of Physical Addressing

CPU Memory

A0-A31 A0-A31

D0-D31 D0-D31

“Physical addresses” of memory locations

Data

All programs share one address space: The physical address space

No way to prevent a program from accessing any machine resource

Machine language programs must beaware of the machine organization

Programming the Apple ][ ...


Solution: Add a Layer of Indirection

CPU Memory

A0-A31 A0-A31

D0-D31 D0-D31

Data

User programs run in an standardizedvirtual address space

Address Translation hardware managed by the operating system (OS)

maps virtual address to physical memory

“Physical Addresses”

AddressTranslation

Virtual Physical

“Virtual Addresses”

Hardware supports “modern” OS features:Protection, Translation, Sharing


MIPS R4000: Address Space Model

Process A

AddressError

2 GB

0

231

232

- 1

Process B

AddressError

2 GB

0

231

232

- 1

Process A and B have independent address spaces

ASID = 12 ASID = 13

ASID = Address Space Identifier

When Process A writes its address 9, it writes to a different physical memory location than

Process B’s address 9

May only be accessed by kernel/supervisor

To let Process A and B share memory, OS maps parts of

ASID 12 and ASID 13 to the same physical memory locations.

All address spacesuse a standard memory map

Still works (slowly!) if a process accesses more virtual memory than the machine has physical memory


MIPS R4000: Who’s Running on the CPU?

System Control Registers

User cannot write supervisor/kernel bits. Supervisor cannot write kernel bit.

User cannot change address translation configuration

Status (12): Indicatesuser, supervisor, or

kernel mode

EntryLo0 (2): 8-bit ASID field codes virtualaddress space ID.

or run other privileged instructions ...


MIPS Address Translation: How it works


CPU Memory

A0-A31 A0-A31

D0-D31 D0-D31

Data

TLB also contains ASID andkernel/supervisor bits for virtual address

Virtual Physical


TranslationLook-Aside

Buffer(TLB)

Translation Look-Aside Buffer (TLB)A small fully-associative cache of

mappings from virtual to physical addresses

Fast common case: Virtual address is in TLB, process has permission to read/write it.

What is the table

ofmappings

that it caches?


Page tables code virtual address spaces

A machine usually supports

pages of a few sizes

(MIPS R4000):

PhysicalMemory Space

A valid page table entry codes physical memory “frame” address for the page

A virtual address spaceis divided into blocks

of memory called pagesframe

frame

frame

frame

A page table is indexed by a virtual address

virtual address

Page Table(One per ASID)

OS manages the page table for each ASID


V=0 pages either reside on disk or have not

yet been allocated.

OS handles V=0“Page fault”

In this example,physical and virtual

pages must be the same size!

The TLB caches page table entries

MIPS handles TLB misses

in software (random replacement). Other

machines use hardware.

for ASID

Physicalframe

address

TLB

Page Table

2

0

1

3

virtual address

page off

2frame page

250

physical address

page off

TLB caches page table

entries.

frame


Page tables may not fit in memory!

A table for 4KB pages for a 32-bit address space has 1M entries

Each process needs its own address space!

P1 index P2 index Page Offset31 12 11 02122

32 bit virtual address

Top-level table wired in main memory

Subset of 1024 second-level tables in main memory; rest are on disk

or unallocated

Two-level Page Tables


V=0 pages either reside on disk or have not

yet been allocated.

OS handles V=0“Page fault”

What if a page resides on disk?

TLB

Page Table

2

0

1

3

virtual address

page off

2frame page

250

physical address

page off

TLB caches page table

entries.

Question: What to do when a TLB miss causes an access to a page table

entry with V=0?

for ASID

Physicalframe

address


VM and Disk: Page replacement policy

...

Page Table

1 0useddirty

1 00 11 10 0

Set of all pagesin Memory Tail pointer:

Clear the usedbit in thepage table

Head pointerPlace pages on free list if used bitis still clear.Schedule pages with dirty bit set tobe written to disk.

Freelist

Free Pages

Dirty bit: page has

been written.

Used bit: set to

1 on any reference

Architect’s role: support setting dirty and used bits

On page fault: deallocate page table

entry of a page on the free list.


TLB Design Concepts


MIPS R4000 TLB: A closer look ...


CPU MemorySystem

A0-A31 A0-A31

D0-D31 D0-D31

Data


Buffer(TLB)

Virtual Physical


Physical space larger than virtual

space!

Checked againstCPU ASID


Can TLB and caching be overlapped?

Index Byte Select

Valid

Cache Block

Cache Block

Cache Tags Cache Data

Data out

Virtual Page Number Page Offset


Buffer(TLB)

Virtual

Physical

=

Hit

Cache Tag

This works, but ...

Q. What is the downside?

A. Inflexibility. VPN size locked to cache tag size.


Can we cache virtual addresses?


CPU Main Memory

A0-A31 A0-A31

D0-D31 D0-D31

Only use TLB on a cache miss !


Buffer(TLB)

Virtual Physical


A. Synonym problem. If two address spaces share a physical frame, data may be in cache

twice. Maintaining consistency is tricky.

CacheVirtual

D0-D31

Downside: A subtle problem. What is it?

Solution: Anti-aliasing. See book, page B-38.


Virtual Memory Recap

VM: Uniform memory models,protection, sharing.

Operating systems manage the page table and (often) the TLB

A TLB acts as a fast cache forrecent address translations.

UC Regents Spring 2014 © UCBCS 152 L12: Virtual Memory

Break

Play:


Running Windows on a Mac

Depends on the meaning of the word “run” ...

2006 edition ...


Method #1: Boot Camp

Basic Idea: New Macs use Intel CPU and support chips. So, set up boot ROM to let you choose Win or OS X.

+++ Great compatibility. Just add device drivers.

+++ No performance hit: full-speed, use all RAM, etc.

--- Must reboot to change OS.--- Sharing files between OS partitions securely is tricky.


Method #2: Run WINE on OS XBasic Idea: Emulate the Windows API in software running under OS X. Lets you run Windows apps in a “compatibility box” without running Windows.

+++ Do not needto buy Windows.+++ No reboot to run Win-app.--- Slow.

--- Chances are, the app you want to run has compatibility woes.


Method 3: Virtual PCBasic Idea: Make a software emulation of PC hardware. Runs as a user process under OS X. Boot Windows and run apps on the emulator.

+++ Runs on PowerPC Macs.

+++ Good compatibility. Easier to emulate CPU than Win API.--- Must buy Windows.--- Slow


Emulating a PC --> emulating everything!

Windows expects to see raw disks,so VirtualPC has Virtual Disks.

Windows expects to manipulate page tables, so VirtualPC has Virtual TLB.

Windows expects to to configure network: Virtual Ethernet Card.

Windows expects to set up a graphics card, to VirtualPC has a Virtual GPU.

Like the movie “The Truman Show” ... no wonder its slow.


Method 4: Parallels, a Virtual MachineBasic Idea: Like emulating a PC, but different. Use an Intel-based Mac, runs on top of OS X. Uses hardware support to create a fast virtual PC that boots Windows.

Source: http://www.atpm.com/12.10/parallels.shtml

+++ Reasonable performance.Virtual CPU runs 33% slower than running on physical CPU. 2 GB physical memory for a 512 MB virtual PC to run w/o disk swaps.

(2006 data)


“Hardware assist?” What do we mean?

In an emulator, we run Windows code by simulating the CPU in software.

In a virtual machine, we let safe instructions (ex: ADD R3 R2 R1) run on the actual hardware in user mode.

We use hardware features to preventdirect execution of unsafe instructions (ex: change a page table entry).

We trap each attempt, and emulate the instruction in software, in a safe way.

A “trap” is one type of “exception” ...

UC Regents Fall 2008 © UCBCS 194-6 L10: Advanced Processors II

Exceptions and Interrupts

Exception: An unusual event happens to an instruction during its execution. Examples: divide by zero, undefined opcode.Interrupt: Hardware signal to switch the processor to a new instruction stream. Example: a sound card interrupts when it needs more audio output samples (an audio “click” happens if it is left waiting).


Challenge: Precise Interrupt / Exception

Definition:

Follows from the contract between the architect and the programmer ...

(or exception)


Precise Exceptions in Static Pipelines

Key observation: architected state only

changes in memory and register write stages.


Adding trap support to pipelines ...

Detect @ decode, set an Exc E bit

Call the code to be run on this trap type.

Pass along Cause and EPC as arguments.

Virtual Machines: Better as servers than clients

Google runs Linux servers running the KVM module (Kernel Virtual Machine Monitor) and

spins up VMs with varying specs on demand.

$2/hour for a 16-virtual-core 104GB machine ...

Shell command for managing VMs ...

Command-line arguments set

RAM, disk, network ... and the OS

to install.

VMs can be monitored and

reconfigured on the fly.

Under the hood

What Google customers “think” is happening.

(Guest)

What actually happens.

Where Google runs “make new VM” commands

When the guest OS tries to privileged instructions, host kernel intercepts.

Example: Paging

Guest OS runs instructions that manipulate page tables, and as far as it can tell everything works OK.

Exists to “fake out” guest OS.Hypervisor

watches every Guest OS move, and updates the “shadow” page tables and TLB to work correctly.

Hardware Support

Intel VT-x adds a new level of privilege where hypervisors can run (VMX root).

Guest OS’s run in “kernel mode” (ring 0) like they do on bare metal. Hypervisor relieved from faking guest privilege levels.

Hardware Support

Intel VT-x supports Extended Page Tables(EPT).

The TLB and the page replacementhardware tracks the shadow/guests page mappings.

A work in progress

Each generation of Intel server adds new features for virtualization, and improves the latency for getting in and out of VMX root mode for critical operations.

On Tuesday

Memory semantics for multi-core ...

Have a good weekend !

2014-2-27 john lazzaro (not a prof - “john” is always ok)

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