ufdcimages.uflib.ufl.edu · 2013. 5. 31. · 4 acknowledgments first of all i would like to thank...
TRANSCRIPT
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SYNCHRONIZATION AND CONTROL OF HIGH FREQUENCY DC-DC CONVERTERS
By
PENGFEI LI
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2009
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© 2009 Pengfei Li
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To my Mom and Dad
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ACKNOWLEDGMENTS
First of all I would like to thank my academic advisors, Dr. Rizwan Bashirullah for his
valuable guidance over the course of the last five years. I would also like to thank Dr. Robert Fox,
Dr. Kenneth O, Dr. Loc Vu-Quoc and Dr. Prabhat Mishra for their advice and their willingness
to be on my thesis committee.
A special thanks to Deepak Bhatia, Lin Xue, Jikai Chen, Yan Hu, Hang Yu, and Chunming
Tang for having useful design related discussions. I would also like to thank Zhiming Xiao,
Pawan Sabharwal for always being open to answer any question at any time, let it be day or
night. Speaking about the classes at UFL, I would like to thanks Dr. Bashirullah for his excellent
Advanced VLSI class, Dr. Fox for his Bipolar and MOS design class, especially the simple
design related approach and second order analysis, Dr. O for his excellent Microwave IC design
class, Dr. Ngo for his introduction to power electronics.
Finally, I would like to thank my mom, dad for all their love and support till date.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS.................................................................................................................... 4
LIST OF TABLES................................................................................................................................ 8
LIST OF FIGURES .............................................................................................................................. 9
LIST OF ABBREVIATIONS ............................................................................................................ 13
ABSTRACT ........................................................................................................................................ 14
CHAPTER
1 INTRODUCTION....................................................................................................................... 16
1.1 Background ........................................................................................................................... 16 1.2 Recent Progress towards Integration of High Frequency DC-DC Converters ................. 19 1.3 Thesis Organization .............................................................................................................. 23
2 SWITCHED INDUCTOR DC-DC CONVERTERS................................................................ 24
2.1 Introduction ........................................................................................................................... 24 2.2 Buck / Boost DC-DC Converters Basics ............................................................................. 24
2.2.1 Buck Converter Topology ......................................................................................... 24 2.2.2 Boost Converter Topology......................................................................................... 26 2.2.3 Inductor Current Ripple and Output Voltage Ripple ............................................... 28 2.2.4 Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode
(DCM)............................................................................................................................... 29 2.2.5 Overall efficiency analysis for synchronous buck converter ................................... 31
2.3 Control Scheme of DC-DC Converters ............................................................................... 34 2.3.1 Voltage Mode Pulse Width Modulation (PWM) Controller ................................... 34 2.3.2 Variable Frequency Controller .................................................................................. 35
2.3.2.1 Current mode hysteretic controller ................................................................. 35 2.3.2.2 Voltage mode hysteretic and constant on-time controller ............................. 38
2.4 Multiphase Technique .......................................................................................................... 40
3 MULTIPHASE SYNCHRONIZATION WITH DELAY LOCKED LOOP .......................... 43
3.1 Introduction ........................................................................................................................... 43 3.2 DLL Based Multiphase Hysteretic Controller .................................................................... 44
3.2.1 System Architecture ................................................................................................... 44 3.2.2 Delay Locked Loop (DLL) Design ........................................................................... 45 3.2.3 Circuits Implementation............................................................................................. 48
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3.2.3.1 Delay cell.......................................................................................................... 48 3.2.3.2 Phase frequency detector and startup circuit.................................................. 48 3.2.3.3 Charge pump and loop filter ........................................................................... 50
3.3 Analysis for DLL based Multiphase Buck Converter ........................................................ 51 3.3.1 Voltage Conversion Range ........................................................................................ 51 3.3.2 Voltage Ripple ............................................................................................................ 53 3.3.3 Effects of Phase and Duty Cycle Mismatch ............................................................. 53 3.3.4 Effect of Inductor Mismatch ...................................................................................... 58 3.3.5 Effect of DLL on Transient Response ...................................................................... 58
3.4 Simulation Results ................................................................................................................ 61 3.4.1 Loop Dynamics .......................................................................................................... 61 3.4.2 Duty Cycle Error and Current Mismatch .................................................................. 64
3.5 Measurement Results ............................................................................................................ 65 3.5.1 Four Phase Operation ................................................................................................. 66 3.5.2 Frequency Dependence .............................................................................................. 67 3.5.3 Efficiency .................................................................................................................... 68 3.5.4 Transient Response .................................................................................................... 69 3.5.5 Performance Summary ............................................................................................... 72
3.6 Summary................................................................................................................................ 74
4 FREQUENCY SYNCHRONIZATION WITH DIGITAL PHASE LOCKED LOOP (DPLL) ......................................................................................................................................... 76
4.1 Introduction ........................................................................................................................... 76 4.2 DPLL Synchronized DC-DC Converter .............................................................................. 78
4.2.1 System Architecture ................................................................................................... 78 4.2.2 Modeling Hysteretic Buck Converter as a Voltage Controlled Oscillator ............. 80 4.2.3 Modeling the DPLL Synchronized Converter as a Charge Pump PLL .................. 81 4.2.4 Frequency Response................................................................................................... 83
4.3 Circuit Implementation of DPLL Synchronized Hysteretic Converter ............................. 86 4.3.1 Digital Phase Locked Loop (DPLL) Design ............................................................ 87 4.3.2 Digitally Controlled Delay Line (DCDL) ................................................................. 89 4.3.3 Hysteretic Comparator ............................................................................................... 90 4.3.4 Non-Overlapping Clock Generation ......................................................................... 91 4.3.5 On-Chip Load ............................................................................................................. 92 4.3.6 Layout of the Power Switches ................................................................................... 93
4.4 Mixed Signal Simulation of DPLL Synchronized Hysteretic Converter .......................... 94 4.4.1 DPLL Operation with Variable Proportional Path Gain .......................................... 94 4.4.2 Transient Response to a Frequency and Load Step.................................................. 95
4.5 Measurement Results ............................................................................................................ 96 4.5.1 Frequency Locking Performance .............................................................................. 96 4.5.2 Efficiency .................................................................................................................... 98 4.5.3 Load Transient Response ........................................................................................... 99 4.5.4 Digital Frequency Control ....................................................................................... 101 4.5.5 Performance Summary ............................................................................................. 102
4.6 Summary.............................................................................................................................. 104
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5 HIGH FREQUENCY BOOST CONVERTER WITH DIGITAL DELAY LOCKED LOOP (D-DLL) ......................................................................................................................... 105
5.1 Introduction ......................................................................................................................... 105 5.2 Multiphase Boost Converter with High Voltage Devices ................................................ 106
5.2.1 System Architecture ................................................................................................. 106 5.2.2 Schottky Diode Based Rectifier .............................................................................. 107 5.2.3 Synchronous Switch ................................................................................................. 109
5.3 Proposed Digital Delay Locked Loop ............................................................................... 112 5.3.1 D-DLL Architecture ................................................................................................. 112 5.3.2 Digital-Controlled Delay Line ................................................................................. 114
5.4 Circuit Implementation ....................................................................................................... 116 5.4.1 Current Mode PWM Control ................................................................................... 116 5.4.2 Current Sensing Circuit............................................................................................ 120 5.4.3 Oscillator (OSC) ....................................................................................................... 122 5.4.4 Layout for Power Switches ...................................................................................... 123
5.5 Measurement Results .......................................................................................................... 124 5.5.1 Four Phase Operation ............................................................................................... 124 5.5.2 Efficiency .................................................................................................................. 126 5.5.3 Transient Response .................................................................................................. 127 5.5.4 Performance Summary ............................................................................................. 128
5.6 Summary.............................................................................................................................. 129
6 CONCLUSIONS AND FUTURE WORKS ........................................................................... 131
6.1 Summary and Contributions............................................................................................... 131 6.2 Future Works ....................................................................................................................... 132
LIST OF REFERENCES ................................................................................................................. 134
BIOGRAPHICAL SKETCH ........................................................................................................... 141
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LIST OF TABLES
Table page 2-1 Summary of CCM-DCM characteristics for the buck and boost converters...................... 31
3-1 Duty cycle and current-sharing analysis of the DLL controller .......................................... 65
3-2 Performance summary ........................................................................................................... 73
3-3 Performance comparison ....................................................................................................... 73
3-4 Performance comparison ....................................................................................................... 74
4-1 Performance summary ......................................................................................................... 103
4-2 Performance comparison ..................................................................................................... 103
5-1 D-DLL performance summary ............................................................................................ 126
5-2 Performance summary ......................................................................................................... 129
5-3 Performance comparison ..................................................................................................... 129
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LIST OF FIGURES
Figure page 1-1 Processor's voltage and current of ITRS Roadmap, 2006 ................................................... 18
1-2 Intel's roadmap for processor’s slew rate.............................................................................. 18
1-3 Simplified power delivery network for Intel Pentium4 processor ...................................... 18
1-4 Near-load converter insertion for processor power supply.................................................. 20
1-5 A multiphase CPU power delivery system for an AMD Socket 939 processor................. 21
2-1 A standard step-down buck converter topology ................................................................... 25
2-2 Buck converter equivalent circuits. ....................................................................................... 25
2-3 Synchronous buck converter topology.................................................................................. 26
2-4 An ideal step-up boost converter topology ........................................................................... 27
2-5 Boost converter equivalent circuits. ...................................................................................... 27
2-6 Capacitor current waveform for (a) buck converter, and (b) boost converter .................... 28
2-7 Buck converter operating in DCM ........................................................................................ 30
2-8 Voltage mode PWM buck converter’s (a) schematic and (b) waveforms .......................... 35
2-9 Single phase current mode hysteretic buck converter.......................................................... 36
2-10 Voltage waveforms at nodes VFB and VX. ............................................................................ 36
2-11 Single phase voltage mode hysteretic buck converter ......................................................... 39
2-12 Single phase constant on-time buck converter ..................................................................... 39
2-13a Basic 2 phase synchronous buck converter topology and (b) current waveforms ............. 40
2-14 Inductor current cancellation effect affected by the number of phases and duty cycle. .... 41
3-1 Block diagram of DLL based four-phase interleaved dc-dc converter. .............................. 45
3-2 Block diagram of DLL based synchronization controller ................................................... 46
3-3 Representative timing waveforms of core and duty cycle loops ......................................... 47
3-4 Block diagram and schematic of delay cells ........................................................................ 49
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3-5 Circuit schematic of the phase frequency detector .............................................................. 49
3-6 Circuit schematics of charge pump/loop filter (CP/LF) ...................................................... 50
3-7 Derivation of DLL locking range for minimum and maximum duty cycles ...................... 52
3-8 Derivation of ripple voltage due to (a) phase and (b) duty cycle errors ............................. 54
3-9a DC current imbalance in a 2-phase converter and (b) DC current sharing model ............. 56
3-10 Derivation of DLL based controller load response for a four-phase buck converter. ....... 60
3-11 Simulated loop response during (a) startup and (b) line step. ............................................. 63
3-12 Four phase inductor currents and ripple cancellation. ......................................................... 64
3-13 Die photo. ............................................................................................................................... 66
3-14 Measured bridge output waveforms with 220nF/phase. ...................................................... 67
3-15 Measured jitter while dc-dc converter is operational ........................................................... 67
3-16 Measured switching frequency and duty cycle vs. output voltage as VREF is swept ......... 68
3-17 Measured efficiency for VIN=4.8V, VOUT=3.3V, 220nH/phase and 26MHz-30MHz ....... 69
3-18 Measured load response for 0.3A current step. .................................................................... 70
3-19 Output voltage droop for a 0.3A current step. ...................................................................... 70
3-20 Measured output voltage at 4.9V/3.3V conversion .............................................................. 71
4-1 Proposed DPLL synchronization scheme for hysteretic control loop ................................ 79
4-2 A s-domain model of the charge pump PLL with dc-dc converter as a VCO.................... 81
4-3 Bode plot of the (a) open loop and (b) closed loop transfer function. ................................ 83
4-4 Transient response to a frequency step for different damping factor ................................. 85
4-5 Transient response to a frequency step versus converter duty cycle. ................................. 85
4-6 Proposed DPLL synchronized hysteretic controlled buck converter .................................. 86
4-7 DPLL block diagram .............................................................................................................. 88
4-8 Digital-Controlled Delay Line............................................................................................... 90
4-9 Hysteretic comparator Schematic.......................................................................................... 91
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4-10 Circuit schematic for non-overlapping clock generation ..................................................... 92
4-11 On-chip emulated transient load with programmable rise time and amplitude ................. 92
4-12 Layout of power switches ...................................................................................................... 93
4-13 Control word versus time in the startup simulation for different values of KP .................. 94
4-14 Simulated control word versus time in a transient response. .............................................. 95
4-15 Die photograph ....................................................................................................................... 96
4-16 Converter switching frequency versus output voltage ......................................................... 97
4-17 Jitter histogram of (a) divided clock and (b) buck converter bridge output. ...................... 98
4-18 Measured efficiency ............................................................................................................... 99
4-19 Measured load response at 1.2V/0.8V conversion using 25nF output capacitor ............. 100
4-20 Measured load response at 1.2V/0.8V conversion. ............................................................ 102
5-1 Four-phase boost converter with D-DLL based controller ................................................ 107
5-2 Cross section and J-V curves for schottky diodes with or without guard ring ................. 108
5-3 Cross section of the DENMOS and measured breakdown characteristics. ...................... 111
5-4 8-Phase Delay Locked Loop................................................................................................ 113
5-5 Digitally-Controlled Delay Line ......................................................................................... 115
5-6 Current mode PWM controller ............................................................................................ 117
5-7 Schematic of the error amplifier and the comparator in the voltage feedback loop ........ 117
5-8 Demonstration of loop instability in a current mode converter......................................... 119
5-9 Schematic of the current sensing circuit ............................................................................. 121
5-10 Schematic of the oscillator (OSC) with current ramp generator ....................................... 122
5-11 Layout for the output stages of the single phase boost converter ..................................... 123
5-12 Die photo............................................................................................................................... 124
5-13 Measured waveforms of 4-phase boost converter .............................................................. 125
5-14 Measured jitter while boost converter is operational. ........................................................ 126
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5-15 Measured efficiency ............................................................................................................. 127
5-16 Measured load response for 50% current step.................................................................... 128
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LIST OF ABBREVIATIONS
VRM Voltage regulator module
D Duty cycle of the converter
PWM Pulse width modulator
DPWM Digital Pulse width modulator
PFM Pulse-frequency-modulation
CCM Continuous conduction mode
DCM Discontinuous conduction mode
TS Switching time period
DLL Delay locked loop
DDLL Digital delay locked loop
VCDL Voltage controlled delay line
DCDL Digital controlled delay line
VCO Voltage controlled oscillator
PLL Phase locked loop
DPLL Digital phase locked loop
ΔIL Peak-peak inductor current ripple
ESR Equivalent series resistance
rms Root mean square
PFD Phase frequency detector
CP Charge Pump
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
SYNCHRONIZATION AND CONTROL OF HIGH FREQUENCY DC-DC CONVERTERS
By
Pengfei Li
December 2009 Chair: Rizwan Bashirullah Major: Electrical and Computer Engineering
Modern high performance microprocessor systems in advanced CMOS technologies
demand high peak current, large current transients, stringent voltage tolerance and high power
dissipation. In order to cope with these requirements, near-load power delivery solutions are
proposed to integrate the voltage regulator module near or within the processor die for localized
power delivery. This solution is based on high frequency dc-dc converter designs, leading to fast
load response, reduction in the component sizes and reduction in the external peak current. The
objective of this work is to explore several high frequency dc-dc converter designs and
synchronization techniques for near-load power delivery systems.
This work begins with an overview of high frequency power converter design techniques.
The multiphase hysteretic controlled converter is investigated in detail as it provides current
staggered operation for ripple reduction and fast load response. We present a novel delay locked
loop based hysteretic control scheme for high-frequency multiphase buck converters topologies
to enable synchronous and stable operation. The converter employs the switching signal from the
main voltage-regulation control loop and generates multiphase control signals with accurate duty
cycle adjustment. Its key advantages include large output voltage range determined by the
attainable duty cycle of the DLL.
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A digital phase locked loop frequency locking technique for high frequency hysteretic
controlled dc-dc buck converters is also presented. The proposed technique achieves constant
operating frequency over a wide output voltage range, eliminating the dependence of switching
frequency on duty cycle or output voltage conversion range. The DPLL is programmable over a
wide range of parameters and can be locked to a reference clock to ensure the converter
switching frequency falls outside power supply resonance bands.
Finally, this thesis reports a digital delay locked loop to synchronize a high frequency
multiphase boost converter. The boost converter employs current mode pulse-width-modulation,
and the D-DLL provides multiphase synchronization signals with accurate duty cycle control.
The proposed digital control scheme can easily accommodate high frequency dc-dc converters
with different structures and control loops, enabling fast and flexible design strategies for power
management systems.
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CHAPTER 1 INTRODUCTION
1.1 Background
The continued scaling of CMOS technologies used in high performance microprocessor
systems enables increased functionality with higher transistor count, and often times faster clock
speeds, resulting in higher current demands, increased power dissipation and heat generation. Fig.
1-1 shows the ITRS roadmap for the processor’s required current and voltage [1]. Though the
supply voltage decreases to levels as low as 0.7 V, the total power skyrockets due to the
tremendously increased supply current (>150A). Additionally, higher currents and lower
voltages decrease the processor’s load impedance, requiring power supply impedances of less
than 1mohm for accurate and efficient power delivery [2].
The continuous increase of speed and the transistor count for the microprocessor raises
another serious challenge for voltage regulation module (VRM) design. The high clock
frequency causes very high current slew rates (di/dt) when the microprocessor operation changes
from full power to sleep modes and vice versa [2]-[4]. The rate of change between these modes
is more than one thousand times per second. Fig. 1-2 shows this developing trend: the slew rate
of the processor’s current can reach ~100A/ns. This high dynamic characteristic makes accurate
voltage regulation extremely difficult, requiring a VRM with very fast transient response. Also,
this VRM must be placed in close proximity to the microprocessor to reduce the impedance of
the power delivery path [5], [6].
Therefore, power converter design for the processors of the next decade is very important
and challenging. The direct problem is maintaining the output voltage within the 5%-10%
tolerance range, thus allowing for a regulation window of only about 35mV-70mV for 0.7V DC
supply voltage. Furthermore, the voltage must maintain accuracy during large current excursions
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and fast di/dt changes. In order to meet the voltage accuracy requirements, traditional power
delivery methods employ fast on-board voltage regulators modules (VRM) and make extensive
use of external and on-die decoupling capacitances. For instance, the external decoupling
capacitance requirements for the Intel Pentium4 in 90nm process include ten 560μF aluminum
(Al) polymer capacitors, twenty four 22μF multi-layer ceramic capacitor (MLCC) size-1206
capacitors and four 4.7μF size-1206 Al electrolytic capacitors [7], increasing the cost of on-
package and motherboard decoupling capacitors, as shown in Fig. 1-3. Furthermore, at higher
frequencies above which the external dc–dc power supplies can respond, the use of on-chip
decoupling capacitors as a sole means to supply the temporary current demands is becoming
more difficult as the decrease in oxide thickness in advanced nodes leads to possible electrostatic
discharge (ESD) induced oxide breakdown and an increase in static power via gate tunneling
leakage.
One strategy to reduce the size of the external motherboard decoupling capacitor is to
operate the VRM at significantly higher switching frequencies. For instance, when the VRM is
operated at 2 MHz, only 1500μF output capacitance is required, in comparison to the 6000 μF
that is required when the VRM is operated at 500 kHz [8]. Another benefit of operating at a
higher frequency is the smaller inductor size, which also occupies significant space in VRM
design. However, high frequency converters raise efficiency and thermal issues due to severe
switching and conduction losses, especially when delivering large currents (~100-200A) to the
output. As a result, high efficiency, high power density, fast transient VRMs are critical for
meeting the power requirements of the next generation of processors.
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Figure 1-1. Processor's voltage and current of ITRS Roadmap, 2006
Figure 1-2. Intel's roadmap for processor’s slew rate
Figure 1-3. Simplified power delivery network for Intel Pentium4 processor
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1.2 Recent Progress towards Integration of High Frequency DC-DC Converters
Based on the power management issues mentioned in the previous section, it is clear that
high efficiency, high power density, fast transient dc-dc converters are critical for meeting the
power requirements of future microprocessors. Several innovative control loops have been
introduced in the literature including enhanced V2 control [9], active-droop control [10], [11],
valley current mode control [12], multiphase voltage-mode hysteretic control [13], [14],
multiphase current-mode hysteretic control [15], dynamic pulse modulator method [16], and
hybrid control [17]. The digitally controlled power converter has also been developed, improving
design flexibility and noise immunity [18]-[25]. However, some control schemes have potential
problems when applied to integrated high frequency (10s-100sMHz) dc-dc converters, including
control accuracy, control delay, multiphase synchronization and power dissipation.
Despite the development in converter control schemes, near-load converter insertion
solutions utilizing high-frequency low-voltage dc-dc converters are currently being pursued to
reduce the component sizes and the parasitic impedances of the power supply connections [15],
[26]. As shown in Fig. 1-4a, integrating the dc-dc converter near or within the processing die has
several advantages. First, the load response of a high frequency near-load converter can be
improved by several orders of magnitude to cope with fast localized transients due to the smaller
impedance between the dc-dc converters and the load circuits. Second, a high voltage conversion
ratio near the load trades voltage for current efficiency to reduce the external peak current (IEXT)
that must be supported by the power distribution network, therefore reducing the conduction loss
on the board interconnect and relaxing the stringent impedance requirements of packages and
board level traces. Third, ultra-high frequency converters can lead to a reduction in capacitor and
inductor sizes by several orders of magnitude. Thus, the cost of increased on-die area from
integrating the dc-dc converter can be traded for smaller and fewer external components at the
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board level, which decreases the cost and footprint of the external power delivery system.
Finally, localized and efficient power delivery systems naturally lend themselves to multiple
voltage domains for multi-core processing architectures as shown in Fig. 1-4b.
MB
VRM
Analog or I/O
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ESL ESR
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ESL ESRGND
IEXT
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VDD1
VDD2
Microprocessor
(a) (b)
Figure 1-4. Near-load converter insertion for processor power supply (a) on a 3D-stacked dies and (b) simplified power network
Near-load dc-dc converter insertion based on multiphase topologies can be used to reduce
external current requirements and to decrease on-die capacitance and the size of output filters,
enabling multiple supply domains in future microprocessor platforms. Multiphase techniques
have been widely used in computer power supplies to convert the 12V power supply to a lower
voltage. For instance, Fig. 1-5 shows a picture of a three phase power supply for an AMD Socket
939 processor. The three phases of this supply can be recognized by the three black toroidal
inductors in the foreground. Digital pulse width modulators (DPWM) are often used for
multiphase dc-dc converter synchronization [19], [27]. In order to synthesize the switching signal
with high resolution duty cycle, [27] uses a much faster system clock (50 MHz) to generate a 16
phase 150 kHz switching signal while [19] employs a 128 stage differential ring oscillator
generating a 100kHz to 5MHz four phase signal in 0.25μm CMOS process. Thus, it is difficult to
employ these digital techniques in future integrated dc-dc converter designs with ultra-high
http://en.wikipedia.org/wiki/Switch_mode_power_supply�
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frequency (>100MHz). In the analog controller regime, a recently reported four phase dc-dc
converter in 90nm CMOS process in [28] can operate at 480MHz by using externally generated
signals to synchronize a hysteretic controller via injection locking at the switching instants.
However, it does not ensure accurate synchronization with high resolution duty cycle. An
improved voltage-mode control loop is proposed in [14], but the conversion factor is limited to
1/N, where N is the number of converter phases, and therefore requires larger minimum input
voltage when the number of phases increases.
Figure 1-5. A multiphase CPU power delivery system for an AMD Socket 939 processor
Although there are numerous control schemes for step-down voltage regulators, multiphase
hysteretic controlled buck converters are a potential candidate for near-load VRMs as this
topology exhibits a near instantaneous load response and ripple cancellation effect. Unlike the
traditional PWM controller, the hysteretic controller is inherently stable without complex
compensation. Thus it exhibits a faster load response and further reduces the decoupling
capacitor size, given the same load transient requirement. However, combining hysteretic
controlled techniques with multiphase dc-dc converters can be challenging due to a lack of
accurate converter synchronization. For the controller to operate correctly, all bridge drive
signals must be synchronized and staggered in time, and their duty cycles must be proportional to
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the desired output voltage conversion ratio. Lack of synchronization leads to increased ripple
voltage, slower response, and larger inductor sizes. In chapter 3, we propose a delay locked loop
(DLL) based scheme to solve the multiphase synchronization problem for the hysteretic
controller.
Another problem with hysteretic control is that the free running switching frequency
changes with conversion voltage. If left unchecked, the free-running oscillations may fall in
undesired power supply resonance bands created by parasitic package inductance interconnects
and on-die decoupling capacitances. Operation at these frequencies can potentially generate large
voltage excursions in the supply network due to high impedance peaks formed by the multi-
resonant networks, compromising overall system operation and device reliability [29]. Therefore,
it is desirable to synchronize the converter to an on-chip clock generated from within the
processor to mitigate noise injection in undesirable frequency bands. A digital phase lock loop
(DPLL) based synchronization scheme is presented to solve this problem in Chapter 4.
Although the synchronization techniques in Chapter 3 and Chapter 4 are proposed for the
current-mode hysteretic buck converter, these techniques are easily compatible with other
converter topologies and voltage control loops. In Chapter 5, we demonstrate a digital delay
locked loop (D-DLL) synchronization scheme for boost converters. High frequency boost
converters integrated with advanced CMOS technology can find use in battery powered portable
systems, to deliver high voltage for display devices, audio amplifiers, and flash memory. In this
work, a current-mode pulse-width-modulation (PWM) 4-phase boost converter is operated with
100MHz switching frequency and synchronized with the proposed D-DLL based controller,
achieving automatic multiphase signal generation, accurate duty cycle control and current
sharing.
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1.3 Thesis Organization
The focus of this thesis is to investigate the synchronization scheme and control loop
designs for high frequency dc-dc converters. Our objective is to implement high frequency
digitally assisted dc-dc converters in CMOS process to enable integrated power supply systems
on-chip or on-package. This thesis is organized into six chapters and this chapter introduces the
background and motivation for integrated high frequency dc-dc converters. A literature review of
switched inductor dc-dc converter topologies is presented in chapter 2. Chapter 3 demonstrates a
synchronization scheme for high-frequency multiphase hysteretic controlled buck converters
using a delay locked loop (DLL) based controller. It can achieve automatic phase
synchronization with accurate duty cycle, and large voltage conversion range. A 25M-70MHz
multiphase hysteretic buck controller has been designed with this scheme in a 0.5μm CMOS
process. Chapter 4 describes a digital phase locked loop (DPLL) frequency locking technique for
ultra-high frequency hysteretic buck converters to mitigate noise injection in undesirable
frequency bands. The modeling of the hysteretic converter as a voltage controlled oscillator
(VCO) and the analysis of the entire system as a charge pump PLL (CPPLL) is proposed. A
90M-240MHz single phase hysteretic buck controller has been designed with this scheme in
0.13μm CMOS process. Chapter 5 reports a multiphase boost converter design utilizing digital
delay locked loop (D-DLL) with current-mode PWM control. By using integrated schottky
diodes and stacked NMOS device in 0.13μm CMOS process, a 1.2V input 100MHz 4-phase
boost converter achieved 3-5V output. Finally, conclusions and continuing work are presented in
chapter 6.
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CHAPTER 2 SWITCHED INDUCTOR DC-DC CONVERTERS
2.1 Introduction
The key principle in the switched inductor converter is the tendency of an inductor to resist
changes in current. When the inductor is being charged, it acts as a load and absorbs energy;
when being discharged it acts as an energy source. During the discharging phase, the resulted
voltage drop across the inductor is related to the slope of the inductor current, thus allowing
different output voltages generated from the absorbed energy.
In this chapter, the basic topologies for switched inductor converters are introduced in
section 2.2. The fundamental concepts of conduction mode, output ripple, and efficiency will be
discussed. Control loops including pulse width modulation (PWM) and hysteretic control are
presented in section 2.3, followed by a brief review of the multiphase technique in section 2.4.
2.2 Buck / Boost DC-DC Converters Basics
2.2.1 Buck Converter Topology
A buck converter is a dc-dc converter which generates step down voltages (i.e. input voltage
VIN is larger than output voltage VO). Shown in Fig. 2-1, between the input voltage VIN and the
load RL, is the standard buck converter topology consisting of an inductor L, an output capacitor
C, an active switch Q1, and an ideal diode D1. The duty cycle, D, is defined as the ratio between
the on-time of switch Q1 and the period of the switching signal, TS. The expression (1-D)
represents the time ratio that Q1 is off and is referred to as D` for convenience.
Fig. 2-2 shows the buck converter’s equivalent circuits as the switch Q1 turns on/off and
the voltage/current waveforms of the inductor vL(t), iL(t). During the time interval DTS, Q1 turns
on and connects VX to VIN, which reverse biases diode D1, turning it off. vL(t) is then equal to the
difference VIN-VO and iL(t) increases, as shown in Fig. 2-2a and 2-2c. During the time interval
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25
D`TS, Q1 turns off and, in order to continue the inductor current, D1 turns on, connecting VX to
ground. Then vL(t) jumps to -VO and forces iL(t) to decrease, as shown in Fig. 2-2b and 2-2c.
VIN RLC
LVX
D1
Q1 iL(t)
vL(t)VO
Figure 2-1. A standard step-down buck converter topology
VIN RLC
LiL(t)
vL(t)
VIN RLC
LVX=0 iL(t)
vL(t)
VX=VIN
VO
VO
When Q1 is on
When Q1 is off
(a)
(b) (c)
t
iL(t)
t
vL(t) VIN-VO
DTS D`TS
IO
-VO
Figure 2-2. Buck converter equivalent circuits when (a) Q1 is on, (b) when Q1 is off. (c) shows the voltage and current waveforms of the inductor L.
In terms of power transfer, the inductor L is functioning as a regulated current source
supporting the required output current, IO, during the whole cycle, TS. It is recharged by the input
power only during DTS. In terms of signal processing, the inductor and capacitor work as a
second-order low pass filter, attenuating the switching components and harmonics while also
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26
generating a DC output from the switching signal, VX. Ideally, without considering the resistive
loss on the current path, the output voltage VO is simply equal to the average value of VX.
INXO DVVV >==< (2-1)
When integrated buck converters are fabricated in CMOS technology, diode D1 is
typically replaced by a controlled NMOS switch, shown as Q2 in Fig. 2-3. Smaller turn-on
voltage drop and improved efficiency are the primary reasons for the substitution of the switch.
This topology, called a synchronous buck converter, is the modified version of the standard buck
converter (or asynchronous buck converter) in Fig. 2-1. Typically it requires a controller to
generate non-overlapping control signals to prevent Q1 and Q2 from conducting at the same time
[30].
RLC
LVX
Q2
Q1 iL(t)
vL(t)
Control
Figure 2-3. Synchronous buck converter topology
2.2.2 Boost Converter Topology
The boost converter, shown in Figure 2-4, is a dc-dc converter topology that generates
step-up output voltages (i.e. VO>VIN). The steady state waveforms and equivalent circuits for the
boost converter are provided in Figure 2-5. When the active switch, Q1, is switched on by the
gating signal, VX is grounded. Thus, inductor L has a charging path through ground and its
current level increases. During this period of DTS, D1 is reversed biased and the output load is
powered by capacitor C. As shown in Fig. 2-5b, when Q1 turns off (during D`TS), the inductor’s
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27
continuous charging current forces VX to increase to VO (neglecting the diode turn-on voltage).
Inductor L then transfers its stored energy to the load.
VIN RLC
LVX
D1
Q1
iL(t)
vL(t)VO
Figure 2-4. An ideal step-up boost converter topology
When Q1 is on
(a)
(b) (c)
t
iL(t)
t
vL(t) VIN
DTS D`TS
IIN
VIN-VO
VIN RLC
LVX=0iL(t)
vL(t)VO
VIN RLC
LVX=VOiL(t)
vL(t)VO
When Q1 is off
Figure 2-5. Boost converter equivalent circuits when (a) Q1 is on, (b) Q1 is off. (c) shows the voltage and current waveforms for inductor L.
As shown in Fig. 2-5c, during steady state, the net change in inductor current over a cycle
is zero. Therefore, VIN-VO must be negative, or equivalently, VO must be larger than VIN. In
terms of power transfer, inductor L in the boost converter connects the input voltage source, VIN,
and regulates the input current, IIN, during the whole cycle, TS, and charges the output load only
during D`TS. Therefore, the boost converter’s output voltage can be given by the following,
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28
OXIN VDVV `>==< (2-2a)
DV
DV
V ININO −==
1` (2-2b)
2.2.3 Inductor Current Ripple and Output Voltage Ripple
As shown in Fig. 2-2c, for the buck converter, the inductor current ripple can be expressed as
LDTVV
I SOINL)( −
=∆ (2-3)
Fig. 2-6 shows the typical timing waveforms for the capacitor current iC(t) in the buck and
the boost converter, respectively, assuming the capacitor charging current is positive. For the
buck converter, iC(t)=iL(t)-IO and thus ΔIC=ΔIL, as shown in Fig. 2-6a. In the steady state, the
capacitor’s current has 0 dc value and the total charge dumped and removed from the output
capacitor is ΔIL/4fS. Therefore, the output voltage ripple (half of the peak-to-peak value) can be
written as
LCfDVV
CfIVV
S
OIN
S
LCO 28
)(8
−=
∆=∆=∆ (2-4)
t
iC(t)
- IODTS D`TS
t
iC(t)
DTS D`TS
-∆IL/2
∆IL/2
(a) (b)
Figure 2-6. Capacitor current waveform for (a) buck converter, and (b) boost converter
As shown in Fig. 2-5c, the inductor current ripple in the boost converter can be expressed as
LTDVVI SOINL
)1)(( −−=∆ (2-5)
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29
Also, iC(t)=-IO during DTS and iC(t)= iL(t) during D`TS, as shown in Fig. 2-6b.
Since the change in output voltage, ΔVO, is quite small compared to VO, it can be assumed that
the load current IO remains constant at VO/R. When the capacitor current is constant, its voltage
changes linearly with time and the voltage ripple is given by
RCfDV
CDT
RV
VS
OSOO =×=∆ (2-6)
2.2.4 Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM)
So far the converters analyzed were assumed to operate in the continuous conduction mode
(CCM). In this mode, the inductor’s current is continuous and its average value (dc value) is
larger than half of the current ripple (ΔIL/2). However, when the required output power level
becomes small enough, converters can enter the discontinuous conduction mode (DCM).
Consider the buck converter as an example, as shown in Fig. 2-7; for very light loads, the
inductor current ramp iL(t) falls to zero during part of the period. In this case, the inductor is
completely discharged because diode D1 in Fig. 2-1 cannot support the negative current of the
inductor (i.e. negative iL indicates the reverse leakage current from the load). Then VX is charged
to VO and D1 is off.
Note that the synchronous buck converter in Fig. 2-3 cannot enter DCM in light loads. This
is because an NMOS switch, unlike a diode based rectifier, allows negative inductor current iL,
indicating a reverse leakage current from the load to ground. This current leakage costs an
additional power loss and undermines the light load efficiency. To solve this problem, the control
circuit needs an auxiliary loop to sense the zero-crossing current, indicating when to turn off the
NMOS switch properly [31].
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30
VIN RLC
LVX=VO iL(t)
vL(t)
VO
When Q1 and
D1 are off
(a) (b)
t
iL(t)
t
vL(t) VIN-VO
DTS
-VO
TS0
Figure 2-7. Buck converter operating in DCM (a) equivalent circuit when Q1 and D1 are both off
and (b) inductor voltage and current waveform
The inductor value determines the slope and the amplitude of iL, and thus determines when
the converter enters DCM. For a buck converter with a load resistance of RL=Rlim, the load
current at the boundary between CCM and DCM, equals to half of the inductor current ripple (Δ
IL/2). Based on Eq. 2-4 and Eq. 2-1, this relationship can be written as
( )S
INLO
LfDDVI
RV
21
2lim
−=
∆= (2-7)
Therefore, the minimum inductor value, Lmin, which guarantees CCM operation for the
specified load range (R ≤Rlim) is
( ) ( )SSO
IN
fRD
fVRDDV
L2
121 limlim
min−
=−
= (2-8)
In other words, when L
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31
Table 2-1. Summary of CCM-DCM characteristics for the buck and boost converters
Converter Lmin VO in CCM VO in DCM
Buck
( )SfRD
21 lim−
DVIN
2
811
2
RDLf
V
S
IN
++
Boost
( )
SfRDD
21 lim
2−
DVIN−1
2
2112
++
SIN Lf
RDV
2.2.5 Overall efficiency analysis for synchronous buck converter
The conduction efficiency calculation in dc-dc converters only includes the conduction
losses caused by the parasitic resistive impedances (the on-resistance of the power MOSFET and
diode, the inductor’s ESR). In contrast, the overall efficiency includes the conduction losses and
the switching losses due to the parasitic capacitive impedances of the circuit components. Here
we only demonstrate the overall efficiency analysis for the synchronous buck converter topology
as an example (see Fig. 2-3). The main power loss comes from (1) the power MOSFET and the
related gate drivers, and (2) inductor L; the power dissipation of the controller circuits and the
output capacitors are typically small as compared to the loss of (1) and (2); the short circuit
power loss is neglected, assuming non-overlapping control signals are applied for the power
MOSFET. Therefore, the conduction loss and the switching loss for the power MOSFET and the
related gate drivers are given by the following [33].
BRDGL
ORMOS RI
IP
∆+=
3
22
_ (2-9a)
2_ 1 INSBRDGCMOS
VfCP−
=αα
(2-9b)
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32
( )DWR
DWR
RNMOS
NMOS
PMOS
PMOSBRDG −+= 1 (2-9c)
( ) ( ) ( ) MOSNMOSPMOSdbgdgsoxNMOSPMOSBRDG CWWCCCCWWC +=++++= 2 (2-9d) where PMOS_R is the conduction loss, which is inverse proportional to the width of the
NMOS (WNMOS) and PMOS (WPMOS) in Eq. 2-9c; PMOS_C is the switching loss proportional to the
width of the MOSFETs (WPMOS+WNMOS). RBRDG and CBRDG are, respectively, the equivalent series
resistance and equivalent capacitance of the buck bridge. The bridge consists of both high-side
PMOS and low-side NMOS transistors. The tapering factor of the gate drivers, α, is used in Eq.
2-9b to include the additional loss from the gate driver. RPMOS and RNMOS are, respectively, the on-
resistance of a 1-μm-wide PMOS and NMOS. Cox, Cgs, Cgd, and Cdb are the gate oxide, gate-to-
source overlap, gate-to-drain overlap, and drain-to-body junction capacitances, respectively, of a
1-μm-wide MOSFET. For simplicity, we assume that these parameters are the same for both
PMOS and NMOS devices. The sum of these capacitances is represented by CMOS in Eq. 2-9d.
As given by above equations, increasing the MOSFET width decreases the conduction
loss while increasing the switching loss. Thus, for a target load current IO and the converter
frequency fS, the optimum widths for PMOS (WPMOS_OPT) and NMOS (WNMOS_OPT) that optimizes
the overall efficiency is given by
2
22
_
1
3
INsMOS
LOPMOS
OPTPMOSVfC
IIDRW
−
∆+
=
αα (2-10a)
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33
( )
2
22
_
1
31
INsMOS
LONMOS
OPTNMOSVfC
IIDRW
−
∆+−
=
αα (2-10b)
The conduction loss related to the inductor is
22
2
3 INSindindL
Oind VfCRIIP +
∆+= (2-11)
where Rind and Cind are the parasitic series resistance and the parasitic stray capacitance of the
inductor, respectively.
Considering all the primary loss mechanisms described above, the overall efficiency of the
synchronous buck converter can be expressed as
22
222
22
2
__
313 INSindindL
OINSBRDGBRDGL
OLO
LO
indCMOSRMOSO
O
VfCRIIVfCRIIRI
RI
PPPPP
+
∆++
−+
∆++
=
+++=
αα
η
(2-12)
where PO is the output power and RL is the load resistance. If the power MOSFET widths and the
input/output voltages are fixed, the peak efficiency based on the Eq. 2-10 only occurs at the
target load IO. At lighter loads than IO, efficiency degrades because the switching loss dominates
the total input power. At heavier loads, the efficiency decreases due to higher conduction losses
associated with the inductor and bridge resistances. Additionally, high input voltage VIN leads to
smaller duty cycle for a fixed VO, and makes high efficiency converter design more difficult due
to the VIN related components shown in Eq. 2-12.
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34
2.3 Control Scheme of DC-DC Converters
2.3.1 Voltage Mode Pulse Width Modulation (PWM) Controller
PWM is the most common control scheme for dc-dc converters. As shown in Fig. 2-8. the
control loop senses the output voltage, VO, and subtracts this from a reference voltage, VREF, to
establish an error signal (VERROR). This error signal is compared to a fixed frequency carrier
waveform (VCAR), usually triangular or saw tooth in shape, as shown in Fig. 2-8b. The
comparison between VERROR and VCAR results in a square wave signal VX and generates a dc
output VO. When VO changes due to the varying input/output conditions, VERROR changes
accordingly to modulate the output pulse width. This pulse width modulation then moves the
output voltage towards VREF due to the negative feedback loop. Let the carrier waveform VCAR
vary from VCAR_min to VCAR_max, then the duty cycle D can be estimated to be as
min_max_
min_
--
CARCAR
CARERROR
VVVV
D = (2-13)
VINPWMgenerator
LVXrL
IOCOUT
VO
Bridge drivers
+
-
+
-
Compensation
VREF
VERROR
VCAR
Erroramplifier
VINPWMgenerator
LVXrL
IOCOUT
VO
Bridge drivers
+
-
+
-
Compensation
VREF
VERROR
VCAR
Erroramplifier
(a)
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35
t
t
VX(t) VIN
DTS
VERROR
VCAR(t)
0
t
t
VX(t) VIN
DTS
VERROR
VCAR(t)
0 (b) Figure 2-8. Voltage mode PWM buck converter’s (a) schematic and (b) waveforms
This control scheme is optimized for output voltage regulation, but is not preferred in
terms of loop dynamics [34], [35]. As shown in Fig. 2-8a, an RC compensation circuit is required
to ensure the stability of the PWM control loop. The design of the compensation circuit can be
complicated, especially when the load current has large dynamic range or when the load
capacitor is not fixed in the design. Also, increased stability by the compensation circuit design
(i.e. increased phase margin) degrades the loop response to a load or line transient.
2.3.2 Variable Frequency Controller
2.3.2.1 Current mode hysteretic controller
PWM control is a fixed frequency control loop, in which the duty cycle is variable. In
contrast, a variable frequency controller has variable duty cycle and switching frequency
determined by the load conditions. Current mode hysteretic control is one type of variable
frequency controller and is favored due to its simple topology and fast transient response. Fig. 2-
9 shows a current mode hysteretic controlled buck converter comprised of a hysteretic
comparator, a cascade of buffers to drive the high-side PMOS and low-side NMOS bridge, a
switched inductor L and the feedback network RF, CF. The feedback network RF and CF is an RC
integrator used to estimate the inductor current.
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36
VINHystereticComparator
L
CFRFRD
VX
VFB
VREFrL
IOCOUT
VO
+
-
Bridge drivers
Figure 2-9. Single phase current mode hysteretic buck converter
VREF+VH
VREFVFB
VXVIN
0
DTS
VFB
time
VXDTS
VREF+VH
VREF
VIN
0
timeτON τOFF
(a) (b) Figure 2-10. Voltage waveforms at nodes VFB and VX (a) without converter propagation delay
and (b) with finite propagation delay.
Fig. 2-10a shows the idealized voltage waveforms VFB at the feedback node and VX at the
bridge output. The switching frequency of the buck converter can be derived from the slope of
VFB at the feedback node and the hysteretic window VH. If we consider the finite propagation
delays of the comparator, buffers and bridge, as shown in Fig. 2-10b, the switching frequency
can be expressed as [36]
( )( ) ( )
1
11/
−
+
−+
−=
DDDDVVf OFFONINHRCS
τττ (2-14a)
where τRC equals RFCF, τON and τOFF correspond to the finite propagation delays of
switching the inductor to VIN and ground, respectively, and D is the duty cycle. If the propagation
delays are assumed to be equal (τON=τOFF=τD), the switching frequency reduces to
-
37
( )( ) DINHRCS VVDDf
ττ +−⋅
=/1 (2-14b)
This suggests that the maximum switching frequency occurs when D=0.5, or
fMAX=0.25/(τRC(VH/VIN) + τD). Since D sets the output conversion ratio VO/VIN, the switching
frequency exhibits a parabolic dependence on the conversion ratio. If the conversion range of the
converter is D=0.2 to D=0.8, the switching frequency will vary from 0.64fMAX to fMAX.
Unlike a PWM control, the hysteretic control loop does not require an error amplifier with
frequency compensation, resulting in a wider bandwidth and simpler design. Therefore, it reacts
faster to load and line transients than a PWM does.
If resistor RD is introduced between the comparator output and VFB as shown in Fig 2-9,
the converter output impedance will exhibit a resistive response for improved load response [37].
When the converter is loaded with current, the output will exhibit a dc error proportional to the
output resistance, forcing the output voltage to “position” itself along a load line with the slope
of the output resistance – a concept known as “voltage positioning” [15], [37]. At the output of
the hysteretic comparator the average voltage is DVIN, which is reduced by the bridge series
resistance RBRDG and the inductor effective series resistance rL at the bridge output. It follows that
the average voltage at the output of the buck converter is
( ) OLBRDGINXO IrRDVVV ⋅+−== (2-15)
And the average voltage can be expressed as [15]
OBRDGFD
DINFB IRRR
RDVV ⋅+
−= (2-16)
where VIN and are the input voltage and the average bridge output voltage,
respectively, and is the average output current. Since the negative feedback loop of the
controller forces the voltage variation of VFB to match the hysteretic window, VH, set by the
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38
comparator, the average voltage ‹VFB› is given by VREF + VH/2, where VREF is the input reference
voltage. Then the average output voltage can be expressed as
OLBRDGFD
FHREFO IrRRR
RVVV ⋅
+
+−+=
2 (2-17)
Thus, the output impedance can be adjusted by selecting RD to yield an improved load response
at the expense of a dc error in the output voltage.
2.3.2.2 Voltage mode hysteretic and constant on-time controller
Unlike current mode hysteretic control, voltage mode hysteretic modulation senses the
output voltage VO as the feedback ramp, as shown in Figure 2-11. When the feedback voltage
exceeds the reference voltage VREF, the comparator output goes low, turning off the upper
switch. The switch remains off until the feedback voltage falls below the reference hysteresis.
Then, the comparator turns on the switch, allowing the output voltage to rise again. As
mentioned previously, this technique is fast, simple, and low-cost, while its disadvantage is the
varying switching frequency [38], [39]. In steady state, the hysteretic window VH limits the
output voltage ripple, and thus we can derive the switching frequency as
( )H
CINS LV
DDrVf −= 1 (2-18)
where rC is the ESR of the output capacitor. A second disadvantage is that this control
scheme requires a triangle-like voltage ripple for stable operation. Thus, the ESR of the output
capacitor cannot be too small [40]. Otherwise the output voltage will not cross the hysteretic
comparator thresholds in phase, and the control scheme will not operate in a smooth and stable
manner. Typically, an electrolytic capacitor is used for COUT to meet this voltage ripple
requirement.
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39
VINHystereticComparator
LVXVREFrL
IO
COUT
VO+
-
Bridge drivers
rC
VINHystereticComparator
LVXVREFrL
IO
COUT
VO+
-
+
-
Bridge drivers
rC
Figure 2-11. Single phase voltage mode hysteretic buck converter
VINHystereticComparator
LVX
VFB
VREFrL
IOCOUT
VO
+
-
Bridge drivers
ON-timeone shot
VINHystereticComparator
LVX
VFB
VREFrL
IOCOUT
VO
+
-
+
-
Bridge drivers
ON-timeone shot
Figure 2-12. Single phase constant on-time buck converter
The constant on-time (COT) control is a modified version of a conventional voltage mode
hysteretic control. In a COT controller, the on time of the upper switch is fixed and the off-time
is varied according to a reference voltage [41]. The implementation of the control scheme is
shown in Figure 2-12. A comparator samples the output voltage VO at a fixed sample frequency
and compares it to the reference VREF. When VO
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40
Thus the switching loss is greatly reduced with slower frequency in light loads. This control
scheme provides the advantage of high efficiency in ultra-light loads and is ideal for the
converter in standby mode. However, a COT controller used with a varying input supply results
in variable input-to-output energy transferred per switching cycle, producing widely varying
ripple and average output voltages [43].
2.4 Multiphase Technique
Multiphase dc-dc converters are often used in computer power supplies to convert the 12V
supply to roughly 1V. This technique is suitable for modern microprocessors which require
~100A current and have very tight ripple requirements (~10mV). Typical motherboard power
supplies use 3 or 4 phases, although control IC manufacturers allow as many as 6 phases [44].
This technique is often used with the synchronous buck topology, where the basic buck
converters are placed in parallel between the input and load.
IL1
IL2
IL_tot
IL_tot
RLC
CLK1IL1
L1Controller
CLK2IL2
L2Controller
IL1
IL2
IL_tot
IL_tot
RLC
CLK1IL1
L1Controller
CLK2IL2
L2Controller
IL_tot
RLC
CLK1IL1
L1Controller
CLK2IL2
L2Controller
(a) (b)
Figure 2-13. (a) Basic 2 phase synchronous buck converter topology and (b) current waveforms
Fig. 2-13 shows a basic 2 phase buck converter with a dashed line to represent the feedback
network. There is 180 degree phase shift between CLK1 and CLK2, so the inductor current IL1
and IL2 also has 180 degree phase shift. After adding these inductor currents together, the ac
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41
components are cancelled which results in a smaller current ripple per total inductor current
output IL_tot. Therefore, we can achieve smaller voltage ripple with the same LC filter or we can
use a smaller sized LC filter to obtain the same ripple performance. Another important advantage
provided by the multiphase converter is that the load current splits among the n-phases of the
multiphase converter, allowing the heat generation on each of the switches to be spread across a
larger area.
N=2N=3
N=4
1.0
0.8
0.6
0.4
0.2
00 0.2 0.4 0.6 0.8 1.0
Duty Cycle 0.1 0.3 0.5 0.7 0.9
ΔIL_tot /ΔIL N=2N=3
N=4
1.0
0.8
0.6
0.4
0.2
00 0.2 0.4 0.6 0.8 1.0
Duty Cycle 0.1 0.3 0.5 0.7 0.9
ΔIL_tot /ΔIL
Figure 2-14. Inductor current cancellation effect affected by the number of phases (N=2,3,4) and duty cycle.
In the multiphase buck converter, the staggered operation of each phase produces a current
ripple cancellation effect at the output node, where the total current IL_tot is integrated onto the
output capacitor. For an ideal N-phase buck converter, the ratio of the magnitudes of the output
current ripple ΔIL_tot to the current ripple ΔIL flowing in each phase is denoted as α and is given
by the following expression [45]:
( )DD
DN
mNmDN
II
L
totL
−
−
+
−
=∆
∆=
1
1_α (2-18)
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42
where m=floor(N·D) is the maximum integer that does not exceed N·D, N is the number of
phases and D is the duty cycle. Fig. 2-14 shows how the current ripple cancellation is affected by
the number of phases (N=2, 3, 4) and duty cycle. Only at duty cycles of 1/N, 2/N,…,(N-1)/N, can
the N-phase converter achieve ideal current cancellation with zero ripple output. On average,
converters with more phases have better ripple cancellation effect across most of the duty cycle
range. A multiphase topology provides an additional benefit: the load response can be improved
significantly because the load is monitored by an N-times higher sampling frequency.
Additionally, large increases/decreases in load current can be addressed by turning on/off
multiple phases to improve the overall system efficiency [46].
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43
CHAPTER 3 MULTIPHASE SYNCHRONIZATION WITH DELAY LOCKED LOOP
3.1 Introduction
Although there are numerous embodiments of step-down voltage regulators for near-load
power delivery systems, the switched-inductor multiphase and hysteretic controlled dc-dc
converter topology is a suitable candidate as it exhibits a near instantaneous load response and
ripple cancellation effect via current sharing [47]. Unlike the pulse-width modulation (PWM)
controller, the hysteretic controller exhibits a faster load response and is inherently stable but is
difficult to synchronize to multiple phases. For the controller to operate correctly, all bridge drive
signals must be synchronized and staggered in time, and their duty cycles must be proportional to
the desired output voltage conversion ratio. Lack of synchronization leads to increased ripple
voltage, slower response and larger inductor sizes. External synchronization of the multiphase
hysteretic controller is feasible by direct injection of synchronization signals into the reference
voltage nodes of the hysteretic comparators [15]. However, this approach requires that the
amplitude, shape and frequency be carefully controlled to achieve proper frequency lock.
Multiphase topologies based on PWM controllers reported in [19] were synchronized using high
frequency clocks in relation to the switching frequency and are therefore not suitable for very
high frequency multiphase converters, whereas multiphase voltage-mode hysteretic controllers
based on [14] exhibit an output conversion range limited to 1/N of the input voltage, where N is
the number of converter phases, and therefore requires larger minimum input voltage when the
number of phases increases.
In this chapter, we demonstrate a synchronization scheme for high-frequency multiphase
hysteretic controlled dc-dc converters using a delay locked loop (DLL) controller that achieves
automatic phase synchronization with accurate duty cycle and large voltage conversion range. A
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44
four phase hysteretic buck converter was implemented in 0.5µm CMOS process and is
operational from 25MHz to 70MHz with an output voltage conversion range of 17.5%-80%. In
section 3.2, we present a DLL based multiphase hysteretic buck converter design. Detailed
analysis of the proposed converter’s performance is discussed in section 3.3. Simulation results,
measurement results and concluding remarks are presented in section 3.4, 3.5 and 3.6,
respectively.
3.2 DLL Based Multiphase Hysteretic Controller
3.2.1 System Architecture
The proposed DLL-based multiphase hysteretic controller for a four-phase buck converter is
shown in Fig. 3-1. The converter consists of four single-phase modules, one of which operates
independently to set the desired output voltage from VREF and generate the reference clock
(CKS0) for the DLL. The switching frequency and duty cycle is thus determined by the first
hysteretic control loop, which can be digitally programmed by changing the value of the
feedback resistor RF. When the DLL is locked, the synchronization signals (CKS90, CKS180 and
CKS270) for the remaining converters are appropriately offset by 90°, 180° and 270° to stagger
the inductor currents for ripple cancellation. Using this method, the hysteretic controlled bridge
and the remaining DLL controlled bridges are combined seamlessly without external driving
clocks to synchronize the phases. In addition, the output voltage range is now determined by the
attainable duty cycle of the DLL, which is larger than previous designs [14], [15]. To achieve
proper synchronization between N output phases, the DLL must be able to 1) track the switching
frequency of the master hysteric controller, 2) maintain a 360o/N offset between each phase and
3) avoid duty cycle distortion in the bridge drive signals.
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L
LPhase 180
Phase 270
VPH180VSENSE
HystereticComparator
DLL
L
CF
RFRD
VIN
VXA1
+
-
VFB
VREF
R1
R2
VPH0
VSENSE
Phase 0
L
CF
RFRD
VIN
VX VPH90
Phase 90
VPH270VSENSE
VSENSE
IOCOUT
VO
Control bits
CKS0
CKS0
CKS90
CKS270
CKS180
Figure 3-1. Block diagram of DLL based four-phase interleaved dc-dc converter.
3.2.2 Delay Locked Loop (DLL) Design
Fig. 3-2 shows the block diagram of the DLL controller. The DLL consists of three loops: a
core loop for fine phase synchronization and two auxiliary loops for duty cycle adjustment and
coarse phase tuning. The voltage control delay line (VCDL) is composed of eight identical delay
cells that are controlled primarily by the coarse loop via the main bias generator block. The
coarse loop consists of two replica delay cells which are identical to the VCDL cells, an XOR
phase detector and a charge pump (CP). At the input of the coarse loop, a divide-by-2 circuit
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46
divides down the reference clock (CKS0) from the output of the hysteretic comparator to produce
a 50% duty signal. The XOR gate compares the divided down clock with the same signal
delayed by the two replica delay cells. Under locked conditions, the coarse loop voltage
(VCOARSE) at the output of the charge pump forces the delay of the two replica delay cells to be
approximately one fourth of the reference clock period. Since the same delay cells are used in the
VCDL, the delay of the VCDL will be approximately equal to the reference clock period. It can
be shown that by intentionally setting the coarse loop charge pump pull-up current to three times
the pull-down current, the DLL lock range can be increased to 7:1 [48].
PFD
Startup
CP LF
CP LF/2DD
DD DD DD DD
VDD/2
CP LF
VPcoarseVNcoarse
VCOARSE
VFINE
UP1
UP2
DN2
DN1
VPcore
VNcore
VCDL
Core Loop
Coarse Loop
Duty Cycle Loop
VDUTY
CKS90 CKS180 CKS270CKS0
from hysteretic
comparator
To bridge drivers
CKS360
CKS0
BiasGen
BiasGen
Figure 3-2. Block diagram of DLL based synchronization controller
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CKS0
UP1
DN1
(UP2)
(DN2)
CKS360
CKS0
CKS360
Figure 3-3. Representative timing waveforms of core and duty cycle loops
Fig. 3-3 shows timing waveforms of the core and duty cycle loops. The core loop
compares the outputs of the hysteretic comparator (CKS0) and the VCDL (CKS360) using a phase-
frequency detector (PFD) to fine tune the VCDL. Up (UP1) or down (DN1) pulses proportional
to the phase difference of the input clock signals are generated by the PFD and fed to the charge-
pump (CP) to produce a proportional current filtered by a first order loop filter (LF), thereby
reducing or increasing VFINE until the clock edges are aligned by the negative feedback loop of
the DLL.
As shown in Fig. 3-3, the duty cycle of the reference clock generated by the hysteretic
comparator can deviate from 50%. A dedicated duty cycle loop is used to correct for mismatch
arising from unbalanced rise and fall times in the VCDL. Since the duty cycle of the reference
clock signal CKS0 at the output of the hysteretic comparator determines the buck converter
voltage conversion ratio, the VCDL must maintain accurate duty cycle across all its phases to
ensure proper current sharing operation of the multi-phase converter. The duty cycle correction
loop comprised of a charge pump and loop filter operates on inverted CKS0 and CKS360 signals
(or UP2 and DN2) to generate a voltage VDUTY proportional to the error in pulse widths. The
voltage VDUTY is used to change the current ratio in the delay cells and adjust the duty cycle of
the VCDL.
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3.2.3 Circuits Implementation
3.2.3.1 Delay cell
Fig. 3-4 shows the basic VCDL delay cell configuration. It is composed of two current
starved inverter delay cells (DC), one duty cycle delay (DCD) cell and two inverters, one to
buffer the following delay stage and the other to buffer the input of the drivers to the dc-dc
bridges. The current starved delay cells (DC) are controlled using VPcore and VNcore from the bias
generator circuit. These control signals are determined by VFINE and VCOARSE from the core and
coarse loops and used primarily to adjust the delay and align the rising edges of reference clock
and VCDL output. VDUTY is used to adjust the current ratio of the DCD cell to ensure proper duty
cycle matching. Since the duty cycle is applied to all the delay cells, the duty cycle is preserved
for all output phases. Although VDUTY is adjusted simultaneously with VPcore and VNcore, a
sufficiently smaller loop gain in the duty cycle correction loop ensures overall DLL loop
stability. The relative gain of VFINE and VCOARSE over the VCDL can be adjusted using a V-I
current summing circuit in the bias generator to produce voltages VNcore and VPcore that directly
control the delay cells. The bias generator circuit employs two weighted current sources (P1 and
P2) to control the coarse and fine delay tuning range, respectively, and a current sink IMIN to set
the minimum bias current and thus the maximum delay of the delay cells. In the coarse loop
VDD/2 is applied to the bias generator instead of VFINE and the control voltages VPcoarse and
VNcoarse control the replica delay cell (see Fig. 3-2).
3.2.3.2 Phase frequency detector and startup circuit
Schematic of the phase frequency detector (PFD) is provided in Fig. 3-5. The PFD is
comprised of a conventional sequential PFD and a startup circuit. The startup circuit is used to
disable the charge-pump for eight reference cycles and reset the core loop control voltage (VFINE)
to mid voltage (i.e. VDD/2) in the event of lock failure when VFINE drops below 0.1V. Lock
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49
failure problem for the core loop might occur at the startup condition before the coarse loop is
locked, and the core loop’s control voltage VFINE is stuck at ground potential. In this case, the
startup circuit generates a zero pulse from the latched comparator’s output as the reset signal.
After eight reference cycles, the reset signal becomes “1” to restart the core loop.
VPcore
VNcore
in out
VPcore
VNcore
in out
BiasGen
DC DCD
Delay cell duty cycle control
VDUTY
Current starved delay cell
DC DCDDCin out
VDUTY
VFINEVCOARSE to bridge
drivers
VFINEVCOARSE VPcore
VNcore
P1 P2
IMIN
Bias Generator
Figure 3-4. Block diagram and schematic of delay cells
UP
DN
CKS0
CKS360
D QQ
Phase Frequency Detector
reset
CKS0 8÷
Startup Circuit
0.1V
0.5VDD
VFINE
From CP/LF
Figure 3-5. Circuit schematic of the phase frequency detector
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50
3.2.3.3 Charge pump and loop filter
The static phase offset in the DLL mainly stems from the timing mismatch in phase
detector and the current mismatch in the charge pump. By matching the up and down signal
propagation paths in phase detector, the phase detector mismatch can be neglected given the
moderate operating frequencies. Therefore, the dominant source of static phase error is caused by
charge pump current mismatch which can be approximated as:
CP
CP
S
ON
II
TT ∆
⋅=ξ (3-1)
where TS and TON are the reference period and the charge pump on-time, respectively; ΔICP
is the charge-pump current mismatch and ICP is the charge pump current. Notice that the charge-
pump mismatch is more relevant in the auxiliary duty cycle loop as the on-time is equal to the
duty cycle of the converter (D).
Startup
DN
UPUPVO
P1 P2 P3
N1 N2 N3
VR
P4 P5
N5N4
Current Steering Network
VN2
DN
UPLoopFilter
VODN
ICH
ChargePump
Figure 3-6. Circuit schematics of charge pump/loop filter (CP/LF)
The charge pump circuit in Fig. 3-6 provides accurate current matching to reduce static
phase error [49]. Static phase error or offset in the DLL stems mainly from timing mismatch in
phase frequency detector and current mismatch in the charge pump. Timing mismatch in the
PFD is mitigated by matching the up and down signal propagation delays. The charge-pump
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consists of matched PMOS current sources P1-P3 and the NMOS current sinks N1-N3, with
minimum sized MOS switches in between to reduce the effect of charge feedthrough. An error
amplifier inserted between the current mirrors improves current matching by forcing VR equal to
VO, such that when UP is enabled the source currents are equal (IP2=IP1=IN1), and when DN
enabled the sink currents are equal (IN2=IN1=IP1). In addition, a current steering network
comprised of N5 and P5 legs is used to minimize current spikes across the output capacitor filter.
When switch N4 is disabled, the complementary N5 switch turns on to maintain the N2 drain
voltage (VN2) stable. Without the current steering legs the drain node of N2 can be discharged to
ground leading to current spikes at the switching instants of the UP and DN signals. The
schematics for the CPs and LFs in all three loops (see Fig. 3-2) are the same, except in the coarse
loop where the P2:P1 current ratio is set to 3:1 instead of 1:1 as the pull-up current is three times
the pull-down current for improved DLL locking range [48]. In addition, the current to loop-filter
capacitance ratio are 3x190µA/18pF, 130µA/12pF and 45µA/18pF for the coarse, fine and duty-
cycle loops, respectively.
3.3 Analysis for DLL based Multiphase Buck Converter
3.3.1 Voltage Conversion Range
The voltage conversion range is largely determined by the duty cycle range that is
attainable by the DLL based controller. As shown in Fig. 3-7, since the output voltage is
proportional to the duty cycle, the maximum output voltage VOmax is DmaxVIN and the minimum
output voltage VOmin is DminVIN, where Dmax and Dmin are the maximum and minimum duty cycles
of the DLL, respectively. The duty cycle range in turn i