2010 foleded voltage follower.pdf

8/10/2019 2010 Foleded voltage follower.pdf

1/4

IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)

A Fast-Trasiet LDO Based o

Buffered Flipped Voltage Follower

Hua Cen and Ka Nang eungDepartment of Electronic EngineeringThe Chinese University of Hong Kong

Hong Kong, ChinaEmail: [email protected];[email protected]

Abtrct this work, the analysis of the ippedvoltage follower (FVF) based single-transistor-control(STC) LDO is given. Two evolved versions of FVF,cascaded FVF (CAFVF) and level shied FVF (LSFVF),are studied. Then, a buffered FVF (BFVF) for LDOapplication is proposed, combining the virtues of bothCAFVF and LSFVF structures. It alleviates theminimum loading requirement of FVF and the

simulation result shows that it has faster transientresponse and better load regulation.

yworFl vol oowr low root rltor owr mmt

I. NTRODUCTION

Low-dropout regulator (LO) is a low-cost powermanagement solution which is especially suitable for systemon-a-chip (SoC) applications. The invention of singletransistor-controlled (STC) LO rported in [1] and [2]based on ipped voltage follower (FVF) [3]. Theinformation stated in [4] is a response to the upcoming

challenges in LO design, and it broadens the horizon ofpossible LO strctures.

In this work, the FVF-based STC LO is analyzed. Aerthat, two evolved version of FVF, cascaded FVF (CAFVF)and level shied FVF (LSFVF), are evaluated. Then, abuered FVF (BFVF) for LO application is proposed,combining the vrues of both CAFVF and LSFVFstructures. The loop response, stability and transient responseare adressed in this paper.

II. FVF BASED STC LO

The STC LO inoduced in [2] is shown in Fig. 1. Here,M is the power transistor, M is a control transistor and iBIASis the biasing current. Va is the output-voltage node, andVC is a d cntro vtag. CL is he laing apact. Rmodels the equivalent series resistance (ESR) of the loadingcapacitor and models the loading cuent.

The conguration of M, M and iBIAS form a typicalFVF structure, where the voltage at the source of Me Vafollows the voltage at the gate of Me VC7. It is dened asa 'ipped structure since the bias cuent appears at thedrain terminal of M instead of the source terminal, as that insimple source follower. As a voltage follower, the dc voltageat Va can be expressed as

978-1-4244-9996-0/10/$26.00 2010 IEEE

V =V/ +Vc 1where VSG(Me is determined by iAS and the size of M.

d

igure tructure o STC LDO.

Moreover, in [2], a circuit is also proposed to generate thecontrol voltage (i.e. VCT) and guarantees that Va is equal tothe reference voltage. The circuit in [2] is applicable to allthe LOs that are based on the FVF family.

ne major drawback of STC LO is that it has minimumloading requirement. If the loading is smaller than theminimum loading requrement, the gate voltage of M needsto increase to reduce the overdrive voltage of M. However,this will push M to triode region. In that case, the outputvoltage of the LO is altered.

The small-signal circuit is shown in Fig. 2, where gand g denotes the transconductance of ansistor M andM, and are the output resistance of M and M,respectively, n models the output resistance of the current

source iBIAS, and Cp models the gate capacitance of M. the ansin sns o he STC O a stp

nction of h can be considered as the input signal, and thevariations on as the ouut signal. To elucidate thefeedback loop in Fig. 2, the signal block diagram is shown inFig. 3. The forward gain is

Af =(/SCL+R)11rop (2)

and the feedback gain is:Ab =gmc l+gmp k II1sC (3)


2/4

+

I

' rap

Iep

Figure 2. Small signal circuit o the STC LO.

The transfer nction of is given by

voliL =-Af(l+AfAbwhich is also the output impedance of the LO.

Figure 3. Block diagram othe signal ow graph o the STC LO.

(4)

n the other hand, the ccuit can be regarded as a sourcefollower. In that case, Vc is viewed as the input signal and Vis viewed as the output signal. The transfer nction om Vc

to V is therefore given byvolv

=-(l+AfAbIt is observed that, in both cases, the loop gain isOI f b(5)

(1+ sCRE)(1+ s C / gm ) (6) gmpgmJrp . p(1+ sCp)(1+ sr"C)

Therefore, the stability of the FYF-based LO can beanalyzed om both perspectives, and they are equivalent.For example, if a test signal is injected at vc, the output sialat V is expected to reect the loop gain of the system, as long

as the feedback loop is broken at V. This is achieved byinserting ideal voltage controlled voltage source (YCYS) andcuent control cuent source (CCCS) for isolation. Thecircuit for ac open loop simulation is shown in Fig. 4. In Fig.4, the connection at Va is broken. The dc biasng of M ismaintained by a CCCS conected at the drain of M. Itcopies the drain current of M. Notice that this CCCS alsocarries the ac current of M, which corresponds to the feedforward path in Fig. 4. The output voltage is fed into an ideallow-pass lter that blocks the ac signal, and the lteredvoltage is used to set up the dc voltage of M. For more

accurate modeling, a resistor rc is added at Va to model theeffect output resistance of M at Va.

Two le-half-plane (LHP) poles and two LHP zeros areobserved in the loop gain om (6). PI = - lCr is thedominant pole, and P = - lrnC is a parasitic pole caused bythe gate capacitance of M. ZI = - lCR is created by theESR of loading capacitor, and Z = -gmfC locates at vehigh equency. In ideal case, proper values of C and R arechosen so that ZI and P cancels each other. However, if thisis not the case, P may appear before UGF and the systemmay not be stable. It is especially the case in heavy loading,since in that case r decreases and the dominant pole shisto higher equency.

Figure 4. Simulatio circuit or open-loop aalysis.

To mitigate this problem, it is desed to push P to higherequency. However, since the size of the power transistor(i.e. M) is usually determined by the maximum loadingcurrent required, it is dicult to reduce the gate capacitanceC Therefore it is desed to reduce the resistance appear atthe gate of M. In other words, it is necessary to increase thegate riving force of M. In FYF as shown in Fig. 1, thiscontradicts with the regulation requirement, which is that thelower resistance at VG leads to inaccracy of biasing current.The variation in biasing leads to the inaccuracy of Va.

I. LSFYF & CAFYF

The cascoded ipped voltage follower (CAFYF) [5], andlevel shied ipped voltage follower (LSFYF) [5], [6] hasbeen repored as improved versions of FYF. The applicationof CAFYF in LO has been repored in [7]. The circuit ofCAFYF is shown in Fig. 5. An NMSFET, M, is inserte,shiing VA to VB - VGS(M, where VGS(M) is dened bybiasing crrent I and the size of M. VB is a biasing voltagethat can be set as desired. This conguration alleviates thesituation in light load, and M will not be pushed into trioderegion.

Another advantage of CAFYF is that M acts as acommon-gate amplier, providing extra gains in thefeedback loop. This rther reduces the output impedance,or, equivalently, enhances the load regulation. However, as


3/4

analyzed before, the resistance appearing at the node VG isstill large, therefore the parasitic pole caused by Cp stillexists in a relatively low equency.

d

Fiure 6. LSFVFbased LO.

he circuit of SFVF is shown in Fig. 6. Comparing tothe CAFVF counterpar, the transistor M is replaced by a

PMSFE, M. Now, VA = VG - VSG(M}> where VSG(M) isdeteined by the biasng current and the size of M. hisalso alleviates the situation at low loading, and M willalways stay in saturation region.

Comparing to the CAFVF D, here, M works as asimple sorce follower with unity gain. herefore, it does notboost the loop gain. n the other hand, a sorce follower haslower output impedance to rive the gate of M, therefore,pushing the parasitic pole at VG to a higher equency. hisincreases the bandwidth and helps to stabilize the system.

IV. BFVF FOR D PLICATION

It is desed to combine the merits of both CAFVF andSFVF structures, i.e. a) alleviates the minimum loadingrequement of FVF, b) provide large driving force at thegate of M and c) boost the loop gain to improve loadregulation. ne possible topology is the proposed bueredFVF (BFVF) as shown in Fig. 7. It could be understood as aCAFVF structure (consists of M, M and M) with a simplesource follower insered (M) to reduce the impedance at VG,or, as an SFVF structure (consists of M, M and M) witha common-gate amplier (M) insered to boost the loopgain. herefore, it is expected that it has the merits of bothCAFVF and SFVF structres.

In the BFVF O structure, VA, the rain voltage of M,is determined by VB and VGS(M), which are independent ofloading current. herefore it does not have minimum loadingconstraint. However, the bias voltage VB cannot be set toolow, otherwise the transistor which acts as IN might entertriode region. n the other hand, the upper limit of VB is VH+ V7(M)' therwise, M will enter triode region. Anadditional remark is that the control voltage VCTR could be

generated using the same circuit as proposed in [2].

Figure 7. Proposed BFYF-based LO.

Figure 8. Signal ow graph oBFVF LO.

Similarly, as in the FVF analysis, the signal ow graphof the BFVF O is shown in Fig. 8, where gb and g arethe transconductance of M and M, r is the outputresistance of M, and rn r and r2 are the output resistanceof IN, I and I2 Comparing to Fig. 4, it is observed that theloop gain is boosted by , and a negative feedback loop

is introduced to reduce the impedance associated with Cpoas

Acodin t Fig. 8, te on lo ain can be cmutd

= . (-sfzJ-sfz (-sf pJ-sf p )(7)

whereo =r Z = -fRtC' Z2 = -r/Cp,P = -fCr adp2 = -Cp. is observed that P and Zare the same as that in FVF O. P2 is shied to a higherequency because Cp now is driven by g" which is theconductance appearing at the source of M. A byproduct is


4/4

that Z is shied to an even higher equency. he dc gain isalso boosted.

V. IMULATION ESULTS

he ccuits of FVF, CAFVF, LSFVF and BFVF LOsare constructed, using austriamicrosystems AMS) 350-process. he size of the power transistor M is 5000 05

m. In the simulation, DD= 2.5 V, C = 5 F, R = 50 mQ.he output voltage is set to 1.8 V. he total quiescent biasingcurent is around 2040 A.

Using similar conguration as that in Fig. 4, the openloop gains of four circuits re simulated, and the equencyresponse is shown in Fig. 9

For the FVF LO, the dc gain is 67 dB, and thebandwidth is around 200 kHz. For CAFVF LO, the OCgain is 72 dB, and the bandwidth similar to that of FVFLO. For LSFVF LO, it has similar OC gain as that ofFVF, but the bandwidth is around 1.8 MHz. Notice that theposition of P in the LSFVF LO is about two decadeshigher than that of the FVF LO. BFVF LO has both

boosted gain and larger bandwidth. he phase margin ofBFVF and LSFVF LOs is also larger than that of theCAFVF and FVF counterparts, since P is at higherequency.

8:; - -

_ 6

2 - FVF __ CAFV

2 LSFV-4 BFVF

,

O

-50 .

FVF

_.- CAFVF; LSFV

2010 foleded voltage follower.pdf

Documents