2010 blakiewiz output-capacitorless low-dropout regulator.pdf

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Published in IET Circuits, Devices & SystemsReceived on 9th December 2010Revised on 18th March 2011doi: 10.1049/iet-cds.2010.0431

ISSN 1751-858X

Output-capacitorless low-dropout regulatorusing a cascoded flipped voltage followerG. BlakiewiczDepartment of Microelectronic Systems, Gdansk University of Technology, Narutowicza 11/12, PL 80-233 Gdansk, PolandE-mail: [email protected]

Abstract: An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator arepresented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the outputcurrent change from low to high value and poor stability for large capacitive load. The most important parameters of themodified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improvedone are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS0.35 mm technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93%for output current 100 mA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mVfor output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 ms, and load capacitance 0–100 pF.

1 Introduction

In modern systems on a chip (SoC) there is a strong need foron-chip integration of voltage regulators providing necessarysupply voltages and enabling power management ofcomponent subsystems. The high-efficiency, fast-responseand low-dropout (LDO) voltage regulators become criticalfor successive implementation of effective SoC supplying.

There are two main approaches to integrated LDO voltageregulators design. The regulators with a relatively big outputcapacitor, typically located off-chip as a discrete component,are designed to have the dominant pole located at theregulator output [1–9]. Big output capacitance helps toachieve the dominant pole at low frequencies, wellseparated from the remaining non-dominant poles, whichguaranties stable operation. Such a configuration is veryfavourable from the point of view of electrical parameters,because big output capacitance reduces overshoots andundershoots caused by rapid changes of output current, andit additionally improves the power supply rejection (PSR) athigh frequencies. On the other hand, the need forconnecting the external capacitor complicates SoC layoutand restricts the number, and possible locations of theregulators on a chip, because each of them needs adedicated terminal for the external capacitor connection.

The other solution of LDO regulators is based on verysmall on-chip capacitance connected to its output, mainlyresulting from parasitic capacitance of an on-chip supplynetwork [10–17]. The small output capacitance makes thedesign of such on-chip regulators extremely difficult,because in this case the dominant pole has to be realisedinside a negative regulation loop. Such a location of thedominant pole degrades most of electrical parameters.The dominant pole located inside the regulation loop

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significantly reduces its speed. Because there is smallcapacitance at the regulator output, its output impedancebecomes large at higher frequencies resulting in twoadditional serious disadvantages, poor PSR at highfrequencies and lack of charge reservoir at the output. Thesmall output capacitance is typically insufficient to provideelectrical charge, which could compensate for outputvoltage spikes caused by rapid change of load current.

Several solutions were proposed to overcome the outlineddifficulties. The single-transistor-control configuration [10,11] using flipped voltage follower (FVF) [18], shown inFig. 1, is utilised to form a regulator able to operate stablewith no output capacitance. The circuit presented in [11],working also with any value of output capacitance, revealsgood characteristics especially when the output capacitorhas capacitance of 1–10 mF and equivalent series resistance(ESR) greater than zero. The improved version of thatconfiguration with reduced response time is achieved byapplying voltage-spike detection mechanisms [12–14]. Theregulators detect output voltage spikes and dynamicallyincrease biasing currents, which increase their speed. Allthe mentioned regulators are based on similar idea of usingthe output stage with very low output resistance achieved asa result of a local negative feedback. As discussed in [11],such a stage has two main poles in the frequency responseof the negative regulation loop

p1 = gds2 + gbias

Cgs1 + (1 + gm1/(gds1 + gm2))Cgd1

(1a)

p2 = gm2 + gds1

Cout

(1b)

where gm1 and gm2 are the transconductances, and gds1, gds2

IET Circuits Devices Syst., 2011, Vol. 5, Iss. 5, pp. 418–423doi: 10.1049/iet-cds.2010.0431

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are the drain–source conductance of M1 and M2, whereasgbias is the internal conductance of the current source. Cgs1

and Cgd1 are the gate–source and gate–drain capacitancesof M1. Cout is the total output capacitance.

The equations (1a) and (1b) are valid under the assumptionthat the load capacitance Cout has zero ESR and is relativelysmall, which directly corresponds to the case where theregulator is loaded with parasitic capacitance of a small on-chip supply network. The second pole (1b) is typicallylocated at frequencies greater than the unity gain frequency[11], which means that the regulator has almost a single-pole frequency characteristic in this frequency range, andconsequently the phase margin close to 908.

The output stage composed of FVF is well suited to fullyon-chip integrated regulators, because its low outputresistance limits the lowest magnitude of the non-dominantpole when Cout increases. This assures large separation ofthe dominant and non-dominant poles and guarantees stableoperation. The regulators using the classical FVF presentedin [10–14] have also limitations. The stable operation of atypical on-chip FVF is only possible for output capacitanceCout limited to 20–30 pF when RESR ¼ 0 or for largercapacitances but with RESR . 0 [11]. For greater loads,caused, for example, by large on-chip supply networks,FVF has to be stabilised by connecting additionalcapacitance to node X, shown in Fig. 1 [18]. Unfortunately,the additional capacitance degrades speed of the regulatorand increases output voltage spikes. Another problemresults from limited current which can be applied todischarge the parasitic capacitance CX associated with node X.The maximum discharge current is restricted by the

Fig. 1 Classical FVF


current source to Ibias, and in most cases cannot effectivelycompensate a rapid change from low to high value of theoutput current. A better situation is with FVF reaction tooutput current change from high to low value. In this case, thecharging current is generated by transistor M2, which is ableto source much greater current. Typically for this circuit, theoutput voltage undershoot is greater than overshoot, and mayreach over 150 mV in magnitude for rapid current changefrom 0 to 50 mA [11].

In this paper LDO regulator with an improved FVF ispresented. The proposed circuit reveals better frequency andtime responses with only a little increase of its complexity.The rest of the paper is divided to Section 2 that discussesthe improved FVF configuration. Section 3 presents designtrade-offs and discusses the circuit optimisation. Themeasurement results of a prototype regulator using theimproved FVF are provided in Section 4. The final sectionincludes conclusions.

2 Improved FVF

The schematic of the proposed improved FVF is depicted inFig. 2. The capacitors CX and Cout represent the parasiticcapacitances associated with X and the output nodes,respectively. The additional transistor M3 plays 2-fold role.Firstly, it increases the equivalent resistance seen at node Xat lower frequencies by cascoding the current source.Secondly, M3 increases voltage gain of the common gatestage, formed of M2, at higher frequencies. At higherfrequencies both transistors M2 and M3 work together withthe equivalent transconductance increased to gmS ¼ gm2 + gm3,where gm2, gm3 are their transconductances. As a result, thepresented FVF has the dominant pole, associated with node X,shifted to lower frequencies without increasing the nodeparasitic capacitance. Because CX is almost unchanged, and thedominant pole is more separated from the non-dominant one,the phase margin of the regulation loop is improved withoutany penalty in speed of its time response. However, the mostimportant advantage of this configuration is the increasedcurrent discharging CX. In this circuit, transistor M2 generatescharging Ichr, whereas M3 discharging Idis current. Bothtransistors form a class-AB amplifier with the quiescent biasingcurrent defined by the current source Ibias. During transients ofthe output current, the drain current of one of M2 or M3increases without limitation to Ibias, as was the case for theclassical FVF shown in Fig. 1. Such a operation enables fastreaction to output current changes, under relatively small

Fig. 2 Improved FVF

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biasing current Ibias. This permits a low-power operation andhigh-efficiency of supplying.

The magnitude of discharging Idis and charging Ichar

currents flowing through the capacitance CX can beapproximated by

Idis � Cf

DV−out

t1

+ Ibias ≃ Cf

DV−out

t1

for DVGS3 ≪DV−out (2a)

Ichr � gm2DV+out − Ibias ≃ gm2DV+

out for VGS2 ≪DV+out (2b)

where t1 is the fall time of the output voltage, as shown inFig. 2. The biasing current Ibias is omitted in (2a) and (2b)because of its relatively small value. The above equationswere derived assuming that each transistor is working in thesaturation region while sourcing or sinking its drain current.For properly designed circuit, the output spikes DVout

+(2) arestrongly limited in magnitude, which entitles using thesmall-signal approach ( gm2 in 2b). The approximation (2a)is valid when change of the gate–source voltage DVGS3 issmaller than the magnitude of the output spike DV−

out,resulting in the following condition:

DVGS3 ≃1

gm3

idis ≃1

gm3

Cf

DV−out

t1

.DV−out ⇒ gm3 .

Cf

t1

(3)

The output voltage overshoot DV+out and undershoot DV−

outwill be of similar magnitude if Idis ¼ Ichr, which leads to

gm2 ≃ Ichr

DV+out

= Idis

DV+out

≃ 1

DV+out

Cf DV−out

t1

�DV+

out≃DV−out Cf

t1

(4)

The minimal biasing current Ibias is limited by the minimalrequired transconductance of transistors M2 and M3,expressed by (3) and (4). For low-power application thebiasing current Ibias can be reduced, to some extend, bymaking the transistors wide. Unfortunately, wide transistorsincrease the parasitic capacitance CX and consequentlyreduce the speed of FVF. The selection of Ibias, width ofM2 and M3 requires finding a satisfactory trade-off betweenthe speed and power consumption.

A simple approximation of the output spikes can beachieved using the circuit shown in Fig. 3, which representsa simplified model of the output node of FVF from Fig. 2during an initial time interval denoted by t1. As it will bepointed out later, this small-signal model is only valid forrelatively small Cout for which the gate–source voltage ofM1 does not change much, and gm1 can be regarded as aconstant. During the interval t1, the change of the gate–source voltage DVgs1 follows the change of output voltageDVout. In this interval the gain of the stage composed of M2and M3 is hardly limited to value close to unity, becausethe parasitic capacitance CX is reloaded by the limited

Fig. 3 Simplified model of FVF output node during an initialperiod t1 of output transient

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discharging current defined by (2a), which results in

DVgs1 = DVX = t1

CX

Idis≃t1

CX

Cf

DV−out

t1

=Cf

CX

V−out (5)

By making Cf . CX, one can achieve the voltage gain greaterthan unity during the considered transient, and consequentlymore effective reduction of FVF output voltage undershoot.Similar conclusion can also be formulated for the processof charging capacitance CX. Using the model from Fig. 3one can easily see, that the change of output current DIout

is compensated by the controlled current source andcapacitance Cout

DIout =Cf

CX

gm1DV−out + Cout

DV−out

t1

(6)

The output voltage changes rapidly until the moment whenthe drain current of M1 becomes equal to the currentflowing through capacitance Cout. Once this happens, therate of DVout change starts to decrease rapidly, because thecurrent generated by M1 due to its high gain increasesmuch faster than current flowing through Cout. Thismoment can be approximately regarded as the moment ofthe output voltage undershoot occurrence. The time intervalt1 after which both currents become equal can be estimatedfrom [compare (6)]

Cf

CX

gm1DV−out = Cout

DV−out

t1

(7)

The simplified approximation of the output voltageundershoot DV−

out is derived by substitution of t1, achievedfrom (7), into

t1

DtDIout =

Cf

CX

gm1DV−out + Cout

DV−out

t1

(8)

where the left side of the equation represents the fraction ofthe output current change DIout after the period t1. Finally,the undershoot is

DV−out ≃

1

2

CX

Cf

( )2Cout

g2m1

DIout

Dt(9)

where gm1 is approximately equal to M1 transconductancecalculated for Id1 ¼ Ibias + (Iout)min. The approximation (9)is only valid for Cout ≤ Cf + CX, where DV−

out is relativelysmall and gm1 can be regarded as a constant. The outputvoltage overshoot can also be estimated from (9), becausethe sequence of events is similar, but they happen in thereverse order. During the initial period (denoted by t2 inFig. 2) of output current change from high to low value, thedrain current of M1 is greater than the current through Cout

owing to its high gain. When both currents become equal,the rate of DV+

out change starts to decrease rapidly, and theovershoot occurs. The approximation (9) can be directlyused for DV+

out calculation under the assumption thatIdis ¼ Ichr, which requires the condition (4) to be fulfilled.

The expression (9) shows that increasing the outputcapacitance Cout does not reduce the output spikes DV+(−)

out ,whereas the most important factor for its reduction is M1transconductance. For typical circuit parameters, the


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Table 1 Comparison of important parameters of the classical and improved FVFs

Parameter Classical FVF

from Fig. 1

Improved FVF

from Fig. 2

Approximated

improvement factor

the dominant pole p1 gds2 + gbias

Cgs1 + (1 + gm1/(gds1 + gm2))Cgd1

gds2 + gbiasgds3/gm3

Cgs1 + (1 + gm1/(gds1 + gm2))Cgd1

1 + gbias

gds2

� 2

the maximal charging

current Ichr

gm2DV+out gm2DV+

outa 1

the maximal discharging

current Idis

Ibias

C2f gm1

CoutCX

DV−out

a C2f gm1

CoutCX

DV−out

Ibias

= 5.5b

PSR at low frequenciesc gm1

gds1

1 + gm2gm1

(gds2 + gbias)gds1

[ ]−1 gm1

gds1

1 + gm1gm2

(gds2 + (gbiasgds3/gm3))gds1

[ ]−1

1 + gbias

gds2

� 2

PSR at medium frequenciesd gm1

gds1

1 + gm2gm1

(gds2 + gbias)gds1

[ ]−1 gm1

gds1

1 + gm1(gm2 + gm3)

(gds2 + gds3)gds1

[ ]−1

1 + gm3

gm2

� 2

aachieved assuming small signal approximation, valid for DVout+(2) ≪ VT

bcalculated from (2a) and (7) assuming Cx ¼ 8 pF, Cf ¼ 10 pF, Cout ¼ 20 pF, gm1 ¼ 3.5 mS, Ibias ¼ 20 mA, DVout2 ¼ 52 mV

cachieved from (10) for AFB ¼ gm2/(gds2 + gds3gbias/gm3)dachieved from (10) for AFB ¼ (gm2 + gm3/(gds2 + gds3)

magnitude of the spikes calculated from (9), isDV+(−)

out ≃ 52 mV assuming: DIout ¼ 100 mA, Cx ¼ 8 pF,Cf ¼ 10 pF, Cout ¼ 20 pF, gm1 ¼ 3.5 mS, Dt ¼ 1 ms.

The PSR of FVF, shown in Fig. 2, at low frequenciesstrongly depends on the voltage gain AFB of the feedbackamplifier composed of M2. At low frequencies, M3 forms acascode stage and does not provide voltage gain. The noiseat FVF output is reduced by [11]

DVout

DVin

= (gm1/gds1)

1 + (AFBgm1/gds1)(10)

which means that the improved FVF provides a better noiseattenuation than the classical one (Fig. 1), because of itsgreater gain AFB achieved owing to the increased resistanceof node X. At medium-frequency range, the improved FVFalso reveals better performance, because at this range bothtransistors M2 and M3 form a push–pull amplifier withincreased gain.

3 Design trade-offs and circuit optimisation

The most important parameters of the classical and improvedFVFs are compared in Table 1. The last column presentsapproximated expressions for an improvement factorshowing how much improvement can be gained for circuitin Fig. 2. All the presented parameters are derived based onthe small-signal approach, which is only valid for smalloutput spikes DV+(−)

out and small Cout. For larger values, theequations may not be precise enough.

As (9) shows, the minimisation of the output spikesrequires maximisation of M1 transconductance gm1 andminimisation of CX. The best results for the spikesoptimisation can be achieved by adjusting Ibias for minimalpossible width (W1) and length (L1) of M1, designed tosatisfy the assumed maximal output current (Iout)max. Theincreasing of the transistor width results in enlarging CX,because: CX / Cgs1 / W1, and gm1 /

��W1/L1

√, which in

turn diminishes the primary goal. The output voltageundershoot can also be improved by enlarging Cf, but thisrequires that (3) and (4) are satisfied, leading to increasingof Ibias or increasing of M2 and M3 aspect ratios W2/L2 andW3/L3. From the power efficiency point of view, only the


aspect rations enlargement is advantageous, which meansthat length of both transistors L1 and L2 has to beminimised. In the other case, the parasitic capacitances ofM2 and M3 increase CX, and as a result reduce speed of thenegative loop.

The maximal output capacitance Cout for stable operationof the improved FVF is limited by the allowable location ofthe non-dominant pole. The pole can be approximated by

p2 =gm2 + gm3 + ggd1

Cout

(11)

The phase characteristic of the local negative feedback isdetermined by two poles [the dominant (Table 1) and thenon-dominant (11)] and an additional pole-zero pairintroduced by Cf in series with the resistance seen form thesource of M3. The simplified approximation of the upperlimit of Cout for a non-zero phase margin can be evaluatedassuming that |p2| ≥ GB, where GB is the unity gainbandwidth of the negative loop, which leads to the condition

Cout

CX

≤ gm2 + gm3 + gds1

gm1

(12)

In practical circuit realisations, the approximation (12) givesa much underestimated limit, because it omits the influenceof the pole-zero pair, typically located close to GB. The

Fig. 4 Implemented LDO regulator

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simulations of the phase characteristic and the measurementsresults of a prototype circuit show that the limit (12) can bepractically enlarged 10–20 times.

4 LDO regulator with the improved FVF

The test LDO regulator, shown in Fig. 4, has been implementedin AMS 0.35 mm CMOS technology. The circuit was designedto provide 1.2 V output voltage at 50 mA output current for inputvoltage greater than 1.4 V. The circuit consists of the discussedFVF (M1 – M4 and Cf) optimised for low-power operation.The local negative feedback (M2, M3 and Cf) enclosing thelast stage guaranties high attenuation of output voltage spikesand stable operation for big output capacitances. The veryslow additional error amplifier composed of M5–M10stabilises DC component of output voltage, and additionallyimproves PSR at very low frequencies (,50 kHz). The mainparameters of the circuit are listed in Table 2.

Table 2 Parameters of the implemented LDO regulator

M1: 5000 mm/0.35 mm M2: 300 mm/

0.35 mm

M3: 100 mm/

0.35 mm

M4: 80 mm/0.8 mm M5, M6: 20 mm/

1 mm

M7, M8: 5 mm/

1 mm

M9: 7 mm/0.8 mm M10: 1.8 mm/

0.8 mm

R1 ¼ 66 kV

R2 ¼ 134 kV R3 ¼ 120 kV Cf ¼ 20 pF

Cc ¼ 3 pF Cb ¼ 3 pF Ibias ¼ 1 mA, Vref ¼ 0.8 V

Fig. 5 Time responses of the implemented regulator for output current changes

a and b Cout ¼ 15 pFc and d Cout ¼ 100 pF

Fig. 6 Time responses of the implemented regulator for input voltage changes

a Cout ¼ 15 pF, Iout ¼ 1 mAb Cout ¼ 100 pF, Iout ¼ 1 mAc Cout ¼ 15 pF, Iout ¼ 50 mAd Cout ¼ 100 pF, Iout ¼ 50 mA

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& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-cds.2010.0431

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Table 3 Performance comparison of selected output-capacitorless LDO regulators

Parameter [11] [12] [14] This work

technology CMOS 0.35 mm CMOS 0.09 mm CMOS 0.35 mm CMOS 0.35 mm

(Iout)max 50 mA 100 mA 100 mA 50 mA

Vout 1.0 V 0.5–1 V 0.7–1.2 V 1.2 V

Iin for Iout ¼ 0 95 mA 8 mA 43 mA 34.6 mA

Cout any .10 pF any 0–200 pF

on-chip capacitance 0 pF 7 pF 6 pF 26 pF

cip area 0.045 mm2 0.019 mm2 0.358 mm2 0.08 mm2

output voltage spikes DV+out/DV−

out

for output current change

130 mV/160 mV for

DIout ¼ 0–50 mA

and the rise/fall

times

300 ns/300 ns

114 mV/73 mV for

DIout ¼ 3–100 mA

and the rise/fall

times

100 ns/100 ns

70 mV/70 mV for

DIout ¼ 1–100 mA

and the rise/fall

times

1 ms/1 ms

46 mV/75 mV for

DIout ¼ 0.1–50 mA

and the rise/fall

times

300 ns/300 ns

line regulation 18 mV/V 3.78 mV/V N/A 8.8 mV/V

load regulation 0.28 V/A 0.1 V/A N/A 0.003 V/A

PSR at low freq. and (Iout)max N/A 50 dB for freq.

,200 Hz

N/A 40 dB for freq.

,50 kHz

PSR at high freq. and (Iout)max N/A 0 for freq.

.1 MHz

N/A 6 dB for freq.

.19 MHz

The regulator time responses for the output current changeDIout/Dt ¼ 50 mA/0.3 ms are presented in Fig. 5 forCout ¼ 15 pF and 100 pF. The output voltage overshoot andundershoot are DVout

+ ¼ 44 mV and DV−out = 73 mV for

Cout ¼ 15 pF, whereas DV+out = 46 mV and DV−

out = 75 mVfor Cout ¼ 100 pF. The output voltage responses for theinput voltage change from 1.4 to 1.6 V with the rise/falltimes DVin/Dt ¼ 200 mV/0.3 ms are presented in Fig. 6 forCout ¼ 15 pF, Cout ¼ 100 pF and two output current valuesIout ¼ 1 mA and Iout ¼ 50 mA. The biggest output voltagespikes DV+

out = 22 mV and DV−out = 27 mV were observed

for Iout ¼ 50 mA. The spikes magnitude did not practicallydepend on the load capacitance as long as Cout , 200 pF.Table 3 compares important parameters of selected output-capacitorless LDO regulators reported in the literature withthe regulator presented in this paper.

5 Conclusions

A useful modification of FVF having good time and frequencyresponses is presented in this paper. The proposed FVFimproves most weaknesses of the classical one, namely itspoor time response to the output current change from low tohigh value and poor stability for large capacitive load. Thecomplexity of the improved FVF is only little increased,because it requires additional single transistor and capacitor.The designed and implemented LDO regulator using theimproved FVF reveals very good characteristics.

6 Acknowledgments

This work was supported by the Polish Ministry of Scienceand Higher Education, in part from grant N N515 423034,and O R00 0046 09.

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2010 blakiewiz output-capacitorless low-dropout regulator.pdf

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