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2009 International SoC

Design Conference

(ISOCC 2009)

Busan, Korea

22 - 24 November 2009

4 IEEE IEEE Catalog Number: CFP0969E-PRT

ISBN: 978-1-4244-5034-3

TIB/UB Hannover

133 817 571

Foreword i

Message From Technical Program Committee Chair ii

Invitation to ISOCC 2010 iii

Committee iv

Time Table xi

Keynote Speeches xiii

Keynote Speech 1

Toward Development of Solution-Driven SoC

Youm Huh (Silicon Mitus, Korea) xiii

Keynote Speech 2

Mobile Phones and Multicores: Programming Nightmare or Architectural Renaissance

Arvind (MIT, USA) xv

Plenary Speeches xvi

Plenary Speech 1

Energizing and Powering MicrosystemsGabriel A. Rincon-Mora (Georgia Institute of Technology, USA) xvi

Plenary Speech 2

Multitechnology System on System (SoS) Domain: The Reality of 3D HyperintegrationVolumetric ThresholdingKarnran Eshraghian (Innovation Laboratories, Australia and Chungbuk National University,Korea) xviii

Invited Speeches 1

Invited Speech 1

New Frontiers in Nano-scale highly Nonlinear Photonic Circuits for System on System(SoS) IntegrationShahraam Afshar V. (Institute for Photonics and Advanced Sensing, Australia) 1

Invited Speech 2

SOC/SIP for Energy ManagementBernard Courtois (CMP, France) 5

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Low-voltage Low-power RF CMOS Integrated Circuits and De-embedding

Techniques

13:30 - 15:00 Monday, November 23, 2009 . Room 201

Special Session

Organizer: Kiat Seng Yeo, Nanyang Technological University, Singapore

Chair: Kiat Seng Yeo, Nanyang Technological University, Singapore

Overview

With the rapid evolution of nanometer radio frequency (RF) CMOS technologies, it is no longer

impossible to have exceptionally compact, high-performance and low-cost RF integrated circuits and

systems. This special session focuses on a new architecture and some innovative circuit and de-embedding

techniques to realize low-voltage low-power RF CMOS transceivers for ultra-wideband (UWB), IEEE

802.16 and IEEE 802.15.3c applications. It consists of six contributing papers. Paper [Sl.l] presents a

novel 24/36-GHz double conversion heterodyne architecture for IEEE 802.15.3c standard. Paper [S1.2]

proposes a technique to simultaneously cancel the thermal noise in UWB low-noise amplifiers while paper

[SI.3] describes a direct conversion UWB receiver with a pulse detector. Its low-noise amplifier has a

variable gain optimized for low-power consumption. A fully-integrated CMOS power amplifier for 3.5GHz

mobile WiMAX (IEEE 802.16 standard) is demonstrated in paper [S1.4]. Paper [SI.5] introduces a

low-power all-digital pulse generator and modulator for FCC UWB low frequency band (3.1-4.5GHz)

spectral mask specifications. Finally, Paper [SI.6] proposes a new de-embedding technique based on

general fixture model to accurate de-embed test fixture parasitic for characterization ofRF CMOS at very

high frequency.

[Si.i] A New 24/36-GHz Transceiver Architecture for 60-GHz Applications

Bharatha Kumar Thangarasu, Jinna Yan (Nanyang Technological University, Singapore)

Kaixue Ma (ST Electronics, Singapore)

Qiong Zou (Nanyang Technological University, Singapore)Jianguo Ma (University of Electronic Science and Technology ofChina, China)Kiat Seng Yeo (Nanyang Technological University, Singapore) 9

[Si.2] Reciprocal Noise Cancelling Low Power UWB LNA

Thu Nga Tran Thi, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo

(Nanyang Technological University, Singapore) 13

[S1.3] A Low Power UWB Direct Conversion Receiver with Pulse Detectors

Caixia Chen, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon


XX


[S1.4] A Low-Voltage Fully-Integrated CMOS Power Amplifier for Mobile WiMAX

Subscriber Station

Pan Renjing, Yeo Kiat Seng, Do Manh Anh, Boon Chirn Chye, Gu Jiangmin


[S1.5] A CMOS Energy Efficient UWB Transmitter Module

Tao Yuan (Institute of Microelectronics, A*STAR, Singapore)

Yuanjin Zheng, Kiat Seng Yeo, Chirn Chye Boon, Manh Anh Do (Nanyang Technological

University, Singapore) '•25

[S1.6] A Novel De-embedding Technique for On-Wafer Characterization of RF CMOS

Xi Sung Loo (Nanyang Technological University, Chartered Semiconductor Manufacturing,

Singapore)Kiat Seng Yeo (Nanyang Technological University, Singapore)

Kok Wai Johnny' Chew (Nanyang Technological University, Chartered Semiconductor

Manufacturing, Singapore)Lye Hock Kelvin Chan (Nanyang Technological University, Singapore)Shih Ni Ong (Nanyang Technological University, Chartered Semiconductor Manufacturing,

Singapore)Manh Anh Do, Chirn Chye Boon (Nanyang Technological University, Singapore) 29

Design Automation Techniques for SoC Design

13:30 - 15:00 Monday, November 23, 2009 Room 202

Special session

Organizer: Kyu-Myung Choi, Samsung Electronics, Korea

Chair: Byeong Mill, Samsung Electronics, Korea

Overview

This special session shows Samsung's approaches to produce a competitive SoC design with 45nm

process or below, The first paper presents an effective way of fixing lithography hotspots. In the design

technologies with 45nm process or below, there is no practical solution to detect the lithography hotspots

and remove them in full chip level within a reasonable range of design time and accuracy. This solution

can effectively decrease systematic defects with the accuracy of timing closure within a reasonable design

time. The second paper shows how to enhance design productivity in RTL design activities. It shows an

idea of implementing automatic RTL generator with a user defined specifications. The solution can help

RTL designers who are suffering from frequent changes of design specification. The third paper shows a

fully automated.clock jitter analysis which can handle clock network with a clock divider and state

dependency, Thereby, it can handle odd-numbered divider network as well as worst case clock jitter

analysis. The last paper shows the body bias and gate-length bias techniques to improve parametric yield.

As the variation of process increases, these techniques become important more and more for mass

production.

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[S2.1] Fixing Lithography Hotspots on Routing without Timing DiscrepancyJoo Hyun Park, Seung Weon Paek, Naya Ha, Dae Hyun Jang, Byung Mu Kim, Hyo Sig Won, Kyu

Myung Choi (Samsung Electronics, Korea) 33

[S2.2] Design Automation of Pixel Control Block for Productivity Enhancement

Sik Kim, Jong-Seok Seo, Jesuk Lee, Kwang-Hyun Cho, Tae-Chan Kim, Byeong Min, Kyu-MyungChoi (Samsung Electronics, Korea) 37

[S2.3] Automatic Clock Jitter Analysis Considering Clock Divider

Woojin Jin, Moon-su Kim, Chan-min Jo, Hyosig Won, Kyu-Myung Choi

(Samsung Electronics, Korea) 41

[S2.4] Design Techniques to Minimize the Yield Loss for General Purpose ASIC/SoC

Devices

Jung Yun Choi, Bong Hyun Lee, Kyung-Tae Do, Hyung-Ock Kim, Hyo-Sig Won, Kyu-MyungChoi (Samsung Electronics, Korea) 45

[S2.5] [Invited] A Power-Constrained MPU Roadmap for the International Technology

Roadmap for Semiconductors (ITRS)

Kwangok Jeong, Andrew B. Kahng (University of California San Diego, USA) 49

[S2.6] [Invited] Architectural-Level Prediction of Interconnect Wirelength and Fanout

Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi

(University of California San Diego, USA) 53

H.264 Video Compression Architecture and Design


Special Session

Organizer: Satoshi Goto, Waseda University, Japan and Jongwha Chong, Hanyang University, Korea

Chair: Satoshi Goto, Waseda University, Japan

Co-Chair: Jongwha Chong, Hanyang University, Korea

Overview

H.264 Video coding is now commonly used in the broadcasting or video camera product in the real life.

But, there still need new technologies to realize the low complexity, low power or less hardware. This

session is focused on these subjects to have better performance of H.264 video coding.

[S3.1] High Profile Intra Prediction Architecture for H.264

Xun He, Dajiang Zhou, Jinjia Zhou, Satoshi Goto (Waseda University, Japan) 57

[S3.3] A High Speed Deblocking Filter Architecture for H.264/AVC

Jinjia Zhou, Dajiang Zhou, Xun He, Satoshi Goto (Waseda University, Japan) *•••• 63

[S3.4] A Memory Efficient Architecture of Deblocking Filter in H.264/AVC using Hybrid

Processing Order

Kyeong-Yuk Min, Jong-Wha Chong (Hanyang University, Korea) 67

[S3.5] A 360Mbin/s CABAC Decoder for H.264/AVC Level 5.1 Applications

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Yu Hong, Peilin Liu, Hang Zhang, Zongyuan You (Shanghai Jiao Tong University, China)

Dajiang Zhou, Satoshi Goto (Waseda University, Japan)

Bio & Medical Devices


Chair: Shiho Kim, Chungbuk National University, Korea

[S4.1] [Invited, 30min] Error Tolerant DNA Self-Assembly by Link-Fracturing

Young Bok Kim, Yong-Bin Kim, F. Lombardi (Northeastern University, USA) 75

[S4.2] Design of Highly Programmable Bio-Impedance Measurement IC in 0.18um

CMOS

Min-Chang Cho (KAIST, Korea)Young-Gyu Yoon (KAIST Institute, Korea)

SeongHwan Cho (KAIST, Korea) 79

[S4.3] A High Performance Current-Balancing Instrumentation Amplifier for ECG

Monitoring SystemsChia-Hao Hsu, Chi-Chun Huang, Kian Siong Lim, Wei-Chih Hsiao, Chua-Chin Wang

(National Sun Yat-Sen University, Taiwan) 83

RF Circuits


Chair: Jinwook Burm, Sogang University, Korea

[S5.1] [Invited] Reconfigurable RF CMOS Circuit Design for Cognitive Radios

Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) 96

[S5.2] [Invited] A Low-Cost, Multi-Standard AZ Fractional-N Synthesizer Design for

WiMAX/WLAN Applications

Yuanfeng Sun, Jian Qiao, Jun Li, Rui He, Chengwen Liu, Woogeun Rhee (Tsinghua University,

China)

Sung Hun Woo (Future Communications IC, Korea)Zhihua Wang (Tsinghua University, China) 100

[S5.3] Design of a 3.5-GHz OOK CMOS Transmitter with Triangular Pulse Shaping

Hyun Kim, Jongsik Kim (Kwangwoon University, Korea)

Jinsup Kim, Hajoong Chung (KETI, Korea)

Hyunchol Shin (Kwangwoon University, Korea) 104

[S5.4] A Wideband CMOS LNA with Varactor Tuned Input Matching for WLAN/WiMAX

ApplicationsSeongku Lee, Hyunchol Shin (Kwangwoon University, Korea) 108

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[S5.5] High Dynamic Range Power Regulator Design for UHF band Near-field Passive

RFID Tag ChipsQuoc-Tai Duong, Duong Huynh Thai Vo, Quoc-Hung Huynh, Sang-Hoon Hong, Jong-Wook Lee

(Kyung Hee University, Korea)

Bo-Hyun Lee, Juno Kim (Ucomm Technology, Korea) 112

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Testing and Verification

16:15-17:45 Monday, November 23, 2009 Room 202

Chair: Jae-Kyung Wee, Soongsil University, Korea

[S6.1] Parallel Test Method for NoC-Based SoCs

Ansari Muhammad Adil (Hanyang University, Korea)

Song Jeahoon (TranSono, Korea)Kim Minchul, Park sungju (Hanyang University, Korea) 116

[S6.2] A BIST Architecture for Multiple DACs in an LTPS TFT-LCD Source Driver IC

Hyeonuk Son, Jaewon Jang, Youbean Kim, Kicheol Kim, Incheol Kim, Sungho Kang

(Yonsei University, Korea) 120

[S6.3] On-Chip Transaction Level Debug Support for System-on-ChipsAmir Masoud Gharehbaghi, Masahiro Fujita (University of Tokyo, Japan) 124

[S6.4] DFT for Achieving Hybrid Transiton Delay Fault Test with Reduced Pin Count

TestingChangwon Son, Seongyong Ahn, Sungho Kang (Yonsei University, Korea) 128

[S6.5] Case Studies with Process Analysis Toolkit (PAT)K.L. Man (Xi'an Jiaotong-Liverpool University, China)

T. Krilavicius (Vytautas Magnus University, Lithuania)H.L. Leung (Solari, Hong Kong) 133

[S6.6] A Methodology for Timely Verification of a Complex SoC

Peretz Landau, Guy Regev (Percello, Israel) 137

Design Techniques for Multi-core and Embedded Systems


Special Session

Organizer: Hyunchul Shin, Hanyang University, Korea

Chair: Hyunchul Shin, Hanyang University, Korea

Overview

This special session focuses on the design methodologies and techniques for multi-core and embedded

systems, including automatic design methodologies for MPSOC and prototyping on multi-FPGA platforms

in [S7.1], real-time power management for a multi-performance processor in [S7.2], effective memory

access optimization by memory delay modeling, memory allocation, and buffer allocation in [S7.3].

[S7.1] [30min] Automatic Design Methodologies for MPSOC and Prototyping on

Multi-FPGA Platforms

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0. Hammami, X.Li (ENSTA Paristech, France)L.Larzul, L.Burgun (Eve Team, France) 141

[S7.2] [30min] Real-Time Power Management for a Multi-Performance Processor

Tohru Ishihara (Kyushu University, Japan) 147

[S7.3] Effective Memory Access Optimization by Memory Delay Modeling, Memory

Allocation, and Buffer Allocation

Sultan Daud Khan, Hyunchul Shin (Hanyang University, Korea) 153

[S7.4] [Invited] ALU-Array based Reconfigurable Accelerator for Energy Efficient

Executions

Koji Inoue (Kyushu University, Japan)

Hamid Noori (University ofTehran, Iran)

Farhad Mehdipour, Takaaki Hanada, Kazuaki Murakami (Kyushu University, Japan) 157

[S7.5] [Invited] Software Cache Support and API Design for Embedded DSP Processor

Cheng-Yen Lin, Shao-Chung Wang, Ming-Yu Hung, Kun-Yuan Hsieh, Jenq Kuen Lee

(National Tsing-Hua University, Taiwan) 161

Advanced Design Methodologies and Characterization Strategies for Future

Integrated Systems


Special Session

Organizer: Kursun Volkan, Hong Kong University of Science and Technology, Hong Kong

Chair: Kursun Volkan, Hong Kong University of Science and Technology, Hong Kong

Overview

This special session focuses on the advanced design methodologies and characterization techniques

for near-future SoC, including skew Analysis and design methodologies to improve performance of

resonant Clocking in [S8.1], compressive acquisition CMOS Image Sensor with on-line sorting scheme in

[S8.2], practical battery charge/discharge simulator for future embedded systems in [S8.3], custom digital

cell generation flow for 65nm processes in [S8.4J, strategy to detect bug in pre-silicon phase in [S8.5], and

a novel architecture for tunable heterodyne filters in [S8.6].

[S8.1] Skew Analysis and Design Methodologies for Improved Performance of Resonant

ClockingVinayak Honkote, Baris Taskin (Drexel University, USA) 165

[S8.2] Compressive Acquisition CMOS Image Sensor Using On-line Sorting Scheme

Milin Zhang, Amine Bermak

(Hong Kong University ofScience and Technology, Hong Kong) 169

[ss.3] A Practical Battery Charge/Discharge Simulator for Future Embedded Systems

including Smart Grids

Ittetsu Taniguchi, Keita Kojima, Masahiro Fukui (Ritsumeikan University, Japan) 173

[S8.4] Custom digital cell generation flow for 65nm processes

xxv


Kim Leong Yeoh, Jin Sean Lim, Kong Leng Goh, See Mean Tee

(Intel, Malaysia) 177

[S8.5] Strategy to Detect Bug in Pre-silicon Phase

Mary Yeoh Siaw See (Intel, Malaysia) 182

[S8.6] A Novel Structure for Tunable Complex-Arithmetic Heterodyne Filters

Michael A. Soderstrand (DeVry University, USA)

Grace Yoona Cho (Tellabs Wireless Group, USA) 186

Sensors and/for SoCs

09:30 - 10:45 Tuesday, November 24, 2009 Room 201

Special Session

Organizer: Makoto Ikeda, University ofTokyo, Japan

Chair: Tetsuya Iizuka, University ofTokyo, Japan

Overview

Sensing is becoming one of the most important topics in many areas such like bio-interfaces,

monitoring the operation of SoCs. Also to achieve low-power and versatile sensor-net nodes, single chip

sensor node SoCs are essential. This special session covers this wide diversity of technical areas to

overlook the state-of-the art techniques and future perspectives.

In the first presentation "CMOS image sensor for recording of intrinsic-optical signal of the brain," S.

Shishido and his colleagues of Nara Institute of Science and Technology (NAIST) describe an image

sensor to capture and record ofbrain activities such like Intrinsic Optical Signal (IOS) and EEG and so on.

The 2nd presentation "Cascaded Time Difference Amplifier using Differential Logic Delay Cell," S.

Mandai and his colleagues of the University of Tokyo describe a time difference amplifier with the gain

error below 5.5% over +-250ps input range in 0.18um CMOS for Time-to-digital Converters (TDCs) and

sensors for precise time-domain signal capture, such like TOFs.

The 3rd presentation "On-Chip Power Noise Measurements of High-Frequency CMOS Digital

Circuits," T. Matsuno and M. Nagata of Kobe University describe an on-chip power and substrate noise

measurements ranging from 100MHz to 1.2GHz using in 90nm CMOS.

The 4lh presentation "A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided

Data-Buffer SRAM," T. Takeuchi and his colleagues of Kobe University describe an ultra-low-power

single-chip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM achieving

only 6uW power consumption in 0.18um CMOS.

The last presentation "An SoC Platform with On-Chip Web Interface for In-Field Monitoring," T.

Iizuka and his colleagues ofthe University of Tokyo describe an SoC platform which enables in-field LSI

testing and an easy access to the on-chip LSI monitoring circuits through on-chip web interface.

[S9.1] CMOS Image Sensor for Recording of Intrinsic-Optical-Signal of the Brain

Sanshiro Shishido, Yasuhiro Oguro (NAIST, Japan)Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, Jun Ohta (NAIST, JST, CREST, Japan) 190

[S9.2] Cascaded Time Difference Amplifier using Differential Logic Delay Cell

Shingo Mandai, Torn Nakura, Makoto Ikeda, Kunihiro Asada (University ofTokyo, Japan) 194

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[S9.3] On-Chip Power Noise Measurements of High-Frequency CMOS Digital Circuits

Tetsuro Matsuno, Makoto Nagata (Kobe University, Japan) 198

[S9.4] A Single-Chip Sensor Node LSI with Synchronous MAC Protocol and Divided

Data-Buffer SRAM

Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh

Tsuruda, Yasuhiro Sakai, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto

(Kobe University, Japan) 202

[S9.5] An SoC Platform with On-Chip Web Interface for In-Field MonitoringTetsuya Iizuka (VLSI Design and Education Center (VDEC), Japan)Daisuke Nakamura (University ofTokyo, Japan)Hiroaki Yoshida, Satoshi Komatsu, Masahiro Sasaki (VLSI Design and Education Center (VDEC),

Japan)Makoto Ikeda, Kunihiro Asada (VLSI Design and Education Center (VDEC), University ofTokyo,

Japan) 208

Power Gating and Low-Power SoC Design

09:30 - 11:00 Tuesday, November 24, 200? Room 202

Special Session

Organizer: Kursun Volkan, Hong Kong University of Science and Technology, Hong Kong

Chair: Kursun Volkan, Hong Kong University of Science and Technology, Hong Kong

Overview

This special session focuses on the low power management techniques of SoC through various levels

and methodologies which include power-gated circuit techniques in [SI0.1], sleep transistor forward body

bias method in [S10.2], SoC power off-noise analysis in [S10.3], SRAM Core Modeling in [S10.4],

Statistical Approach to Low Power in [S10.5], and Incremental Register Placement techniques in [S10.6].

[Sio.i] Self-Retention of Data in Power-Gated Circuits

Jun Seomun, Youngsoo Shin (KAIST, Korea) 212

[S10.2] Sleep Transistor Forward Body Bias: an Extra Knob to Lower Ground BouncingNoise in MTCMOS Circuits

Hailong Jiao, Volkan Kursun (The Hong Kong University ofScience andTechnology, Hong Kong) — 216

[Sio.3] SoC Power Off - Power Noise Analysis

Yong Lee Kee (Intel, Malaysia) 220

[Sio.4] SRAM Core.Modeling Methodology for Efficient Power Delivery AnalysisFern Nee Tan, Sze Geat Pang, Chin Leng Ng, Kam Yee Wong, Lee Kee Yong

(Intel, Malaysia) 224

[Sio.5] Statistical Approach to Low Power and High Volume Pineview Atom-based SoC

DesignSuphachai Sutanthavibul, Azydee Hamid (Intel, Malaysia) 228

[sio.6] Incremental Register Placement for Low Power CTS

Jianchao Lu, Baris Taskin (Drexel University, USA) 232

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Embedded SW & Embedded Memory


Chair: Sungjoo Yoo, POSTECH, Korea

[S11.1] Flexible Framework for Dynamic Management of Multi-Core SystemsYoungho Ann, Young-Si Hwang, Ki-Seok Chung (Hanyang University, Korea) 237

[S11.2] Software Development Tools for Streaming DSP Applications

Ching-Hsiang Chuang, Chiu-Ling Chen, Pi-Cheng Hsiao, Tay-Jyi Lin

(Industrial Technology Research Institute, Taiwan) 241

[S11.3] A Spectral-Based Partitioning Algorithm for Parallel LDPC Decoding on a

Multiprocessor Platform

Wen-Hsiang Hu, Chun-Yi Chen, Nader Bagherzadeh (University ofCalifornia Irvine, USA) —• 245

[Si 1.4] An Advanced BIRA Using Parallel Sub-analyzers for Embedded Memories

Woosik Jeong, Taewoo Han, Sungho Kang (Yonsei University, Korea) 249

[Si 1.5] Modeling Power Consumption of Applications in Wireless Communication

Devices Using OS Level Profiles

Takashi Majima (Nagoya University, Japan)Tetsuo Yokoyama (Nanzan University, Japan)

Gang Zeng (Nagoya University, Japan)Takeshi Kamiyama (NTT DOCOMO, Japan)Hiroyuki Tomiyama, Hiroaki Takada (Nagoya University, Japan) 253

Design Techniques of SoC for Telecommunication


Special session

Organizer: Jun Ma, Shanghai Jiao Tong University, China

Chair: Jun Ma, Shanghai Jiao Tong University, China

Overview

In the system-on-chip (SoC) design for telecommunication applications, it is vital to conduct joint

optimizations among RF, analog, and digital baseband. The imperfections caused by RF and analog blocks

can usually be relaxed and/or compensated by the digital circuits in the baseband. In this special session,

two papers namely [S12.2] and [S12.3] are presented to address these issues such as I/Q imbalance and

phase noise compensations in an OFDM based wireless communication environment. The VLSI

architectures are also investigated for the phase noise compensation based on decision feedback algorithm

using MMSE equalization technique. Two other papers, namely [S12.1] and [S12.4] in this special session

are presented to address the symbol timing synchronization issue and digital automatic gain control

(DAGC) function block for the ultra-wideband (UWB) wireless communications and digital mobile TV

applications, respectively. Due to the very high sampling rate requirement in the UWB system, a

symbol-rate timing recovery approach based on digital adaptive interpolation using LMS algorithm is

proposed for the purpose of power consumption reduction in paper [S12.1]. In paper [S12.4], detailed

finite-word-length (FWL) analysis are conducted on the VLSI architecture of the DAGC function block for

xxviii


the purpose of efficient FWL design, which is an essential step from the system to the digital logic design.

The proposed FWL analysis approaches are also applicable to other digital feedback systems.

[S12.1] A Novel Approach for Symbol-Rate Timing Recovery Based on Adaptive

InterpolationHuan Chen, Guanghui He, Jun Ma (Shanghai Jiao Tong University, China) 257

[S12.2] A Novel Method for Estimation and Compensation of Transmitter l/Q Imbalance

Yijing Xiao, Guanghui He, Jun Ma (Shanghai Jiao Tong University, China) 261

[S12.3] Design Considerations for the Compensation of Phase Noise in OFDM SystemsYi Zhang, Xiaodong Feng, Guanghui He, Jun Ma (Shanghai Jiaotong University, China) 266

[S12.4] Finite Word Length Analysis and Design Of Digital Automatic Gain Control

System for Mobile TV ApplicationsChunhui Ju, Jun Ma (Shanghai Jiao Tong University, China) 270

[S12.5] [Invited] Architecture of a Low-Power FPGA Based on Self-Adaptive VoltageControl

Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama(Tohoku University, Japan) 274

[S12.6] [Invited] Design of a Fine-Grain Reconfigurable VLSI Based on Logic-ln-ControlArchitecture

Nobuaki Okada, Michitaka Kameyama (Tohoku University, Japan) 278

CAD

11:15-12:15 Tuesday, November 24, 2009 Room 202

Chair: Yungseon Eo, Hanyang University, Korea

[S13.1] [Invited] Accelerated Design of Analog, Mixed-Signal Circuits with FineSim and

TitanAnirudh Devgan (Magma Design Automation, USA) 282

[S13.2] [Invited] Chip Package-System Co-DesignJi Zheng, Henry Lee (Apache Design Solutions, USA) 287

[S13.3] [Invited] Thermal Analysis on a two chip TSSVassilios Gerousis, Tze-Ting Fang (Cadence Design Systems, USA)JinTao Xue (Cadence Design Systems, China)Lalit Garg (Cadence Design Systems, India)Tao Li (Cadence Design Systems, China) • 290

[S13.4] [Invited] Advanced Static Verification for SoC DesignsPing Yeung (Mentor Graphics, USA)Sea Choi (Mentor Korea, Korea) • 295

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Analog & Mixed Signal 1


Chair: Jae-Yoon Sim, POSTECH, Korea

[Si4.1] A Variation Tolerent Reconfigurable Time Difference AmplifierSungJin Kim, SeongHwan Cho (KA1ST, Korea) 301

[S14.2] 12x12 Capacitive Matrix Touch Sensing Unit for SoC Application in 0.18um

CMOS process.

Chul Nam,Young-Gun Pu, Kang-Yoon Lee (Konkuk University, Korea) 305

[Si4.3] A 1-V Fully Differential Amplifier with Buffered Nested-Miller Compensation

Meng-Hung Shen, Po-Min Wang (National Tsing Hua University, Taiwan)Li-Wen Wang (National Tsing Hua University, Taiwan Semiconductor Manufacturing Company,

Taiwan)Po-Chiun Huang (National Tsing Hua University, Taiwan) 309

[S14.4] Low-Power Class-AB CMOS OTA with High Slew-Rate

Ah-Reum Kim (Sungkyunkwan University, Korea)Hyoung-Rae Kim (Sungkyunkwan University, Samsung Electronics, Korea)Yoon-Suk Park (Sungkyunkwan University, Korea)

Yoon-Kyung Choi (Samsung Electronics, Korea)Bai-Sun Kong (Sungkyunkwan University, Korea) 313

Data Converters


Chair: Kwang-Hyun Baek, Chung-Ang University, Korea

[S15.1] A Linearization Technique for Voltage-Controlled Oscillator-based ADC

Young-Gyu Yoon (KAIST Institute, Korea)

Min-Chang Cho, SeongHwan Cho (KAIST, Korea) 317

[S15.2] A Time-based Successive Approximation Register Analog-to-Digital Converter

using a Pulse Width Modulation Technique with a Single Capacitor

Young-Hwa Kim, SeongHwan Cho (KAIST, Korea) 321

[S15.3] Design and Implementation of Flash ADC and DBNS FIR filter

Minh Son Nguyen, Jongsoo Kim (University ofUlsan, Korea)Insoo Kim, Kuysun Choi (Pennsylvania State University, USA) 325

[S15.4] A 10b 100MS/S 25.2mW 0.18um CMOS ADC With Various Circuit Sharing

TechniquesBeom-Soo Park, Seung-Hak Ji, Min-Ho Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee

(Sogang University, Korea) 329

[S15.5] [Invited] Parasitic Calibration by Two-Step Ratio Approaching Technique for Split

CapacitorArray SAR ADCs

Si-Seng Wong, Yan Zhu, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R. P. Martins

(University ofMacau, China) 333

XXX


Design Methodology

13:45- 15:00 Tuesday, November 24, 2009 Room 202

Chair: Sang-Bock Cho, Ulsan University, Korea

[S16.1] NBC: Network-based Cache Coherence Protocol for Multistage NoCs

Najla Alfaraj, H. Jonathan Chao (Polytechnic Institute ofNew York University, USA)Mohamed Zahran (The City College of The City University ofNew York, USA) 337

[S16.2] Fast Architecture Exploration with Hierarchical Trace Simulations

Chi-Hung Lin, Pi-Cheng Hsiao, Ching-Hsiang Chuang, Tay-Jyi Lin

(STC/ITRI, Taiwan) 341

[S16.3] GA2CO: Peak Temperature Estimation of VLSI Circuits

Ya-Hsin Chang, Chun-Yao Wang, Yen-An Chen (National Tsing Hua University, Taiwan) 345

[S16.4] Methodology for the Efficient Use of Operands in the Design of Compound

Instructions in ASIP

Jongwon Lee, Minwook Ahn, Jonghee M. Youn, Yunheung Paek

(Seoul National University, Korea) 349

[S16.5] An Area-efficient Built-in Redundancy Analysis for Embedded Memories with

Optimal Repair Rate using 2-D RedundancyJoohwan Lee, Kihyun Park, Sungho Kang (Yonsei University, Korea) 353

SoC for Multimedia*


Chair: Jinsang Kim, Kyung Hee University, Korea

[S17.1] Implementation of H.264 Fractional Motion Estimation using Full Search

Algorithm

Jingyu Ahn, Sehyun Song, Kichul Kim (University of Seoul, Korea) 357

[S17.2] Efficient Integer Motion Estimation Algorithm using Sub-sampling

Sungjo Hwang, Jin Ho Ha, Myung Hoon Sunwoo (Ajou University, Korea) 361

[S17.3] Architecture Optimization for H.264/AVC Propagate Partial SAD Engine in HDTV

ApplicationYiqing Huang, Takeshi Ikenaga (Waseda University, Japan) 365

[Si 7.4] Design of Area-efficient Unified Transform Circuit for Multi-standard Video

Decoder

Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho

(Hankuk University of Foreign Studies, Korea) 369

[S17.5] Application-Specific Instruction Set Processor for H.264 On-Chip Encoder

Kyoungwon Kim, Sanghyun Park, Yunheung Paek (Seoul National University, Korea) 373

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^"^^^^^Platforms and Design Tools for Automotive Systems

13;45 _ ^M Tuesday, November 24, 2009 Room 204

Special session

Organizer: Hiroyuki Tomiyama, Nagoya University, Japan

Chair: Hiroyuki Tomiyama, Nagoya University, Japan

Overview

From a viewpoint of computer engineering, a modern luxury automotive vehicle is a parallel and

distributed computing machine with more than one hundred ECUs (Electronic Control Units) and millions

of lines of software. Automotive systems are an emerging application domain for SOC industry. This

special session focuses on platforms and design tools for embedded systems for automotive applications.

The first paper describes a software platform which is a key technology to efficiently develop ever growing

automotive software. The second paper presents a toolkit for efficient hardware/software co-simulation of

CAN-based automotive network systems. The third paper proposes a two-level hierarchical scheduling

framework with a split interrupt routine, which enables multiple automotive applications to be integrated

on a single ECU with keeping real-time constraints. The last paper presents a new challenge to apply

dynamic reconfiguration technology to the next-generation ECU design.

[S18.1] Integrated Software Platform for Automotive SystemsChiharu Takei, Hiroaki Takada, Masaki Yamamoto, Shinya Honda

(Nagoya University, Japan) 377

[Si8.2] Co-simulation of Multi-ECU Hardware/Software System using Timing

Back-annotation Method

Dai Araki, Hidehisa Takamizawa (InterDesign Technoloigies, Japan) 380

[S18.3] Hierarchical Scheduling for Integrating Real-time Applications with InterruptRoutines

Yutaka Matsubara, Shinya Honda, Hiroaki Takada (Nagoya University, Japan) 384

[Sia.4] A Dynamic Reconfigurable Processor and a Design Tool for the Next Generation

ECUs

Norifumi Yoshimatsu, Trouve Antoine, Takayuki Kando (ISIT, Japan)Kazuaki Murakami (ISIT, Kyushu University, Japan) 388

Analog & Mixed Signal 2 (High Speed Signal Interface)I,, || f|| | „ !„, ,,, ||

J


Chair: Young-Chan Jang, Kumoh National Institute ofTechnology, Korea

[S19.1] [Invited] A Voltage-Controlled Capacitance Offset Calibration Technique for High

Resolution Dynamic Comparator

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Chi-Hang Chan, Yan Zhu, U-Fat Chio, Sai-Weng Sin, Seng-Pan U, R.P. Martins

(University ofMacau, China) 392

[S19.2] [Invited] High-Speed Robust Level Converter for Ultra-Low Power 0.6-V LSIs to

3.3-V I/O

Cheok-Teng Lei, Seng-Pan U, R. P. Martins (University of Macau, China) 396

[S19.3] An Analytic Decision Method for the Feed-forward Equalizer Tap-Coefficients at

Transmitter

Soo-Min Lee, Jae-Yoon Sim, Hong-June Park (POSTECH, Korea) 400

[S19.4] A 8.9mW 25Gb/s Inductorless 1:4 DEMUX in 90nm CMOS

Takayuki Sekiguchi, Shuhei Amakawa, Noboru Ishihara, Kazuya Masu

(Tokyo Institute of Technology, Japan) 404

[S19.5] A CMOS 3.2 Gb/s 4-PAM Serial Link Transceiver

Jikyung Jeong, Jeongjun Lee, Jinwook Burm (Sogang University, Korea) 408

[S19.6] A 36-Context Optically Reconfigurable Gate Array

Mao Nakajima, Minoru Watanabe (Shizuoka University, Japan) 412

DC/DC Converters, Signal Integrity


Chair: Jae-Yoon Sim, POSTECH, Korea

Co-Chair: Taewhan Kim, Seoul National University, Korea

[S20.1] Design of LDO Linear Regulator with Ultra Low-Output Impedance Buffer

Jungsu Choi, Jungeui Park, Wooju Jeong, Junsang Lee, Seok Lee, Jayang Yoon, Jaehoon Kim,

Joongho Choi (University of Seoul, Korea) 420

[S20.2] Design of the Dual Mode DC-DC Buck Converter using Low Power Control

Method

Dong-kyun Lim, Seung-chan Park, Won-Kim, Jung-jin Hwang, Hak-jin Jung, Li-min Park,

Kwang-sub Yoon (Inlia University, Korea) 424

[S20.3] A 93.5% Efficiency, 400-mA Current-Mode DC-DC Buck Converter with

Watchdog Functions

Youngkook Ahn, HyunseokNam, Jeongjin Roh (Hanyang University, Korea) 428

[S20.4] SAT-Based State Encoding for Peak Current Minimization

Yongho Lee, Kiyoung Choi, Taewhan Kim (Seoul National University, Korea) 432

[S20.5] Fast Eye Diagram Determination for the Signal Integrity Verification of

Frequency-Variant Transmission Lines

Hyunsik Kim, Dongchul Kim, Yungseon Eo (Hanyang University, Korea) 436

[S20.6] Signal Integrity Verification of Coplanar Structures for Shielded On-ChipInterconnect Lines

Zafar Bedar Khan, Hyewon Kim, Yungseon Eo (Hanyang University, Korea) 440

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Communication SoCs

15.-15 - 17:00 Tuesday, November 24, 2009 Room 203

Chair: Hanho Lee, Inha University, Korea

[S21.1] Simplified Soft-Decision Demapping Algorithm for DVB-S2

Jang Woong Park, Chang Duk Ryu, Myung Hoon Sunwoo (Ajou University, Korea)Pan Soo Kim, Dae-Ig Chang (ETRI, Korea) 444

[S21.2] A Synchronization Method for Crystal-Less OFDM-Based Wireless Body Area

Network ApplicationsHsiao-Han Ma, Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee (NCTU, Taiwan) 448

[S21.3] High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined

Berlekamp-Massey Algorithm

Jeong-In Park, Kihoon Lee, Chang-Seok Choi, Hanho Lee (Inha University, Korea) 452

[S21.4] An NFC Transceiver using an Inductive Powered Receiver for Passive, Active,

RW and RFID Modes

Jung-Hyun Cho, Peter H. Cole (The University of Adelaide, Australia)Shiho Kim (Chungbuk National University, Korea) 456

[S21.5] Fiber Remote Configuration for an Optically Reconfigurable Gate ArrayYumiko Ueno, Minora Watanabe (Shizuoka University, Japan) 460

[S21.6] A Hardware-Efficient Multi-character String Matching Architecture Using

Brute-force Algorithm

Seongyong Ahn, Hyejong Hong, Hyunjin Kim (Yonsei University, Korea)Jin-Ho Ahn (Hoseo University, Korea)

Dongmyong Baek (ETRI, Korea)Sungho Kang (Yonsei University, Korea) 464

[S21.7] Synchronous Pipelined Two-Stage RADIX-4 200Mbps MB-OFDM UWB Viterbi

Decoder ON FPGA

M.Santhi, G.Lakshminarayanan, R.Sundaram, N.Balachander (NIT, India) 468

Low Power Design Techniques


Chair: Sang-Hoon Hong, Kyung Hee University, Korea

[S22.1] Adaptive Cache-Line Size Management on 3D Integrated Microprocessors

Takatsugu Ono, Koji Inoue, Kazuaki Murakami (Kyushu University, Japan) 472

[S22.2] Model Variable Reduction Technique for High-Level Energy Estimation with an

Accuracy Constraint

Youngjin Cho, Sangyoung Park, Younghyun Kim, Naehyuck Chang


[S22.3] Pipeline Power Reduction through Single Comparator-based Clock GatingWei Wang, YuChi Tsao, Ken Choi (Illinois Institute of Technology, USA)SeongMo Park, Moo-Kyung Chung (ETRI, Korea) 480

xxxiv


[S22.4] Novel RT Level Methodology for Low Power by Using Wasting Toggle Rate based

Clock GatingLi Li, Ken Choi (Illinois Institute of Technology, USA)Seongmo Park, Moo-Kyung Chung (ETRI, Korea) 484

[S22.5] An Adaptive Width Data Cache for Low Power DesignJiongyao YE, Takahiro Watanabe (Waseda University, Japan) 488

[S22.6] Leakage Power Reduction of Functional Units in Processors havingZero-Overhead Loop Counter

Hanmin Park, Jong Kyung Peak, Jinho Lee, Kiyoung Choi


XXXV


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Posterjiession: I ; im

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09;30 - 11:00 Tuesday, November 24, 200? 2nd Floor Lobby

Chair: Jinsang Kim, Kyung Hee University, Korea

[P.1] Compact 0.7-V CMOS voltage/current reference with 54/29-ppm/°C temperature

coefficient

Yoon-Suk Park (Sungkyunkwan University, Korea)

Hyoung-Rae Kim (Sungkyunkwan University, Samsung Electronics, Korea)Jae-Hyuk Oh (Sungkyunkwan University, Korea)

Yoon-Kyung Choi (Samsung Electronics, Korea)

Bai-Sun Kong (Sungkyunkwan University, Korea) 496

[P.2] Implementation of Current-to-Voltage Converter with Wide Dynamic Range and Its

Application

Jae-Hyoun Park, Cheol-Koo Hahn, Hyung-Do Yoon (KETI, Korea) 500

[P.3] Simple Synchronizer to Enhance Time Accuracy for Legacy Ethernet ApplicationsByoung-Yun Lee (Hannam University, ETRI, Korea)Seung-Woo Lee, Bhum-Cheol Lee (ETRI, Korea)

Je-In Baek (Hannam University, Korea) 504

[P.4] A 12-bit Cyclic ADC with Random Feedback Capacitor Interchanging TechniqueChun-Hsien Kuo, Tso-Hung Fan, Tai-Haur Kuo (National Cheng Kung University, Taiwan) •••• 508

[P.5] A 10b 1MS/s 0.5mW SARADC with Double Sampling TechniqueTagjong Lee, Moo-Young Kim (Korea University, Korea)

Yongtae Kim (Texas A&M University, USA)

Phi-Hung Pham (Vietnam National University, Vietnam) 512

[P.6] LED Driver with Self-Optimized Channel Voltage: A Switch-Mode Voltage Regulator

Optimizes an Active Current Regulator for a LED Driver

Jae-Hyoun Park, Hyung-Do Yoon (KETI, Korea) 516

[P.7] A Low-Power Programmable DLL-Based Clock Generator with Wide-Range

Anti-harmonic Lock

Yongtae Kim (Texas A&M University, USA)

Phi-Hung Pham (Vietnam National University, Vietnam)Woonhyung Heo, Jabeom Koo (Korea University, Korea) 520

[P.8] 900 MHz 2.2 mW Spread Spectrum Clock Generator based on Direct Frequency

Synthesis and Harmonic Injection Locking

Woojae Lee, SeongHwan Cho (KAIST, Korea) 524

[P.9] A 5.4Gbps/3.24Gbps Dual-rate CDR with Strengthened Up/Down Pulse Ratio

Jae-Wook Yoo, Dong-Kyun Kim, Jin-Ku Kang (Inha University, Korea) 528

[p.10] A High-Speed Differential Receiver with Low-Power Interleaved Direct Decision

Feedback Equalizer

Min-Sik Han, Sang-Hyuk Yang, Suki Kim (Korea University, Korea)Shin-Il Lim (Seokyeong University, Korea) 532

xxxvi


[P.11] Design and Verification for Dual Issue Digital Signal Processor

Cheng-Hung Lin (National Taiwan Normal University, Taiwan)

Chun-Yu Lin, Shih-Chieh Chang (National Tsing-Hua University, Taiwan) 536

[P.123 PLC Remote Debugger Development Using GDB

Won-Yong Yang, Jong-Yeol Lee (Chonbuk National University, Korea) 540

[P.13] On-chip Current Sensing Circuit for Current-limited Minimum Off-time PFM Boost

Converter

Yeong-Seuk Kim (Chungbuk National University, Korea, University of Adelaide, Australia)Bo-Mi No, Jun-Sik Min (Chungbuk National University, Korea)Said Al-Sarawi, Derek Abbott (University ofAdelaide, Australia) 544

[P.14] A Ring Oscillator-based Temperature Sensor for U-Healthcare in 0.13pm CMOS

Sung-Sik Woo, Jung-Hyup Lee, SeongHwan Cho (KAIST, Korea) 548

[P.15] Implementation of a LED Display System for High Quality Video Processing

Yong-Jun Kim, Byung-Joo Hong, Jun-Dong Cho (Sungkyunkwan University, Korea) 552

[P.16] Inter-Hierarchical Power Analysis Methodology to Reduce Multiple Orders of

Magnitude Run-Time without Compromizing Accuracy

HaiqingNan, Ken Choi (Illinois Institute of Technology, USA) 556

[P. 17] Hardware-Efficient Auto-Correlation for Synchronization of Ml MO-OFDM WLAN

Systems

Jongmin Cho, Youngmin Cho, Mohammad Rakibul Islam, Jinsang Kim, Won-Kyung Cho

(Kyung Hee University, Korea) 560

[P.18] Baseband Transceiver Chip for IR-UWB SystemJung-Yeol Oh, Joo-Ho Park, Mi-Kyung Oh, Jae-Young Kim, Hyung-Soo Lee (ETRI, Korea) • 564

[P.19] Low-Complexity Folded FIR Filter Architecture for ATSC DTV Tuner

Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee (Inha University, Korea) 569

[P.20] 3D Graphics Cache System to Maximize Memory Utilization for an Embedded

System

Youngjin Chung (Yonsei University, Samsung Electronics, Korea)Kilwhan Lee, Jinaeon Lee (Samsung Electronics, Korea)Yongsurk Lee (Yonsei University) 573

[p.21] A Gate Delay Model Considering Temporal Proximity of Multiple Input SwitchingJanghyuk Shin, Juho Kim, Naeun Jang, Eunsuk Park, Yangmin Choi

(Sogang University, Korea) 577

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