20080701-048-hdi image transfer and trend good

8/14/2019 20080701-048-HDI Image Transfer and Trend Good

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Charles Kao, Ph.D

Tel: 02-2601-0700Fax: 02-2602-1556

Mobile: 0939-268-725

[email protected]

HDI Image Transfer

Technology and Trend

V2.1

2007/5/8


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2004/4/15 2/80

1. HDI Development 2. HDI Structure

3. HDI Major Process

4. Fine Line Formation 5. PCB


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HDI DevelopmentFrom through to blind via


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2004/4/15 4/80

Methods to Increase PCB Density

1. Reduce hole and pad diameters

More space for routing

Increase cost, Process difficulty

2. Reduce conductor width

More channels between pads Will increase cost, reduce board yield

3. Increase signal planes

More layers of PCBs

Increase cost

4. Use embedded passives

Increase surface area, reduce routing

Increase cost, Hadco/Sanmina patent issue


5/80

2004/4/15 5/80

HDI (Build-up) Definition

High Density Interconnect --- Mircovia

6 mil (150 m)

IPC/JPCA-2315 Design Guide for HDI and Microvia

Purpose of HDI

More circuit, more via on smaller PCB

Design rule comparison HDI to MLB


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2004/4/15 6/80

Electronic Assembly with HDI/Microvia


7/802004/4/15 7/80

Motorola Mobile phone Development

Lighter, Thinner,Shorter, Smaller

High frequency, High

speed, Multi function , ,

Sequential laminationto form blind and

buried via

Laser drill to form

blind via 2 layer laser vias


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Camcorder

L/S: 65/65~75/75

Via/Pad: 150/250

Notebook PC

L/S 75/75~100/100

Via/Pad:

125~200/250~400

Application cellular phone,

camcorder, notebook,

PDA, GPS

6~10 layer1~2 buildup layers

Need PTH, IVH, BVH

Cellular phone

L/S: 65/65~75/75Via/Pad: 150/250

HDI Applications Miniaturization

Source: PCFab 1999/9, TechSearch


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HDI Applications IC Substrates

Package substrate Flip Chip, BGA, CSP,

MCM, Hybrid

6~12 layer,

1~3 buildup layers IVH, BVH

PTH,

PTH

IVH+BVH

Microvia IC Substrate MPU

L/S: 70/70

Via/Pad: 86/125

ASICVia/Pad: 75/150

Source: PCFab 1999/9, TechSearch


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HDI Application - High Layer Count

Application Router, Server, Base

station, Workstation,

Networking

14~24, up to 32 layers,t=80~180 mil, up to 7.6 mm

1~2, up to 3 buildup layers

PTH, Aspect ratio 12:1

BVH, laser via Low Dk=3.4

Low Df = 0.005

Impedance 8%

Ibiden 1-12-1

Ibiden 1-20-1


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Embedded Passives

Embedded Resister Termination resistor

Buried Capacitor De-coupling, LC filter

Vcc - BC - GND

Power/Ground

Inductor

LC filter
http://www.eurekacp.com.tw/pcb/20010830/index.htm


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PCB Product Market Status

Micro via PCB and IC substrate will accounts

25% of market value in 2007

Source: Prismark, 2003


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PCB

75m

0.25 mm

0.25 mm

150 m

0.25 mm

0.3 mm

0.3 mm

+ 1 mil

+ 2 mil

+ 3 mil

+ 3 mil

+ 5 mil

+ 5 mil

0.4 mil/10m1/1 mil

25 m

Flip chip

0.8 mil/20m2/2 mil

50 m

BGA

1 mil/25m3/3 mil

75 m

HDI

1.2 mil/30m4/4 mil

100 m

Notebook

2 mil/50m5/5 mil

125 m

Desktop PC

2 mil/50m6~8 mil

>150 m

Card/Module

/

PCB


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HDI Roadmap - Ibiden

Source: www.ibiden.co.jp


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HDI PCB (Build-up/HDI PCB)


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Through Hole

Annular Ring

Dielectric

Conductor Space

Conductor Width

2

Inner

Layer #2

1

InnerLayer #1

Multi Layer PCB

Build-up PCB

Buried Via

Blind Via


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Buildup PCB Structure

Buildup PCB

Core

Buildup Dielectric

Blind / Buried

Via

Buildup PCB

Face Buildup + Core

+

Back Buildup

: 1+4+1, 2+2+2,+ +

Multi-layer PTH

Sequential lamination

blind/buried via

1 Layer blind via 2 Layer blind via

Staggered Via

Skipped Via

Stacked Via Via on PTH

Via in Via


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Multi-layer Blind Via Configuration

* Staggered Via

* Skipped Via

L1-L3

* Stacked Via

L1-L2-L3

* Stacked Via

3 Level


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2004/4/15 19/80

Advanced Microvia Configuration

Cu Filled Via

IC Substrate Flip

Chip

Via on PTH

Peeling Strength

Via in via

For Flip chip substrate

signal shielding


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2004/4/15 20/80

Via and Pad

Save space

Reduce routing

Via off Pad Traditional fan out

circuit required

Via in Pad

No Fan Out circuit Microvia on side of

SMT pad

Via on Pad

Microvia under pad


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2004/4/15 21/80

HDI Type I Structure

Type I: 1-C-1, one micro via

layer per side (BVH)

No buried vias

Application

Process

Source: www.ibidenusa.com

Design spec


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HDI Type II Structure -2

Type II: 1-C-C-1, One micro

via layer per side

2 IVH (Inner Via Hole)

Application

Process

Design spec


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2004/4/15 23/80

HDI Type III Structure

Type III: 2-C-2, staggered micro

via

Stacked via

IVH

Application

Process

Design spec


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2004/4/15 24/80

HDI Type IV Structure

Microvia layers usedas RDL over predrilled

passive substrate


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2004/4/15 25/80

HDI Type V Structure

Type V: Even number of layers

Coreless

Plated microvia and

conductive pasteinterconnections

One lamination

Ex. ALIVH/Panasonic


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2004/4/15 26/80

HDI Type VI Structure

Type VI: Electrical

interconnection and

mechanical structure

are formed

simultaneously

Ex. B2it/Toshiba


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HDI

Major Process


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2004/4/15 28/80

Buildup/HDI PCB Core

Buildup

Cu windowing :

Laser via

Cu plating

:

:


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2004/4/15 29/80

Buildup Material & Process Category

Source: The Board Authority 2000/3

Sequential Buildup

Via Formation Metallization Method

Laser Drilling

Coated Foil

* Reinforced

* Non-reinforced

Dielectric Format

Conventional

Reinforced Laminate

*Woven *Non-woven

Liquid* Photoimageable

* Non-photoimageable

Dry Film

* Photoimageable

* Non-photoimageable

Additive Plating

Semi-Additive Plating

Subtractive

Conductive Paste

Photoimaging

Dry or Wet Etch

* Plasma

* Caustic

Mechanical

* Drilling

* Punching * Piercing

Material Via Plating/Circuit


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2004/4/15 30/80

Dielectric Material Material

RCC / RCF

FR4, BT

Liquid Dielectric

Taiyo, Ciba, ..

Film Dielectric

Ajinomoto, Hitachi

Aramid Dupont/Thermount

Equipment

RCF Lamination

Liquid Roller

Coating

Film Vacuum Laminator

Aramid

Lamination


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Photovia

IBM SLC

Pastevia

ALIVH

B2it

Via Formation Methods

Laservia Plasmavia

DYCOstrate


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Via Laser

CO2 Blind Via: 150m

Photo

Blind Via: 150m

Plasma

Through Hole: 60m

Blind Via: 100m

Mechanical Blind Via: 100m


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IBM SLC - Photovia

Surface Laminar

Circuit

IBM Yasu (Japan)

Process

Photo-imageable

dielectric coating

Via exposure

Develop

Via Cu plating

Circuit formation


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Dycostrate - Plasmavia

Dielectric lamination

Via formation

Cu Windowing

Double-side PlasmaEtching

Via Cu plating

Circuit formation

Source: www.dyconex.com


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2004/4/15 35/80

Laser Via on RCF, FR4, ABF

Resin Coated Copper Foil

Cu 12 m

Resin 35~70 m

Dielectric buildup

FR4/RCC Lamination Cure

Via formation

Cu windowing

CO2Laser Drilling

UV Laser direct drilling

Via Cu plating

Outer layer circuit process


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2004/4/15 36/80

Conformal Mask Laser Via Process

1.Buildup layer lamination

RCC

FR-4

2.Skiving

Expose alignment targetin inner layer

3.Conformal mask

Exposure Cu window

Etch Cu window

1.Laser drilling

CO2 laser driller

2.Desmear

Plasma desmear

Wet desmear

3.Electroless Cu

Horizontal line

4.Cu panel plating Horizontal PRP plating

5.Outer layer circuit


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Matsushita ALIVH Process

Non-woven Aramid

Prepreg via formation

Laser Drilling

Conductive paste viafilling

Lamination

Circuit process


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Toshiba B2it Process

Conductive piercingcone printing

PP piercing

Layer lamination

Circuit process


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Fine Line Formation1. Thin Copper2. Fine Line Exposure

3. Fine Line Etching


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Effect of Pitch on L/S Laser Via channel

CSP fanout

Pitch 1.27 mm (48 mil)

Via+ring = 20 mil Max. 3 line per channel

Line width

= (48-20) / 7 = 4 mil

Pitch 0.737 mm Line width

= (0.737 0.35) / 5 3

mil

Pitch 0.8 mm 100 m line x 1

60 m line x 2

Pitch 0.5 mm

50 m line x 1


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2004/4/15 41/80

Fine Line Process Key Issues

L/S Requirement

HDI: 3/3, 2.5/2.5 mil

BGA, CSP, FC: 50/50,

35/35, 25/25 m

Impedance control L/S15% , 10%

Etching Factor

1. Thin Copper

2. Fine Line Lithography

L/S Resolution

Collimation angle Energy uniformity

Overlay registration

Accuracy

3. Fine Line Etching

Uniformity

Etching factor


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2004/4/15 42/80

Copper Foil Thickness and Profile (Copper Foil):

.

E (5 m) (0.20 mil, 5 m)

Q (9 m) (0.34 mil, 9 m)

T (12 m) (0.47 mil, 12 m)

H oz/ft2 (153 g/m2) 0.5 oz (0.7 mil, 18 m)

Foil Profile

Standard: n/a

Low profile (L): max. 10.2 m = 400 in profile Very-low profile (V): max. 5.1 m = 200 in profile


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Subtractive and SAP Process Subtractive (L=50~35 m)

Laminate Cu (T oz, 12 m)

Laminate 2-ply ultra-thin

Cu foil (3~5 m)

then dry film

exposure platingsubtractive etching

Semi-Additive Process:

Lamination (L=25 m)

Laminate Cu (12 m) foil

Flush etch Cu to 8 m

dry film exposure

plating Cu/Sn etching


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Fine Line Etching

Artwork

Finer DPI

Exposure

Collimation

Uniformity

Developing

Uniformity

Reduce puddle effect

Cu foil thickness

Uniformity:

oz Cu 171 m

Etching

Acid etch has better

etching factor

Uniformity

Compensation design


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PCB

4. ,Contact free,

Particle free

4. Productivity/Yield

Throughput

3.

PCB 500 ppm

Mylar 18 ppm/1C, 9 ppm/%RH

3. Dimensional

Stability

PCB distortion

Mask distortion

2.

X-Ray 1 mil 2 mil

2. Registration Alignment

accuracy

Inter-layer

registration

Drilling

accuracy

1. CHA/DA

Uniformity(%)

Etching factor

1. Resolution

/ Line

width/Line space

Tolerance

Undercut


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Resolution and Uniformity

Fine Line Process

Thin copper treating

Fine line exposure and

alignment

Fine line etch

Photoinitiator

30~50% used after exp

Monomer

Uniformity

Glass

Photo Mask

, Partition,

Stepper


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Photo Plotter

Barco Silver Writer

For Mylar/emulsion

Laser

Helium-Neon 633 nm

Red laser diode 670 nm

Resolution

4,000~25,400 dpi

Registration

Accuracy 0.16 mil/4m Repeatability 0.08 mil/2 m

Accuracy 0.5 mil/12.5 m

Repeatability 0.5 mil/12.5 m

PCB 18"x24 4000 dpi, 2 min/pcs

20,000 dpi, 10 min/pcs


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2004/4/15 50/80

Mask Generator

Heidelberg

Mask Write 800

For

Glass/Chrome

Glass/emulsion

Mylar/emulsion

Laser

Nd:Yag 532 nm

Argon-ion 363 nm

Resolution

Resolution:

50, 125, 250, 500 nm

Min. feature:

0.8, 1.7, 3.5, 8 m

Registration

Interferometer: 40 nm

Overlay Accuracy 250 nm

Throughput PCB 18"x22", 50,000 dpi,

35 min/pcs


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2004/4/15 51/80

Photo Mask (Artwork) Error

(Diazo ) Solder mask, circuit

(Emulsion )

Circuit, solder mask

(Photo Mask) for

fine paten exposure

Soda lime w/ emulsion, chrome

cheap

Borosilicate w/ chrome

Low expansion glass

Quartz w/ chrome

Highest quality

Kodak Accumax ARX7

7 mil

: 0.0018% / C

: 0.0009% / %RH

Ex. X: 1.000225

Ex. Y: 1.000625

Ex. L/S:

4.5/3.5

4/4


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2004/4/15 52/80

Mylar Artwork & Photo Mask

Edge

roughness

0.8 m6 mCD

>4.5OD

9 ppmCHE

(%)

18 ppmCTE (

C)

MaskMylar

Mylar/

DiazoMylar/

Emulsion

Glass/

Emulsion


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2004/4/15 53/80

Effect of DPI on Fine Pattern Plotting

6.7%

13.3%

16.9%

26.7%

42.3%

56.4%

84.7%

15m

1.3%

2.7%

3.4%

5.3%

8.5%

11.3%

16.9%

75m

5.0%

10.0%

12.7%

20.0%

31.7%

42.3%

63.5%

20m

10.0%4.0%2.0%0.5050,000

20.0%8.0%4.0%1.0025,400

25.4%10.0%5.0%1.2720,000

40.0%16.0%8.0%2.0012,700

63.5%25.4%12.7%3.178,000

84.6%33.8%16.9%4.236,000

n/a50.0%25.0%6.354,000

10m25m50mm/dotDPI

Based on 10% line width


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2004/4/15 54/80

Photo Resist Development

Fine line dry film resist

Dry Film Components

Dupont, Asahi, NIT

1/1 for outer layer plating

Liquid photo resist Thickness: 10~12 m

3/3 for inner layer etching

Electrical Deposited resist

Nippon Paint

Positive liquid resist

Landless Design

Ex. Dupont dry film

USF < 1 mil, 120~150 mj

SF >1 mil

FX > 2 mil

R > 3 mil, 50~60 mj Regular: 62steps: 0.2 mil

APFX > 4 mil, 20 mj, for

inner layer use

Exposure energy for fineline film is much higher than

normal film

Ultra fine: no change in

energy range


55/80

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Registration Methods and Error Budget

Registration

Via annular ring

Solder mask opening

Alignment method

Global alignment Local alignment

Group mark alignment

Skiing

Conformal mask

Pad to laser via

Pad to PTH

Registration

4 point Alignment

Alignment mark

recognition ability


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PCB Material Distortion

Layer 2 - Post Bond Distortion Model (Stretch

Adjusted)

-400

-300

-200

-100

0

100

200

300

400

-400 -300 -200 -100 0 100 200 300 400


Adjusted)

-400

-300

-200

-100

0

100

200

300

400

-400 -300 -200 -100 0 100 200 300 400

With 1080Fabric

With Thermount(DuPont)

With 2113Fabric


Adjusted)

-400

-300

-200

-100

0

100

200

300

400

-400 -200 0 200 400

Source: Viasystems

Varies with material

Varies with panel size Inconsistent from panel to panel


57/80

PCB


58/80


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2004/4/15 59/80

PCB

(2

mil)

(5

mil)

Partition

Stepper

LDI

LDS

(8

mil)

?

/


60/80

i i


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2004/4/15 61/80

Contact Printing

PCB

Collimated exposure

,

Mask compensation PCB ,

Partition exposure

,

Particle

Collimated


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(Collimation Mirror)

(Exposure Surface)

(Reflection Mirror)

(Short Arc Lamp)

(Collector)

(Dichroic Mirror)

(Integrator)

CollimatedExposure

: 5KW

(CHA): 1.5

(DA) < 1


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0.6 mil

>90%

L/S=20/20 m

Global alignment

Local alignment

Fiducial alignment X-ray alignment

issue

PCB

Low expansion film

sorting

,cycle time


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L/S 1.5 mil

: 20 m

: 4 pnl/min

L/S 1.5 mil

: 10 m

: 3 pnl/min

: 10 m

: 2 pnl/min

ADT SRP 600


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2004/4/15 65/80

ADTec SRP-600

4~16 steps

L/S 20 m

Alignment: 2m

CCD cameras for

alignment retract prior

to exposure.

Stage 1 is an

alignment stage withmovable X, Y, and .

Stage 2 is a step &

repeat stage with

movable X and Y.
http://www.adtec.com/products/photos/srp600image_l.jpghttp://www.adtec.com/products/photos/srp600image_l.jpghttp://www.adtec.com/products/photos/srp600image_l.jpghttp://www.adtec.com/products/photos/srp600image_l.jpghttp://www.adtec.com/products/photos/srp600image_l.jpg


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Projection


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j

Imaging

(8)

PCB(10)

Local alignment

,

Source: www.ushio.co.jp


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2004/4/15 68/80

7~12 m

Alignment 2~3 m

Step & Repeat 5~6"

X Y

Step & Repeat Ushio UX-


69/80

2004/4/15 69/80Source: www.ushio.co.jp

Step & Repeat Ushio UX5038

L/S : 12 m

DoF: 50 m

On-axis 2 CCD alignment

Overlay accuracy: 6.5 m

Scaling: 1000 ppm

Step & Repeat

2 KW Short Arc

35 mw/cm2

5%

: ,Max. 141 x 141 mm

St & S T k M d l 302


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2004/4/15 70/80

Step & Scan Tamarak Model 302

Scanning

1 KW Short Arc

40 mw/cm2

3%

Scan :

200 mm

:

L/S: 4 m

DoF: 30 m

Alignment : 2 m

Source:www.tamsci.com

Laser Projection


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2004/4/15 71/80

jImaging

Anvik HexScan 2100SPE

Excimer UV Laser 351 nm,

45~75 mw/cm2

HexScan 40 x 40 mm

structuring

L/S: 10/10 m

Accuracy: 2.5 m

120 pnl/hr

P j ti ith D i M k


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2004/4/15 72/80

Projection with Dynamic Mask

Ball semiconductor

(Japan)

TI

L Di t I i


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Laser Direct Imaging

PCB (5mj)

CAM

PCB

Global compensation

Local compensation

Ar or UV


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UV Laser

IR Laser

Accuracy

Depth-of-Focus

Scaling

Strip-Butting

X Y

-

2 mil35 m

LDI


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2004/4/15 75/80

Pentax Etec Orbotech Automatech Barco Creo DI-2020 DigiRite 2000 DP-100 DI-2700 Gemini Diamond 5170F

Ar UV laser UV laser Ar+, UV olid-state U IR laser

(nm) 333 333~364 355 nm

(m) 15 5 (m) 5 6.3 6.3 (m) 30 50 50 40 50 25 (m) 10 5 2.5 (m) 5 5 2.5

(m) 15 12.7 10 8 12.7 20 (m) 20 20 5 6.3 (m) 5 (mm) 340x600 610x762 610x810 610x762 613x810 493x711 sec/side 26 30 30 20 30 72

340x250 457x610 457x610 457x610 457x610 457x610

LDI
http://194.7.253.113/ets/products/gemini.htm


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2004/4/15 76/80

Laser

Structuring

Solid state UV laser,

Siemens THG UV laser: LPKF

Laser

Projection Imaging Excimer laser ablation:

Anvik, Tamarak

Laser Direct Str ct ring


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2004/4/15 77/80

Laser Direct Structuring

Siemens Microbeam

Laser PCB

IC Substrate HDI PCB LeadFrame

Nd doped, 1064 nm, diode pump

UV 532 nm, 355 nm

L/S - 50/50 m

Accuracy: 10 m

Source: www.pl.siemens.de


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2004/4/15 78/80

Plate Cu

10~15 m

Immersion Tin

Etch resist

1 m Tin

Laser ablation Tin

1000 mm/sec

Etch

Cu

Strip Tin

Surface Finish

Source: www.pl.siemens.de

Laser Patterning


79/80

2004/4/15 79/80

Laser Patterning

LPKF MicroLine Drill 600

THG UV Laser 355 nm

Scan 60x60 mm

structuring

structuring

L: 20 m

Accuracy: 15 mSource: www.lpkfusa.com


80/80

20080701-048-hdi image transfer and trend good

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