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By Graham BellSenior Director of Marketing

Nassda Corp.

In the past decade, static timinganalysis (STA) emerged as theleading method for timing veri-fication in digital designs. Atnanometer process nodes of130nm and below, however, tra-ditional gate-level STA methodsface increased challenges inproviding accurate results. As aconsequence, nanometer de-signs too often successfully passgate-level STA verification only

to fail in silicon.

At nanometer geometries,digital designs exhibit non-digital behaviors such as dy-namic IR drop, leakage cur-rent and cross-coupling effectsthat degrade timing and oftenlead to circuit failure. In fact,

one leading semiconductormanufacturer has observedthat the move from 180nm to130nm has resulted in a 25xincrease in the number of netsexhibiting signal integrityproblems. In moving to 90nmtechnologies, circuit designersanticipate that nanometer ef-fects will severely impact cir-cuit timing and further erodesilicon success rates.

Among verification method-

ologies, STA became the defacto method for timing verifi-cation largely because it elimi-nated the need for vector sets a distinct advantage in the pastand a necessity today. On theother hand, common knowl-

edge in the industry states thatcurrent STA methods predict

timing within 5 percent of ac-tual performance. For todayshigh-performance circuits, thislevel of variance in predicted behavior can easily translateinto failed silicon.

Sources of errorUnder the influence of nanom-eter effects, conventional STAmethods exhibit increasing pre-cision problems as approxima-tion errors pile up during delaycalculation (Figure 1). Conven-

tional STA tools calculate total

path delay by stepping throughnet and cell elements in eachpath, accumulating static inter-connect delays and library celldelays. The use of approximateinterconnect and cell delays se-riously limits the accuracy of

these methods for nanometer

design applications.Traditional STA methods

account for coupling capaci-tance between two nets by split-ting the coupling capacitanceand adding it to both nets as alumped grounded capacitor.This grounded capacitance isassigned a value that is 2x or 3xthe value of the coupling ca-pacitance for maximum delayor simply 0 for minimum delay.In actual nanometer circuits,wire-to-wire capacitance startsto dominate interconnect de-lay, so this kind of approxima-

tion degrades accuracy.For cell delays, STA tools

rely on a timing model that usesa limited lookup table for eachcell-timing arc. Each table com-prises a two-dimensional arraythat is indexed by input slopeand output load. Althoughmore slope and load pointsmean greater precision, tablesize is kept to a minimum tomaximize efficiency, reducethe library footprint, and speed

data access. With earlier pro-cess generations, these limitedlookup tables provided suffi-cient precision to meet perfor-mance objectives within typicaltiming and layout guardbands.In nanometer circuits, how-ever, performance depends notonly on input slope and outputload at specific process/volt-age/temperature (PVT) operat-ing points, but also on interac-tions between nets and thegrowing influence of parasitic

elements.

Growing challenges in nanometertiming analysis

The use of estimated para-sitics introduces an increasing

source of error in delay calcula-tions. Other dynamic effects likeIR drop, non-linear driver ad-mittance and the impact of resis-tive shielding exacerbate errorsin delay calculation. With na-nometer technologies, conven-tional cell-timing abstracts,lumped interconnect modelsand estimated parasitics are un-able to represent the behavior ofnanometer circuits and errorseasily exceed reasonable guard-bands (Figure 2).

As illustrated in Figure 3,even a relatively simple circuitcan exhibit different failureswhen subjected to seeminglyminor timing violations on theorder of nominal STA precision.In the ideal scenario, whereClock1 and Clock2 operate withno timing variation, timing ob-jectives will be met. On the otherhand, if each clock is subjectedto a relatively minor timingvariation on the order of that

generally expected for STA re-sults the same circuit can ex-hibit either a setup violation ora hold violation. In this ex-ample, a setup violation occursif Clock1 is 4 percent slowerthan expected and Clock2 is 6percent faster than expected,while a hold violation occurs ifClock 1 is 4 percent faster andClock2 is 6 percent slower.

Clearly, even acceptabletiming discrepancies can leadto dramatically different behav-

iors. Yet, actual results may be

Figure 2: At nanometer process nodes, parasitic effects increase.

Figure 1: Conventional static timing analysis neglects dynamic nanometer effects that lead

to multiple sources of errors in delay calculation.

Couplingeffects Interconnect

RC delay

Inaccurate celldelay due to

changed inputslope

Clock delaydue to clock

tree parasitics

85nm

90nm

130nm

180nm

250nm

0% 20% 40% 60% 80% 100%

Unloaded delay

RC delay

Coupling capacitance

IR drop

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far worse than commonly un-derstood. The application ofdynamic methods, to be de-scribed below, in the critical-path verification of actual de-signs suggests that STA preci-sion for nanometer circuits var-ies between 10 percent, evenreaching over 30 percent dis-crepancy in some cases.

Transistor-level analysisBecause of growing influence ofnanometer effects on circuittiming, accurate timing analysisrequires transistor-level dy-namic analysis of circuits. De-

signers have attempted to usetraditional SPICE simulationmethods to achieve sufficientlyaccurate analysis. TraditionalSPICE simulation engines arelimited to circuit blocks nogreater than about 50,000 tran-sistors. As a result, engineershave cut netlists into appropri-ately sized partitionsa tedious,error-prone process that ulti-mately leaves the design team without reliable informationconcerning complex net-to-netinteractions like crosstalk. Al-though fast-SPICE engines

have improved capacity and per-formance for circuit-level analy-sis, these engines achieve theirperformance increase by relyingon the independence of indi-vidual circuit stagesa valid as-sumption for previous technol-ogy nodes, but one that breaksdown in the face of the massivecross-coupling inherent in high-frequency nanometer circuits.

More recent circuit simula-tion engines use hierarchicalmethods to achieve high capac-

ity and performance levels, while retaining SPICE-levelprecision. With the availabilityof these SPICE-accurate, high-capacity circuit simulation en-gines, the problem of achieving

accurate timing analysis be-comes one of executing a tim-ing-analysis methodology thataccounts for dynamic effects innanometer circuits.

Nanometer timing analysismethodologyAccurate delay calculationthrough signal paths requiresaccurate clock timing analysisto determine arrival time ateach internal node. Conse-quently, nanometer timinganalysis begins with timing veri-fication of global clock net-works. Because of the signifi-

cant impact of parasitics on tim-ing of nanometer circuits, thisanalysis includes back-annota-tion of parasitic RCs to everyclock net segment. This analy-sis uses non-linear detail in cellSPICE models as well as preciseloading of each cell to ensureprecision. Along with the grow-ing impact of parasitics, otherphenomena such as IR drop,process variability and agingwill emerge as important factorsin performance degradation.

More recent tools are able tocomplete many of these analy-

ses automatically, starting withautomatic identification ofclock nets based on user-pro- vided starting points. Duringanalysis, these tools automati-cally trace through clock net- works, sensitizing the clockpath through each node and us-ing dynamic transistor-levelsimulation to determine exactperformance at each stage.

Using these results, design-ers can more precisely tuneclock nets and more effectivelydesign optimized clockingschemes. In fact, comparison ofresults obtained with these na-nometer analysis methods hasdemonstrated significant vari-ance with STA results. In a typi-cal example, nanometer timinganalysis of clock networksfound clock timing differencesranging from -4% to 6%, a vari-

ance that significantly impactstiming performance of todayshigh-performance designs.

Critical path analysisThe availability of exact clockarrival time and slope providesthe necessary foundationneeded to perform accurate tim-ing analysis in nanometer cir-cuits. This analysis involvestracing each logic path identi-fied as a critical path by conven-tional STA tools. Each path isback-annotated with parasiticRCs and optional secondaryloads are added as necessary.This approach allows the delaycalculation to account for load-ing of cells not in the path byusing their equivalent Millercapacitance. Using clock wave-forms determined in the previ-ous clock-network analysis, theanalysis sensitizes timing pathsand applies accurate non-linearinput slopes to perform path

simulations.The increasing impact of na-

nometer effects has required asignificant change in the meth-ods used to accurately calculatepath timing. The growing gapbetween STA results and actualperformance arises from limi-tations in static methods basedon fixed lookup tables used inconventional delay calculation.In the nanometer circuit envi-ronment, dynamic effects suchas parasitic coupling introducefrequency-sensitive variationsin timing across nets. Achiev-ing accurate results requireshigh-resolution dynamic simu-lation methods of circuits at thetransistor level.

Advanced analysis methodsare able to simulate the entirecritical path simultaneously,rather than stage-by-stage. This

simultaneous analysis enablesthese tools to include both thedynamic effects of crosstalknoise due to coupling capaci-tance and the effects of signaltransitions on adjacent nets.Because of the dynamic interac-tions caused by parasitic cou-pling capacitance at the transis-tor level, SPICE-accurate cir-cuit simulation is required toachieve sufficient precision.The resulting analysis providesa more accurate assessment ofworst-case timing behavior.

Hybrid analysisThe combination of conven-tional static methods with dy-namic analysis of circuit perfor-mance provides a new hybridanalysis needed to achieve accu-rate timing analysis of nanom-eter designs. In this hybrid ap-proach, the dynamic state can bepropagated from stage to stage,just as static state is propagated

Figure 3: Nanometer effects can alter timing in signal and clock nets.

Clock1

Input

Clock2

Clock1

0%

-4%

+4%

Clock2

0%

+6%

-6%

Clock2

0%

-8%

+8%

Result

Timing objectives met

Setup violation

Hold violation

In1

In2

Out

In1

In2

In1

In2

Out

Out

Min MaxMin Max

Min MaxMin

Nanometer analysisStatic analysis

Max

ActualAssumed

Figure 4: Here, static methods assume that signal In2 is ON resulting in a pessimistic worst-case result for signal Out.

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in conventional STA.Conventional STA methods

always assume worst-case tim-ing or use constant values evenon well-known control signals.As illustrated in Figure 4, in as-suming that signal In2 is ON,static analysis provides a pessi-mistic worse-case result for sig-nal Out, limiting the ability toextract maximum performancefrom otherwise tightly de-signed circuits. In contrast, hy-brid timing analysis methodsconsider all functional changes

Figure 5: Hybrid analysis captures effects of coupling capacitance on timing missed by static analysis.

A

B A

B

Hold violation Setup violation

Aggressor

VictimA

B

C

CLK

Hybrid analysis

Time

Inaccurate static analysis

CLK

D Q

T

T

T

T

F

F

R

R

of all neighboring nets, propa-gating the dynamic state to thenext stage. By concurrently up-dating all nets, this newer ap-proach provides a more realis-tic result, as seen in the resultsfor signal Out in Figure 4.

This kind of concurrent up-dating approach becomes veryimportant for achievinggreater precision in crosstalkanalysis. In nanometer circuits,the specific type of interactionbetween aggressor and victimnets can work to increase or de-

crease delay in victim nets.When an aggressor switches inthe opposite direction to thevictim, the victims signal is ef-fectively delayed; when an ag-gressor signal switches in thesame direction as the victim,the victims signal reachesswitching threshold morequickly, reducing the delay inthe affected path. By ignoringsuch nanometer effects, STAproduces larger inaccuracies inits timing analysis (Figure 5).

By calculating the impact of

neighboring nets, this newerapproach to timing analysis ac-counts for design function andsignal transition windows thatdeliver greater precision. Fur-thermore, the current state ofneighboring nets is used to pro-vide accurate rise/fall transi-tions and min/max delay win-dows, resulting in more accu-rate timing results than pos-sible with traditional STAmethods.

As designers employ morecomplex clock structures,higher frequencies and greaterintegration in nanometer de-signs, these designs will con-tinue to push the limits of con-ventional verification meth-ods. Familiar STA approachesalready fall short in their abil-ity to account for the impact ofnanometer effects on timing,

and the gap between predictedperformance and silicon per-formance will continue to grow with conventional STA meth-ods. By including nanometereffects, advanced timing analy-sis methods deliver the preci-sion needed to accurately pre-dict performanceand avoidcostly silicon iterations. Fordesigners working in nanom-eter technologies, these newertiming analysis methods have become a necessary compo-nent of effective verificationflows.