2 overview of cpu architecture
TRANSCRIPT
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Overview of CPU Architecture
By
Prof. Dr. Shaiq A. Haq
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Basic Architecture
Processor
Control Unit Execute Unit
Main Memory Bus
I/O Devices
Processor
Control Unit
Timing & Sequence Controller
Execute Unit
ALU
Registers
IRPC
Instruction Decoder
Memory
I/O
Control
/Status
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Datapath Operations
Load Read memory location
into register ALU operation
Input certain registersthrough ALU, store
back in register
Store Write register to
memory location
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
10
+1
11
11
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Control Unit
Control unit: configures the executeunit operations
Sequence of desired operations
(instructions) stored in memory program
Instruction cycle broken intoseveral sub-operations, each oneclock cycle, e.g.:
Fetch: Get next instruction into IR
Decode: Determine what theinstruction means
Fetch operands: Move data frommemory to datapath register
Execute: Move data through theALU
Store results: Write data fromregister to memory
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
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Control Unit Sub-Operations
Fetch
Get next instructioninto IR
PC: program
counter, always
points to next
instruction
IR: holds the
fetched instruction
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100load R0, M[500]
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Control Unit Sub-Operations
Decode
Determine what theinstruction means
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100load R0, M[500]
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Control Unit Sub-Operations
Fetch operands
Move data frommemory to Execute
Unit register
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100load R0, M[500]
10
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Control Unit Sub-Operations
Execute
Move data through
the ALU
This particular
instruction does
nothing during this
sub-operation
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100load R0, M[500]
10
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Control Unit Sub-Operations
Store results
Write data from
register to memory
This particular
instruction does
nothing during this
sub-operation
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1100load R0, M[500]
10
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Instruction Cycles
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
PC=100
10
Fetch
ops
Exec. Store
resultsclk
Fetch
load R0, M[500]
Decode
100
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Instruction Cycles
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
10
PC=100Fetch Decode Fetch
ops
Exec. Store
resultsclk
PC=101
inc R1, R0
FetchFetch
ops
+1
11
Exec.Store
results
clk
101
Decode
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Instruction Cycles
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
10...
...
load R0, M[500]500
501
100
inc R1, R0101
store M[501], R1102
R0 R1
1110
PC=100Fetch Decode Fetch
ops
Exec. Store
resultsclk
DecodeFetch
ops Exec.Store
results
PC=101
Fetch
clk
PC=102
store M[501], R1
Fetch Fetch
opsExec.
11
Store
results
clk
Decode
102
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Architectural Considerations
N-bitprocessor
N-bit ALU, registers,
buses, memory data
interface
Embedded: 8-bit, 16-
bit, 32-bit common
Desktop/servers: 32-
bit, even 64
PC size determines
address space
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
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Architectural Considerations
Clock frequency
Inverse of clock
period
Must be longer than
longest register to
register delay in
entire processor
Memory access is
often the longest
Processor
Control Unit Execute Unit
ALU
Registers
IRPC
Controller
Memory
I/O
Control
/Status
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Pipelining: Increasing Instruction
Throughput
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Fetch-instr.
Decode
Fetch ops.
Execute
Store res.
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Wash
Dry
Time
Non-pipelined Pipelined
Time
Time
Pipelined
pipelined instruction execution
non-pipelined dish cleaning pipelined dish cleaning
Instruction 1
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Two Memory Architectures
Processor
Program
memory
Data memory
Processor
Memory
(program and data)
Harvard Princeton
Princeton Fewer memory
wires
Harvard
Simultaneous
program and data
memory access
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A Simple (Trivial) Instruction Set
opcode operands
MOV Rn, direct
MOV @Rn, Rm
ADD Rn, Rm
0000 Rn direct
0010 Rn
0100 RmRn
Rn = M(direct)
Rn = Rn + Rm
SUB Rn, Rm 0101 Rm Rn = Rn - Rm
MOV Rn, #immed. 0011 Rn immediate Rn = immediate
Assembly instruct. First byte Second byte Operation
JZ Rn, relative 0110 Rn relative PC = PC+ relative
(only if Rn is 0)
Rn
MOV direct, Rn 0001 Rn direct M(direct) = Rn
Rm M(Rn) = Rm
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Addressing Modes
Data
Immediate
Register-direct
Registerindirect
Direct
Indirect
Data
Operand field
Register address
Register address
Memory address
Memory address
Memory address Data
Data
Memory address
Data
Addressing
mode
Register-file
contents
Memory
contents
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Microprocessor Architecture Overview
If you are using a particular microprocessor, now is a
good time to review its architecture