Folie 1Instruction set – Collection of instructions
Different computers have different instruction sets
But they have many aspects in common
MIPS (Microprocessor without Interlocked Pipeline Stages) architecture – RISC architecture developed by MIPS technologies
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add a, b, c
This adds the two variables b & c & puts the sum in a
All arithmetic operations are of this form
Perform only one operation
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If we want to place the sum of variables b, c, d & e into variable a, the following sequence of instructions are given
add a, b, c
add a, a, d
add a, a, e
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Regularity makes implementation simpler
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Consider the C statements,
Equivalent MIPS instructions are,
add t0, g, h
add t1, i, j
sub f, t0, t1
MIPS has 32 X 32-bit registers
Used for frequently accessed data
Numbered from 0 to 31
32-bit data --- Word
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MIPS convention – For registers, use two-character names preceded by a dollar sign
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f = (g + h) – (i + j);
Variables f , g, h, i & j are assigned to the registers $s0, $s1, $s2, $s3 & $s4 respectively
Equivalent MIPS instructions are,
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Memory Operands
Main memory is used for complex data structures like arrays, structures etc
To perform arithmetic operations
Memory is a large single dimensional array & is byte addressed
Each address identifies an 8-bit byte
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MIPS is big-endian – Most significant byte is at least address of a word
Load instruction
MIPS instruction is lw (load word)
Format is, operation name followed by the register to be loaded, then a constant (offset) & register used to access memory (base register)
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Compiling Memory Operands
Assume A is an array of 100 words. Consider the statement,
g = h + A[8];
g in $s1, h in $s2 & base address of A in $s3
Equivalent MIPS instructions are,
add $s1, $s2, $t0
MIPS instruction is sw (store word)
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Compiling using Load & Store
Assume h is associated with register $s2 & base address of A is in $s3. Consider the statement,
A[12] = h + A[8];
Equivalent MIPS instructions are,
Keep the most frequently used variables in registers
Memory operations require load & store
More instructions to be executed
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To add constant 4 to register $s3 we write,
addi $s3, $s3, 4
No subtract immediate instruction. For this, use a negative constant
addi $s2, $s1, -2
Constant operands occur frequently
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Cannot be overwritten
add $t2, $s1, $zero
Base 2 numbering is used in computer hardware
In MIPS register names are mapped into numbers as follows:-
Registers $s0 to $s7 map onto 16 to 23
Registers $t0 to $t7 map onto 8 to 15
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R-type format – For register operand instructions
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op – Operation code (opcode)
rd – Register destination operand
funct – Function code (Extends opcode)
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op
rs
rt
rd
shamt
funct
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Machine language version is,
23
0
18
8
8
0
32
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For eg, addi $s1, $s2, 100
Machine language version is,
op rs rt constant
Machine language version is,
op rs rt constant
Keep all instructions the same length
Different instruction formats for different instructions
Different formats complicate hardware, but try to keep the formats similar
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sll by i bits means multiply by 2i
Eg:- sll $t2, $s0, 4 #$t2 = $s0 << 4 bits
Machine language version is,
srl by i bits means divide by 2i
Eg:- srl $t2, $s0, 4 #$t2 = $s0 >> 4 bits
Machine language version is,
For eg, and $s1, $s2, $s3
Machine language version is,
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For eg, or $s1, $s2, $s3
Machine language version is,
28
0
18
19
17
0
37
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a NOR b = NOT (a OR b)
For eg, nor $s1, $s2, $s3
Machine language version is,
28
0
18
19
17
0
39
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Branch to a labeled instruction if a condition is true
Else continue sequentially
Instructions in MIPS
Unconditional branch
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beq reg1, reg2, L1
Go to the statement labeled L1 if the value in reg1 equals the value in reg2
bne reg1, reg2, L1
Go to the statement labeled L1 if the value in reg1 is not equal to the value in reg2
j L1
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if (i == j) f = g + h; else f = g – h;
Assume that variables f through j correspond to registers $s0 through $s4
Compiled MIPS code is,
bne $s3, $s4, Else
add $s0, $s1, $s2
Exit:
while (save[i] == k) i += 1;
Assume that i & k correspond to registers $s3 & $s5 & the base of array, save, is in $s6
Compiled MIPS code is,
add $t1, $t1, $s6 # $t1 = addr of save[i]
lw $t0, 0($t1) # $t0 = save[i]
bne $t0, $s5, Exit # if save[i] ≠ k, exit
addi $s3, $s3, 1 # i = i +1
j Loop
6 bits 5 bits 5 bits 16 bits
For eg, beq $s1, $s2, L1
Machine language version is,
6 bits 26 bits
For eg, j L2
Machine language version is,
Jump & link (jal)
Eg: jal L1 – Jump to the label & simultaneously save the address of the following instruction in $ra
Machine language version is,
Eg: jr $ra – Jump to the address stored in $ra
Machine language version is,
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Set on less than (slt)
Compares two registers & sets a third register to 1 if the first is less than second, else set it to 0
slt $t0, $s3, $s4 # $t0 = 1 if $s3 < $s4
slti $t0, $s2, 10 # $t0 = 1 if $s2 < 10
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Machine language version is,
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For 32-bit constants MIPS has load upper immediate (lui) instruction
Set the upper 16 bits of a constant in a register
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Contents of $t0 after executing the instruction
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First load upper 16 bits as, lui $s0, 61
Now $s0 is,
Add the lower 16 bits as, ori $s0, $s0, 2304
Now $s0 is,
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Eg: add, sub, and, jr
Base or displacement addressing – Operand is at the memory location whose address is the sum of a register & a constant in the instruction
Eg: lw, sw
Eg: andi, ori
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PC-relative addressing – Address is the sum of the program counter (PC) & a constant in the instruction
Eg: beq, bne
Pseudo direct addressing – Address is the 26 bits in the instruction concatenated with the upper 4 bits of program counter
Eg: j, jal