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Boolean Switching Algebra 2-1

Logic Design ©Dong-Seog Han

2. BOOLEAN SWITCHING ALGEBRA

Ÿ Objectives

1. Understand Boolean algebra.

2. Study the basic rules governing logic analysis and design.

George Boole, 1815~1864 John Venn, 1834~1923

2.1 Logic Functions & Switches (1) Boolean Algebra

A mathematical foundation of digital systems.

Ÿ Axioms of Boolean Algebra Algebraic structure consisting of: set of elements S containing at least two elements, a, b, such that ba ¹ binary operations { }+ , { }· unary operation {'} such that the following axioms hold: Closure: For every a, b in S, a. a + b is in S b. a•b is in S

Commutative Laws: For every a,b in S, a. a + b = b + a b. a•b = b•a

Associative laws: For every a, b, c in S a. (a+b)+c=a+(b+c)=a+b+c b. (a•b) •c=a•(b•c)=a•b•c

Identities: a. $ an identity element w.r.to { }+ : 0

a+0=a for " a in S b. $ an identity element w.r.to { }· : 1

a·1=a for " a in S

Distributive laws: For every a, b, c in S a. a+(b •c)=(a+b) •(a+c) b. a•(b+c)=(a•b)+(a•c)

Complement: For each a in S, $ ( )aa or¢ in S s.t.

a. 1=¢+ aa b. 0=¢· aa



Ex. The set { }1,0=B and the logical operations OR, AND, and NOT satisfy all the

axioms of a Boolean algebra.

Ÿ Logic 1 and 0 in Boolean logic Logic 0 Logic 1 False Off Low No

Open switch

True On

High Yes

Closed switch Ÿ Representation of Boolean Operations

1. Gates, 2. Truth Table, 3. Switches, 4. Venn diagram

Ÿ Function : NOT

X Z

¢= =Z X X

X Z

001

1

Logic symbol Logic function Truth Table

X

ZX

X

Z

0

1

0

1

0t 1t 2t 3t 4t time

Switches Venn diagram Timing diagram Ÿ Function : AND

X

YZ

= ·=

Z X YXY

X Y Z

0 0 00 011 0 01 1 1

Logic symbol Logic function Truth Table

X Y

X Y

Z

X

Y

0

1

0

1

0

1

0t 1t 2t 3t 4t time

Z

5t 6t 7t 8t

Switches Venn diagram Timing diagram



Ÿ Function : OR

X

YZ

= +Z X Y

X Y Z

0 0 00 111 0 11 1 1

Logic symbol

Logic function Truth Table

X

Y

Z

YX

X

Y

0

1

0

1

0

1

0t 1t 2t 3t 4t time

Z

5t 6t 7t 8t

Switches

Venn diagram Timing diagram

Ÿ Reference: Buffer

ZX

=Z X

Ÿ IEEE/ANSI standard symbols

Input Variables

Output Variables

Name or Function Symbol

X X'1

XX'1

General IEEE logic symbol

NOT gate

X &

Y

Z

X

Y

Z1³

AND gate OR gate



Ÿ Multiple inputs gates

XYZ

W

XYZ

VW

( )= · · =W X Y Z XYZ

( )( )= · · =V W X Y Z WXYZ

Ÿ Additional Logic Gates Function Gates Truth Table

NAND

( )¢=Z XY

X

YZ

X Y Z

0 0 10 111 0 11 1 0

NOR

( )¢= +Z X Y

X

YZ

X Y Z

0 0 10 011 0 01 1 0

XOR

¢ ¢= Å = +Z X Y XY X Y X

YZ

X Y Z

0 0 00 111 0 11 1 0

XNOR

( )¢= ÅZ X Y

X

YZ

X Y Z

0 0 10 011 0 01 1 1

Ÿ Consider multiple input XOR/XNOR gates

Ÿ IEEE/ANSI standard symbol

X &

YZ

X

Y

³ 1

X =1

Y

Z

X

YZ

=1

NAND gate NOR gate XOR gate XNOR gate



2.2 Gate Logic Ÿ Laws and Theorems of Boolean Algebra

Operation with 0 and 1:

1. + =0X X 2. + =1 1X

1D. · =1X X 2D. · =0 0X

Idempotent theorem:

3. + =X X X 3D. · =X X X

Theorem of complementarity:

4. ( )¢¢ =X X

Theorem of complementarity:

5. ¢+ =1X X 5D. ¢· = 0X X

Commutative law:

6. + = +X Y Y X 6D. · = ·X Y Y X

Associative law:

7. ( ) ( )+ + = + + = + +X Y Z X Y Z X Y Z 7D. ( ) ( )· · = · · = · ·X Y Z X Y Z X Y Z

Distributive law:

8. ( )· + = · + ·X Y Z X Y X Z 8D. ( ) ( ) ( )+ · = + · +X Y Z X Y X Z

Simplification theorems:

9. ¢· + · =X Y X Y X 9D. ( ) ( )¢+ · + =X Y X Y X

10. + · =X X Y X 10D. ( )· + =X X Y X

11. ( )¢+ · = ·X Y Y X Y 11D. ( )¢· + = +X Y Y X Y

DeMorgan’s theorem

12. ( )¢ ¢ ¢ ¢+ + + = · · ·... ...X Y Z X Y Z 12D. ( )¢ ¢ ¢ ¢· · · = + + +... ...X Y Z X Y Z

13. ( ){ }( )

+ ·

¢ ¢ ¢= · +1 2

1 2

, , ..., ,0,1, ,

, , ..., ,1,0, ,n

n

f X X X

f X X X

Duality

14. ( )+ + + = · · ·... ...D

X Y Z X Y Z 14D. ( )· · · = + + +... ...D

X Y Z X Y Z



15. ( ){ }( )

+ ·

= · +1 2

1 2

, , ..., ,0,1, ,

, , ..., ,1,0, ,

D

n

n

f X X X

f X X X

Theorem for multiplying and factoring:

16. ( ) ( )¢ ¢+ · + = · + ·X Y X Z X Z X Y 16D. ( ) ( )¢ ¢· + · = + · +X Y X Z X Z X Y

Ex. Simplify the following Boolean functions to a minimum number of literals and

implement with gates.

a. ( )( ) ( )¢ ¢ ¢+ = · + = + + = · + = +1 1X X Y X X Y X X X Y X Y X Y

b. ( )

( ) ( )¢ ¢ ¢ ¢ ¢+ + = + + + = + + +

¢ ¢= + + + = +1 1

XY X Z YZ XY X Z YZ X X XY X Z XYZ X YZ

XY Z X Z Y XY X Z

Ÿ Equivalent Gate

NAND NOR AND OR

Ex. Generate AND, OR, NOT gates with NAND or NOR. Ex. NOT, OR, AND gates implementation with NAND gates

Ex. NOT, OR, AND gates implementation with NOR gates Ex. Generate NOT gate with EXOR.

Ex. Implement following Boolean logic with NAND gates.

a. ( ) ¢= = +, , ,Z f A B C D AB CD b. ( ) ( )( )¢ ¢ ¢ ¢= = + + + +, ,D f A B C A B C A B C



2.2 Logic Circuits Ÿ IC: ECL, TTL, MOS, CMOS

Ÿ Basic logic gates elements

IC name Function IC name Function

7400 7404 7408 7410 7420 7432

Quad 2-input NAND Hex INVERTERS Quad 2-input AND Triple 3-input NAND Dual 4-input NAND Quad 2-input OR

7402 7405

7411 7427 7486

Quad 2-input NOR Hex INVERTERS with open collector outputs Triple 3-input AND Triple 3-input NOR Quad 2-input XOR

Ÿ Semiconductor

r r= : W ×, resistivity [ m]l

RA

§ Semiconductors materials

silicon (Si), germanium (Ge) and gallium arsenide (GaAs)

electrical properties somewhere in the middle, between those of a

"conductor" and an "insulator".



§ Doping : the process of adding impurity atoms to semiconductor atoms (the

order of 1 impurity atom per 10 million (or more) atoms of the

semiconductor).

§ Silicon

Four valence electrons in its outer most shell which it shares with its adjacent

atoms in forming covalent bonds.

Silicon atoms are arranged in a definite symmetrical pattern making them a

crystalline solid structure. A crystal of pure silicon (silicon dioxide or glass) is

generally said to be an intrinsic crystal (it has no impurities).

Ÿ N-type semiconductor Introduce an impurity atom such as Arsenic, Antimony or Phosphorus into the

crystalline structure making it extrinsic (impurities are added).



Ÿ P-type semiconductor

Introduce a "Trivalent" (3-electron) impurity into the crystal structure, such as

Aluminium, Boron or Indium, only three valence electrons are available in the

outermost covalent bond meaning that the fourth bond cannot be formed.

Ÿ MOS FET

Source(S) Gate(G) Drain(D)Metal Contacts

p Substrate

n n

SiO2 SiO2SiO2

p Substrate

n n

SiO2 SiO2SiO2

GSVDDV

DR

DI

Induced n-type Channel

S G D



Gate

Drain Source

Gate

Drain Source

nMOS FET pMOS FET

Ÿ nMOS FET Inverter

DDV

1Q

DR

INVOUTV

G

S

D

InputLogic Level 0

0

0

1

1

1

50%

50%

PHLt PLHt

OutputLogic Level

Ÿ CMOS General NOT Gate

1X

DDV

Logic 0

nMOS(implement )Z

pMOS(implement )Z

Z

Logic 1

2X

NX

X

DDV

X

1Q

2Q

G

G

S

S

D

D

X 1Q 2Q Z 0 ON OFF

DDV

DDV OFF ON 0

CMOS NOR Gate



DDV

X

Y

YXZ +=

G

G

G G

S S

S

S

DD

D

D1Q

2Q

3Q 4Q

X Y 1Q 2Q 3Q 4Q Z 0 0 ON ON OFF OFF

DDV

0 DDV ON OFF OFF ON 0

DDV 0 OFF ON ON OFF 0

DDV DDV OFF OFF ON ON 0

NAND Gate

DDV

X

Y

= ×Z X Y

1Q 2Q

3Q

4Q

G

G

G G

S

S

S S

D

D

D D

X Y 1Q 2Q 3Q 4Q Z 0 0 ON ON OFF OFF

DDV

0 DDV OFF ON OFF ON

DDV

DDV 0 ON OFF ON OFF DDV

DDV DDV OFF OFF ON ON 0

Ÿ Internal circuit of basic TTL ICs

Input X

GND

OutputZ

VccWK4 WK6.1 W130

WK1

Y

Input X

GND

OutputZ

VccWK4 WK6.1 W130

W4

YWK1

7400 NAND

7402 NOR



Input X

GND

OutputY

VccWK4 WK6.1 W130

WK1

Input X

GND

OutputZ

VccWK4 WK6.1 W130

W800

Y

WK1

WK2

7404 INVERTER 7408 AND

InputX

GND

OutputZ

VccWK4

Y

Wk4

Wk1 Wk1

Wk5.2Wk6.1

W130

7432 OR

Ÿ Voltage level of ICs

IC type Supply voltage Voltage for logic 1 ( )V Voltage for logic 0 ( )V

Range Typical Range Typical TTL = 5CCV 2.4 ~ 5 3.5 0 ~ 0.4 0.2

ECL = -5.2EEV - -0.95 ~ 0.7 -0.8 - -1.9 ~ 1.6 -1.8

CMOS = 3 ~10DDV DDV DDV 0 ~ 0.5 0

Ÿ 7408 Quad 2-input AND gate IC

12 11 10 9 81314

3 4 5 6 721

GND

VCC



Ÿ Timing diagram of 7404

Ÿ Schematic diagram for ( ) ( )= = · + ·, , ,Z f A B C D A B C D

U1A7400

U1B7400

U2A7402 Z

1

23

4

56

2

31

A

B

C

D

Input Port

Variable Name

Pin NumberPart Number

IC Number

Output Port

Ÿ Representation of an IC

AB

CD

Z

IC Name

EXMP211

ABCD

Z

1235

7

Pin No.

Port Name

Internal circuit

Logic symbol



EXMP211

1 2 3 4

8 7 6 5

A B C

DZ

GND

Vcc NC

NC = no connection

Input Output A B C D Z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Pin placement Truth table

2. boolean switching algebra - knubkict-ocw.knu.ac.kr/include/download.html?fn=558af2863... ·...

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