1csnw1
DESCRIPTION
1CSNW1. Computersystemen en Netwerken. Adrie van Doesburg Leo van Moergestel Jan Nijman Wouter van Ooijen. Cursusinformatie. Site: https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04 http://wwwvoti.nl/hvu/V1CSNW1 - PowerPoint PPT PresentationTRANSCRIPT
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1CSNW1Computersystemen enNetwerken
Adrie van DoesburgLeo van MoergestelJan Nijman
Wouter van Ooijen
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Cursusinformatie
Site:https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04 http://wwwvoti.nl/hvu/V1CSNW1
Boek:Computersystemen en embedded systemenL.J.M. van MoergestelAcademic ServiceISBN 978-90-395-2528-9
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CSNW1 lesprogramma
Week 1: Processors, bussystemen
Week 2: Dataopslag
Week 3: Datacommunicatie
Week 4: Computernetwerken, ISO/OSI model
Week 5: Ethernet
Week 6: Internet
Week 7: Inleiding Operating Systems proeftentamen
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PU(s) MEMORY I/O
Adresbus
databus
besturingsbus
Computersysteem (herh.)
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IF
IDEX
Exception Cycle
Von Neumann cyclus (herh.)
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Registers
1001001001001110
1001001001001110
ALUStatus register
Stack pointer
PC
controle
unit
Instruction register
1001101101100011
0011100101111010
memory and I/O
Von Neumann machine (herh.)
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Konrad Zuse's First Computer The Z1 (1936, relais)
Bron: www.epemag.com/zuse
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The Chip that Jack Built Changed the World
Integrated circuitJack Kilby (JK-Flip/Flop) 1959, TI
Bron: www.ti.com/corp/docs/kilbyctr/jackbuilt.shtml
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• Intel: 4004 Processor
• 2300 Transistoren
• 10 um technologie
• 0,108 MHz
Ted Hoff
Microprocessor(Intel 1971)
Bron: /www.intel.com/museum/archives/4004.htm
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Core 2 Duo (Intel 2006)
Core 2 Duo 291M transistoren 65 nm technologie 1-3,3 GHz
Bron: www.intel.com
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RISC versus CISC
Complex instruction set computer (CISC): many addressing modes; complex operations.
Reduced instruction set computer (RISC): load/store; simple operations pipelinable instructions.
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De instructies verrichten simpele taken Alle instructies zijn even groot Er is geen uitgebreide keuze aan adresseer-
modes Er zijn veel interne registers beschikbaar Load and Store architecture
RISC
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Pipelining
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Superscalaire instructieafhandeling
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Super Pipelining
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Super Pipelining (2)
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Kenmerken Processoren
Architectuur Programmeermodel Instructieset Technologie (fabricage)
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ARM Processor Architecture
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Core 2 Duo Architecture
Bron: www.zdnet.com.au
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Cell Processor Architecture(Sony Playstation 3)
Bron: H.P. Hofstee
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Programmeermodellen
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Instructieset (herh.)
Verplaatsing (mov, ldr, str) Bewerking
Logisch (and, or, lsl, … ) Rekenkundig (add, sub, mul, … )
Sprong Conditioneel (beq, bne, … ) Niet conditioneel (jmp, bra, … )
Subroutine aanroep (call, ret, …) Speciale instructies (nop, hlt, swi, … )
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Bus hierarchie
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Timing: Asynchrone Bus
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Timing: Synchrone Bus
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PCI gebaseerd computersysteem
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PCI-bus Burst Transfer
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Accellerated Graphics Port (AGP)
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Intel PM855 Chipset
Bron: www.intel.com
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PCI Express Based System
Bron: AV Bhatt, Intel
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PCI Express Lanes
Bron: AV Bhatt, Intel
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PCI Express Layers
Bron: AV Bhatt, Intel
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USB Architectuur
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USB Hubs
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• A Low Speed rate of 1.5 Mbits/sec that is mostly used for Human Interface Devices (HID) such as keyboards, mice and joysticks.
• A Full Speed rate of 12 Mbit/s.
• A Hi-Speed rate of 480 Mbit/s.
• Plug and play
• Hot swap
• Power supply 5 V, 500 mA
USB signals are transmitted on a twisted pair of data cables, labelled D+ and D−.
These collectively use half-duplex differential signalling.
Transmitted signal levels are 0.0–0.3 V for low and 2.8–3.6 V for high.
Universal Serial Bus (USB)
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Practicum - ZEP2 Simulator
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Links
CPU (Wikipedia) Intel Processors Site SIMD (Wikipedia) DSP (Wikipedia) Computer Bus (Wikipedia) PCI-bus (Wikipedia) PCI Express (Wikipedia) USB in a Nutshell Firewire (Wikipedia)
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Opdrachten
Bestudeer 8.1 t/m 8.3 en 8.6 Lees PCI-express whitepaper Maak opgaven 8.1 t/m 8.5