1811 tai lieu ve psoc.minhhagroup

5/24/2018 1811 Tai Lieu Ve PSoC.minhHaGroup

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Ti liu v PSoC Bn quyn thuc Nguyn Xun Sn KT1 K44 HBKHN

Gii thiu v PSoC

PSoC l mt t vit tt ca cm t ting anh Programmable System on Chip, nghal h thng kh trnh trn mt chp. Cc chp ch to theo cng ngh PSoC cho php thayi c cu hnh n gin bng cch gn chc nng cho cc khi ti nguyn c sn trn

chp. Hn na n cn c th kt ni tng i mm do cc khi chc nng vi nhauhoc gia cc khi chc nng vi cc cng vo ra. Chnh v vy m PSoC c th thay thcho rt nhiu chc nng nn ca mt s h thng c bn ch bng mt n chp. Thnhphn ca chp PSoC bao gm cc khi ngoi vi s v tng t c th cu hnh c, mtb vi x l 8 bit, b nh chng trnh (EEROM) c th lp trnh c v b nh RAMkh ln. lp trnh h thng, ngi s dng c cung cp mt phn mm lp trnh, vd nh cho cc chp PSoC ca Cypress ngi lp trnh phi c phn mm PSoCDesigner. Ngoi ra ci c chng trnh iu khin vo chp th ngi lp trnh phic mt kit pht trin do hng ch to chip cung cp (hoc mt b np). Phn mm thitk c xy dng trn c s hng i tng vi cu trc module ha. Mi khi chc

nng l mt module mm. Vic lp cu hnh cho chp nhth no l ty thuc vo ngilp trnh thng qua mt s thvin chun. Ngi lp trnh thit lp cu hnh trn chp chn gin bng cch mun chp c nhng chc nng g thi ko chc nng v th vokhi ti nguyn s hoc tng t, hoc c hai ty theo tng chc nng (Phng php lptrnh ko th). Vic thit lp ngt trn chn no, loi ngt l g, cc chn vo ra chot ng ch nhth no u ty thuc vo vic thit lp ca ngi lp trnh khithit k v lp trnh cho PSoC. Vi kh nng t cu hnh mnh m ny, mt thit b iukhin, o lng c th c gi gn trn mt chip duy nht. Chnh v l do , hngCypress MicroSystems khng gi sn phm ca mnh l vi iu khin (C) nhtruyn thng, m gi l thit b PSoC (PSoC device), v h hy vng rng, vi kh nng

t cu hnh mnh m, ng

i s dng s c

c nhng thit b iu khin, nhng thitb o c gi r, kch thc nh gn, v sn phm PSoC ca h s thay th c cc thitb da trn vi x l hoc vi iu khin c t trc n nay.

Chp PSoC (CY8C27xxx) cung cp:

B vi x l vi cu trc Harvard.- Tc ca b vi x l ln n 24 MHz- Lnh nhn 8 bit x 8 bit, thanh ghi tch ly l 32 bit- Hot ng tc cao m nng lng tiu hao t-

Di in p hot ng t 3.0 ti 5.25V- in p hot ng c th gim xung 1.0 V s dng ch kch in p- Hot ng trong di nhit -400C n 850C.

Cc khi ngoi vi c th c s dng c lp hoc kt hp 12 khi ngoi vi tng t c th c thit lp lm cc nhim v:

- Cc b ADC ln ti 14 bit- Cc b DAC ln ti 9 bit.- Cc b khuch i c th lp trnh c h s khuch i.- Cc b lc v cc b so snh c th lp trnh c

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Ti liu PSoC bin dch t Datasheet bi Nguyn Xun Sn KT1 K44 - HBKHN

Hnh 3-1 : S khi cu trc ca PSoC (CY8C27000)

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8 khi ngoi vi s c th c thit lp lm cc nhim v:- Cc b nh thi a chc nng, m s kin, ng h thi gian thc, b

iu ch rng xung c v khng c di an ton (deadband)

- Cc modun kim tra li (CRC modunles)- Hai b truyn thng ni tip khng ng b hai chiu- Cc b truyn thng SPI Master hoc Slave c th cu hnh c- C th kt ni vi tt c cc chn vo ra.

B nh linh hot trn chp- Khng gian b nh chng trnh Flash t 4K n 16K, ph thuc vo tng

loi chp vi chu k ghi xa cho b nh Flash l 50.000 ln

- Khng gian b nh RAM l 256 byte- Chp c th lp trnh thng qua chun ni tip (ISSP)- B nh Flash c th c nng cp tng phn- Ch bo mt a nng, tin cy- C th to c khng gian b nh Flash trn chp ln ti 2,304 byte

C th lp trnh c cu hnh cho tng chn ca chp- Cc chn vo ra ba trng thi s dng Trigger Schmitt- u ra logic c th cung cp dng 25mA vi in tr treo cao hoc thp bn trong- Thay i c ngt trn tng chn- ng ra tng t c th cung cp dng ti 40mA- ng ra a chc nng c t 6 n 44 ty thuc vo tng loi chp

Xung nhp ca chp c th lp trnh c- B to dao ng 24/48MHz bn trong ( chnh xc l 2,5%, khng cn

thit b ngoi)

- C th la chn b dao ng ngoi ln ti 24MHz- B dao ng thch anh 32,768 kHz bn trong- B to dao ng tc thp bn trong s dng cho Watchdog v Sleep

Ngoi vi c thit lp sn- B nh thi Watchdog v Sleep phc v ch an ton v ch ngh- Module truyn thng I2C Master v I2C Slave tc ln ti 400kHz- Module pht hin in p thp c cu hnh bi ngi s dng

Cng c pht trin- Phn mm pht trin min ph (PSoCTMDesigner)- B lp trnh v b m phng vi y tnh nng- M phng tc cao

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Chng 4: Cu trc Vi x l1. B vi x l CPU1.1. Gii thiu chung

Cc h chp ca PSoC da trn b vi x l mnh m 8 bit vi cu trc Harvard(Cu trc Harvard l cu trc m bus d liu, bus a ch v tn hiu iu khin ca bnh chng trnh v b nh d liu c lp vi nhau). N c 5 thanh ghi iu khinhot ng chnh ca CPU. Nhng thanh ghi ny b tc ng bi nhng lnh khc nhau.Ngi s dng khng th truy cp trc tip vo cc thanh ghi ny thng qua khnggian b nh cc thanh ghi. Cc thanh ghi ca CPU c cho trong bng sau:

Bng 4-1: Cc thanh ghi ca CPU

Thanh ghi M gi nhFlags (thanh ghi c) CPU_FProgram Counter (thanh ghi m chng trnh) CPU_PC

Accumulator (thanh ghi cha) CPU_AStack Pointer (thanh ghi con tr Stack) CPU_SPIndex (thanh ghi ch s) CPU_X

B m chng trnh l mt thanh ghi16 bit (CPU_PC), n cho php ngi lptrnh truy cp trc tip vo ton b khng gian b nh chng trnh trn chp (16Kbytes i vi thnh vin ln nht). y l mt khng gian nh lin tc v khng cnphi to thnh trang (no paging).

Thanh ghi cha (Accumulator) l mt thanh ghi a mc ch, n thng c sdng lu gi kt qu ca bt c mt lnh no s dng ch a ch ngun.

Thanh ghi ch s c dng lu gi gi tr Offset ( lch) trong ch a ch chs. Tiu biu l n c dng a ch mt khi d liu bn trong khng gian nh d liu.

Thanh ghi Con tr Stack (Stack Pointer) lu gi a ch ca nh Stack trongkhng gian nh d liu. N b tc ng bi nhng lnh nh PUSH, POP, LCALL,RETI v RET. Ni chung l tt c nhng lnh c lin quan n stack ca phn mm.N cng c th b nh hng bi lnh SWAP v lnh ADD.

Thanh ghi c (Flags) c ba bit trng thi: bit c khng - Zero Flag bit[1]; bit cnh -Carry Flag bit[2]; bit Supervisory State[3]. Bit cho php ngt ton cc GlobalInterrupt enable bit[0] c dng cho php hoc cm ton b cc ngt. Cc c trnb nh hng bi nhng lnh ton hc, nhng lnh logic. v.v

1.2. Thanh ghi ca CPU1.2.1. Thanh ghi c (Flags Register)

Bng 4-2: Thanh ghi c(CPU_F)

Bit # 7 6 5 4 3 2 1 0POR 0 0 0 0 0 0 1 0

Read/Write -- -- -- RW R RW RW RWBit Name Reseved Reseved Reseved XIO Super Carry Zero Global IE

Bit 7: Reserved (cha c nh ngha)

Bit 6: ReservedBit 5: ReservedBit 4:XIO - c t bi ngi s dng cho php la chn gia cc dy thanh ghi

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0 = Bank 01 = Bank 1Bit 3: ReservedBit 2: Carry - c t bi CPU ch r ton t trong php ton logic hoc ton hc trc cnh hay khng0 = No Carry (khng c nh)1 = Carry (c nh)

Bit 1: Zero -

c t bi CPU ch r ton t trong php ton logic hoc ton hc tr

c cbng khng hay khng.0 = Not Equal to Zero (khng bng khng)1 = Equal to Zero (bng khng)Bit 0: Global IE Quyt nh ton b cc ngt l cho php hay b cm0 = Disabled (cm)1 = Enabled (cho php)

1.2.2. Thanh ghi chaBng 4-3: Thanh ghi cha (CPU_A)

Bit # 7 6 5 4 3 2 1 0

POR 0 0 0 0 0 0 0 0Read/Write System1 System1 System1 System1 System1 System1 System1 System1

Bit Name Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0]Bit [7:0]: 8 bit d liu lu gi kt qu ca bt c mt lnh ton hc/logic s dng ch a chngunCh : POR(Power on reset):Trng thi ca bt sau khi reset ngun.

System1: do h thng iu chnh, ngi dng khng th thay i trc tip c gi trca nhng bit ny

1.2.3. Thanh ghi ch sBng 4-4: Thanh ghi ch s(CPU_X)

Bit # 7 6 5 4 3 2 1 0POR 0 0 0 0 0 0 0 0

Read/Write System1 System1 System1 System1 System1 System1 System1 System1

Bit Name Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0]Bit [7:0]: 8 bit d liu lu gi ch s cho bt c mt lnh no s dng ch a ch ch s

1.2.4. Thanh ghi con tr StackBng 4-5: Thanh ghi con tr Stack(CPU_SP)

Bit # 7 6 5 4 3 2 1 0POR 0 0 0 0 0 0 0 0

Read/Write System1 System1 System1 System1 System1 System1 System1 System1

Bit Name Data[7] Data[6] Data[5] Data[4] Data[3] Data[2] Data[1] Data[0]Bit [7:0]: 8 bit d liu lu gi gi tr con tr stack hin thi (tr vo nh ca stack)

1.2.5. Thanh ghi b m chng trnhBng 4-6: Thanh ghi b m chng trnh (CPU_PC)

Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Read/write

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

BitName

Data[15]

Data[14]

Data[13]

Data[12]

Data[11]

Data[10]

Data[9]

Data[8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2]

Data[1]

Data[0]

Bit[15:0]: 16 bit D liu l byte thp v byte cao ca b m chng trnh

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Hnh 4-1 : Cu trc lin kt ca CPU vi b nh (cu trc Harvard)

1.3. nh dng ca lnh1.3.1.Lnh 1 byte

Lnh 1 byte l lnh khng dng a ch hay d liu nhton hng. lnh 1 byte sdng mt m lnh 8 bit v d nhRET,ASR,INC,DEC

Bng 4-7 : Dng lnh 1 byte

Byte 08- bit opcode

1.3.2.Lnh 2 byteLnh 2 byte l lnh dng duy nht mt ton hng l d liu hay a ch. Lnh 2

byte s dng byte u tin cha m lnh, byte th hai cha d liu hoc a ch.Hoc n s dng 4 bit u cho m lnh v 12 bit sau cho a ch.


Byte 0 Byte 14-Bit opcode 12-bit relative address

8-Bit opcode 8-bit data8-Bit opcode 8-bit address

1.3.3.Lnh 3 byte54


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Lnh loi ny s dng 3 byte bi v n c s dng di chuyn d liu giahai a ch trong khng gian a ch m ngi s dng c th truy nhp. Hoc n dng lu gi mt gi tr a ch tuyt i 16 bit trong cc lnh LCALL v LJMP.


Byte 0 Byte 1 Byte 28-Bit opcode 16-bit address (MSB,LSB)8-Bit opcode 8-bit data 8-bit data8-Bit opcode 8-bit address 8-bit address

1.4. Cc ch a ch trong PSoC1.4.1. Ch a ch ngun tc thi (Source Immediate)

Nhng lnh s dng ch a ch ny c gi tr ngun c lu gi trong tonhng 1 ca lnh, kt qu c lu gi trong thanh ghi A, thanh ghi F, thanh ghi SP haythanh ghi X c ch r trong lnh. Lnh s dng ch a ch ny c di l 2 byte.

Bng 4-10 : Ch a ch ngun tc thi

Opcode Operand 1Instruction Inmediate Value

Vd:M ngun M my Ch thch

ADD A,7 01 07 Gi tr tc thi l 7 c cng vo thanh cha, kt qu c luvo thanh cha

MOV X,8 57 08 Gi tr tc thi l 8 c chuyn vo thanh ghi XAND F,9 70 09 Gi tr tc thi l 9 c AND vi gi tr trong thanh ghi F, kt

qu ca php AND c t trong thanh ghi F

1.4.2. Ch a ch ngun trc tip (Source Direct)Trong ch ny th a ch ngun c lu gi trong ton hng 1 ca lnh.

Trong sut qu trnh thi hnh lnh th a ch c dng ly gi tr ngun t RAMhoc t khng gian a ch thanh ghi. Kt qu c ch r trong lnh l t vo thanhghi X hay thanh ghi A. Tt c nhng lnh s dng ch a ch trc tip u l lnhc di 2 byte.

Bng 4-11 : Ch a ch ngun trc tip

Opcode Operand 1Instruction Source Address

V d:M ngun M my Ch thch

ADD A,[7] 02 07 Gi tr trong b nh ti a ch 7 c cng vo thanh cha ktqu li c lu gi trong thanh cha

MOV X, REG[8] 5D 08 Gi tr trong khng gian thanh ghi ti a ch 8 c chuyn vothanh cha

1.4.3. Ch a ch ngun ch s (Source Indexed)Trong ch ny th d liu ca ngun c truy xut trong RAM hoc khng

gian a ch thanh ghi thng qua a ch l gi tr hin thi ca thanh ghi X cng vimt ch s. Kt qu c ch r trong lnh l lu gi trong thanh ghi X hay thanh ghiA. Lnh c di l 2 byte

Bng 4-12 : Ch a ch ngun ch s

Opcode Operand 1

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Instruction Source Index


ADD A,[X+7] 03 07 Gi tr trong b nh ti a ch X+7 c cng vo thanh cha, ktqu li c lu vo thanh cha

MOV X,[X+8] 59 08 Gi tr trong b nh ti a ch X+8 c di chuyn vo thanh ghi X

1.4.4. Ch a ch ch trc tip (Destination Direct)Nhng lnh thuc ch a ch ny c a ch ch c lu tr trong m my

ca lnh, a ch ngun c ch r trong lnh l thanh ghi A hay X. Tt c nhng lnhs dng ch a ch ny u l lnh 2 byte.

Bng 4-13 : Ch a ch ch trc tip

Opcode Operand 1Instruction Destination Address


ADD [7], A 04 07 Gi tr trong thanh cha c cng vi gi tr trong b nh ti ach 7, kt qu li c lu vo b nh ti a ch 7. Gi tr thanhcha khng i

MOV REG[8], A 60 08 Gi tr trong thanh cha c di chuyn vo khng gian thanh ghiti a ch 8. Gi tr thanh cha khng i.

1.4.5. Ch a ch ch ch s (Destination Indexed)Nhng lnh thuc ch a ch ny c ch c xc nh bng cch ly gi tr

ca thanh ghi X cng vi mt ch s lm a ch truy xut vo b nh, ngun cxc nh trong lnh l thanh ghi A hoc mt gi tr tc thi. Nhng lnh s dng ch a ch ny u l lnh c di 2 byte.

Bng 4-14 : Ch a ch ch ch s

Opcode Operand 1Instruction Destination Index


ADD [X+7], A 05 07 Gi tr trong b nh ti a ch X+7 c cng vo thanh cha, ktqu c lu vo b nh ti a ch X+7, thanh cha khng thay i

1.4.6. Ch a ch ch trc tip, ngun tc thi tc thi (Destination Direct,Source Immediate)

Nhng lnh thuc ch a ch ny c a ch ca ch c lu gi trong tonhng 1 ca lnh. Gi tr ca ngun c lu tr trong ton hng 2 ca lnh. Tt cnhng lnh thuc ch a ch ny u l lnh c di 3 byte.

Bng 4-15 : Ch a ch ch trc tip, ngun tc thi

Opcode Operand 1 Operand 2Instruction Destination Address Immediate Value

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ADD [7],5 06 07 05 Gi tr trong b nh ti a ch 7 c cng vi gi tr tcthi 5, kt qu li c lu vo b nh ti a ch 7.

MOV REG[8],6 62 08 06 Gi tr tc thi 6 c di chuyn vo khng gian thanh ghiti a ch 8

1.4.7.Ch a ch ch ch s, ngun tc thi (Destination Indexed, SourceImmediate)Trong ch ny th gi tr ca thanh ghi X cng vi mt ch s c ly lm a

ch ly d liu trong b nh. Cn d liu ngun l mt s trc tip. Tt c nhnglnh thuc ch a ch ny u l lnh 3 byte.

Bng 4-16 : Ch a ch ch ch s, ngun tc thi

Opcode Operand 1 Operand 2Instruction Destination Index Immediate Value


ADD [X+7],5 07 07 05 Gi tr trong b nh ti a ch X+7 c cng vi gi trtc thi 5, kt qu li c lu vo b nh ti a ch X+7.

MOV REG[X+8],6 63 08 06 Gi tr tc thi 6 c di chuyn vo khng gian thanhghi ti a ch X+8

1.4.8.Ch a ch ch trc tip, ngun trc tip (Destination Direct, Source Direct)Ch c duy nht mt lnh s dng ch a ch ny, a ch ca ch c lu

gi trong ton hng 1 ca lnh cn a ch ca ngun c lu gi trong ton hng 2ca lnh. Tt c nhng lnh s dng ch a ch ny u l lnh c di 3 byte.

Bng 4-17: Ch a ch ch trc tip, ngun trc tip

Opcode Operand 1 Operand 2Instruction Destination Address Source Address


MOV [7],[8] 5F 07 08 Gi tr trong b nh ti a ch 8 c di chuyn vo b nhti a ch 7.

1.4.9. Ch a ch s dng con tr t ng tng a ch Con tr l ton hng ngun (Source Indirect Post Increment)

Ch c duy nht mt lnh s dng ch a ch ny, a ch ngun lu gi trongton hng 1 hot ng nha ch ca mt con tr. Trong sut qu trnh lnh thi hnhth gi tr ca con tr s quyt nh xem d liu no trong RAM s c c. Sau khic xong d liu th gi tr ca con tr c tng ln 1.

Bng 4-18 : Ch a ch Source Indiect Post Increment

Opcode Operand 1Instruction Source Address Pointer


MVI A,[8] 3E 08 Gi tr trong b nh ti a ch 8 tr ti mt nh trong RAM. Gi

tr ti nh con tr tr ti s c di chuyn vo thanh cha. Sau, gi tr trong b nh ti a ch 8 c tng ln.

Con tr l ton hng ch (Destination Indirect Post Increment)57


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Ch c duy nht mt lnh s dng ch a ch ny, a ch ch lu gi trongton hng 1 hot ng nha ch ca mt con tr. Trong sut qu trnh lnh thi hnhth gi tr ca con tr s quyt nh xem d liu no trong RAM s c c. Sau khic xong d liu th gi tr ca con tr c tng ln 1.

Bng 4-19: Ch Destination Indirect Post Increment

Opcode Operand 1Instruction Destination Address Pointer


MVI [8],A 3F 08 Gi tr trong b nh ti a ch 8 tr ti mt nh trong RAM. Gitr trong thanh cha s c di chuyn ti v tr nh m con trtr ti. Sau , gi tr trong b nh ti a ch 8 c tng ln.

Nhn xt: Nhvy ta thy cc ch a ch trong PSoC cng tng i d hiu, tmli n ch bao gm:

- Cc d liu tc thi l cc con s: V d: 5 , 6 , 7 , 8 - Cc d liu trc tip c xc nh thng qua cc a ch. V d: [7] , [8] - Cc d liu c xc nh thng qua ch s, n l d liu a ch [X+ch s)]: v

d: [X+5], [X+6], .

- Cc d liu c xc nh gin tip thng qua con tr nhtrong hai ch a chcui. y cng l hai ch a ch m t loi Vi x l c c.

- Ta c th nhn thy rng nhng lnh ly thanh ghi A hoc X nhl mt phn caton hng u l lnh 2 byte (xem li cc v d trn). S d nhvy l v trong mlnh c nh ngha sn l lm vic vi thanh ghi no. Chng hn nhtrong v

d ca mc 2.4.1 th ta c th thy l m my gm 2 byte, byte u tin l m lnhca lnh cng vo thanh cha, byte th hai l gi tr c cng vo thanh cha.Nhvy, vi cch nh ngha trn th nhng lnh nhvy s tit kim c chu khot ng ca chip, t rt ngn c thi gian thc hin lnh. Vic m ha nhvy cho php pht huy tc tnh ton ca chp trong nhng ng dng i hi tc tnh ton cao.

- Ngoi ra cn phi phn bit gia cch truy xut b nh RAM v b nh khng gianthanh ghi. Cch truy xut hai b nh ny c phn bit thng qua lnh. V d: [7]l d liu ti a ch 7 trong RAM, nhng REG[7] li l d liu ti a ch 7 trongkhng gian thanh ghi.

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2. Ngt v B iu khin ngtBng 4-20: Cc thanh ghi ca b iu khin ngt

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access0,DAh INT_CLR0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW:00

0,DBh INT_CLR1 DCB13 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00 RW:00

0,DDh INT_CLR3 I2C RW:000,DEh INT_MSK3 ENSWINT I2C RW:00

0,E0h INT_MSK0 VC3 Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor RW:00

0,E1h INT_MSK1 DCB13 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00 RW:00

0,E2h INT_VC Pending Interrupt [7:0] RC:00

x,F7h CPU_F XOI Carry Zero GIE RL:00

Ch :L: Nhng lnh nh hng n c nh AND, OR v XOR c th c dng thay ithanh ghi nyx: ch x nm trc du phy trong trng a ch ch r rng thanh ghi ny c th ctruy nhp m khng cn bit l dy thanh ghi no ang c s dng.

B iu khin ngt cho php mt on m ca ngi lp trnh c thc hin mikhi c mt ngt sinh ra t cc khi chc nng trong chip PSoC. Mi mt khi s cmt ngt ring v mi mt ct khi tng t cng c mt ngt ring. Mi mt ngt chongun cp, ch ng, xung nhp thay i, v mt ngt ton cc cho cc chn vo raa chc nng.

B iu khin ngt cng vi nhng thanh ghi ca n cho php cc ngt c th b vhiu ha ng thi hoc c lp vi nhau. Cc thanh ghi cung cp mt cch thc ngi s dng c th xa tt c nhng ngt ang ch v thng bo ngt, hoc c th xamt cch c lp hay ring bit thng bo ngt v ngt ch. Mt k thut phn mmc cung cp cho php ngi lp trnh thit lp ngt mt cch ring bit. Thit lp

mt ngt bng k thut ny rt mnh m v hu ch cho vic pht trin m ngun, khim n khng c h thng phn cng hon chnh sinh ra mt ngt thc.

Bng 4-21 : Bng vector ngt ca CY8C27xxx

Mc u tin ngt a ch ngt Tn ngt0 (cao nht) 0000h Reset1 0004h Supply Voltage Monitor2 0008h Analog Column 03 000Ch Analog Column 14 0010h Analog Column 25 0014h Analog Column 3

6 0018h VC37 001Ch GPIO8 0020h PSOC Block DBB009 0024h PSOC Block DBB0110 0028h PSOC Block DCB0211 002Ch PSOC Block DCB0312 0030h PSOC Block DBB1013 0034h PSOC Block DBB1114 0038h PSOC Block DCB1215 003Ch PSOC Block DCB1324 0060h I2C25 (thp nht) 0064h Sleep Timer

2.1. M t cu trc ca b iu khin ngt59


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Interrupt Source: Ngun ngt (b nh thi, cc chn vo ra a chc nng... )

Interrupt Taken or INT_CLRx Write: Thi hnh ngt hoc xa ngt

INT_MSKx: Lp mt n che ngt

Post Interrupt: Thng bo ngt

Pending Interrupt: Ngt ch

Priority Encoder: B m ha mc u tin ca ngt

GIE (CPU_F[0]): Cho php ngt ton cc (Global Interrupt Enable)

Interupt Request: Yu cu ngt

Hnh 4-2: S khi ca b iu khin ngt

Dy cc s kin xy ra khi mt ngt c thi hnh nhsau:

1. Khi mt ngt c kch hot, c th l do mt iu kin ngt c sinh ra (dotrn b m chng hn) v trc thng bo ngt c cho php bi thanh ghimt n che ngt, hoc c mt ngt ang ch c x l v GIE (global interruptenable - cho php ngt ton cc) c t t 0 sang 1 trong thanh ghi c caCPU.

2. Lnh thi hnh hin thi kt thc bin gii lnh (bin gii lnh l thi imCPU chuyn t lnh ny sang lnh khc).

3. Th tc ngt bn trong c thc hin, tiu tn 13 chu k my. Trong khongthi gian ny th CPU thc hin nhng cng vic sau:

- Lu byte cao, byte thp ca b m chng trnh (PCH v PCL) vthanh ghi c (CPU_F) vo trong Stack theo th t nhtrn.

- Thanh ghi c c xa trng v t bit GIE b xa v 0 v nhngngt mi sinh ra tm thi b cm.

- Byte cao ca b m chng trnh (PC[15:8]) c xa v 0 (zero)- Vector ngt c c t b iu khin vector ngt v gi tr ca n

c t vo trong byte thp ca b m chng trnh (PC[7:0]). Vicny s t b m chng trnh tr vo a ch thch hp trong bngvector ngt.

4. Chng trnh s thi hnh vector trong bng vector ngt. Nhn chung th mt lnhLJMP trong bng vector ngt s chuyn s thi hnh ca CPU ti trnh phc vngt ca ngi dng phc v cho ngt ny.

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5. Trnh phc v ngt c thi hnh. Lu rng tt c cc ngt u b v hiu hak t khi bit GIE = 0. Cc ngt khc c th c m li trong trnh phc v ngtnu cn thit bng cch t bit GIE = 1 (hy cn thn trong vic ny bi v nc th lm trn Stack)

6. Khi trnh phc v ngt kt thc vi lnh RETI th thanh ghi c (CPU_F), bytethp v byte cao ca b m chng trnh c ly ra khi Stack theo ng

trnht nhtrn. T khi thanh ghi c (CPU_F) c khi phc li gi tr th ns cho php cc ngt. (GIE =1).

7. Chng trnh s bt u thi hnh lnh k tip, ngay sau lnh c thc hintrc khi xy ra ngt. Tuy nhin, nu nhc ngt ang ch c phc v th ns c thc hin trc.

2.2. Cc thanh ghi ngtBng 4-20 cho ta mt ci nhn tng quan v mi quan h ca cc thanh ghi

i vi hot ng ca b iu khin vector ngt. Chi tit v s dng cc thanh ghi ctrnh by sau y.

2.2.1. Thanh ghi INT_CLRxC 3 thanh ghi xa ngt (INT_CLR0, INT_CLR1 v INT_CLR3) c th c

quy vo tn gi chung INT_CLRx. Nhng thanh ghi INT_CLRx l tng t nhnhngthanh ghi INT_MSKx ngha l chng gi mt bit cho mi ngun ngt. Tuy nhin, vmt chc nngth thanh ghi INT_CLRx li ging nhthanh ghi INT_VC mc d hotng ca chng hon ton c lp vi nhau. Khi mt thanh ghi INT_CLRx c cth bt k bit no c t u ch r l ngt no thng bo cho ti nguyn phncng . Bi vy, c nhng thanh ghi s gip cho ngi s dng xc nh c ttc cc thng bo ngt.

Cch mt gi tr bit ring r c ghi vo thanh ghi INT_CLRx c quyt nhbi bit ENSWINT (Enable Software Interrupt) trong thanh ghi INT_MSK3. Khi bitENSWINT c xa (trng thi mc nh), vic vit 1 vo mt bit no trong thanhghi INT_CLRx u khng c tc dng g. Tuy nhin, vic vit 0 vo mt bit no trong thanh ghi INT_CLRx trong khi bit ENSWINT = 0 s xa thng bo ngt tngng. Nu bit ENSWINT = 1 th vic vit 0 vo bt c bit no trong thanh ghiINT_CLRx s b b qua. Tuy nhin, vic vit 1 vo mt bit no trong thanh ghiINT_CLRx trong khi bit ENSWINT = 1 s lm cho mt ngt tng ng c thngbo. Vic m ngt mm s cho php m ca ngi s dng to ra mt ngt mm v cth hu ch cho vic g ri trong trnh phc v ngt, hay loi tr nh hng ca vic

sinh ra ngt mi trong khi ngt c vn ang c thc thi.2.2.2. Thanh ghi INT_MSKx

C 3 thanh ghi mt n che ngt (INT_MSK0, INT_MSK1, INT_MSK3) c thc quy vo thanh ghi c tn gi chung INT_MSKx. Nu c xa th mi bit trongthanh ghi INT_MSKx s ngn chn mt ngt tng ng vi bit tr thnh mt ngtch c x l (u vo ca b m ha u tin). Tuy nhin mt ngt vn c th cthng bo ngayc khi bit mt n ca n l 0. Ngha l tt c cc bit trong thanh ghiINT_CLRx u c lp vi cc bit trong thanh ghi INT_MSKx. Nu mt bit trongthanh ghi INT_MSKx c set = 1 th ngun ngt kt hp vi bit mt n ca n s sinhra mt ngt tr thnh ngt ch. V d: nu bit INT_MSK0[5] c set v c mtchn vo ra a chc nng c cu hnh sinh ra mt ngt th b iu khin ngt scho php mt ngt ca GPIO yu cu thng bo v tr thnh mt ngt ch phn hi

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ca CPU. Nu mt ngt c mc u tin cao hn c sinh ra trc s phn hi caCPU ti ngt GPIO th ngt c yu cu cao hn s l ngt ch ch khng phi l ngtGPIO. INT_MSK3[7] (ENSWINT) l mtbit khng c mt n c bit iu khinhot ng ca thanh ghi INT_CLRx. (Xem thm phn di bit thm chi tit).

2.2.3. Thanh chi INT_VCThanh ghi INT_VC thc hin 2 nhim v. Khi thanh ghi

c c th n s trv gi tr ca ngt ch c mc u tin cao nht. V d: Nu ngt GPIO v ngt I2Cang trng thi ch v thanh ghi INT_VC c c th n s c ra gi tr 1Ch (l gitr ca ngt GPIO). Tuy nhin, nu khng c ngt no ang trng thi ch th vicc thanh ghi INT_VC s tr v gi tr 00h. y l gi tr ca vector reset trong bngvector ngt. Tuy nhin l vic c c gi tr 00h t thanh ghi INT_VC khng cngha l vector ngt reset ang ch m iu ch ni ln rng chng c vector ngtno ang trng thi ch c. Thanh ghi c mc u tin cao nht c ch r bi gi trc v t thanh ghi INT_VC v n c g b khi danh sch cc ngt ch khi CPUthc hin lnh c vector ngt. Vic xa ngt ch c mc u tin cao nht xy rakhng ng b.

2.2.4. Thanh ghi CPU_FCh c bit GIE trong thanh ghi CPU_F l c nh hng ti b iu khin ngt, bit

ny l bit cho php ngt ton cc (Global Interrupt Enable). Ch khi bit ny c set thCPU mi c th thc hin mt ngt ch. Khi bit ny c xa th CPU s khng thchin mt ngt ch no c (Cn lu l mt ngt vn c thng bo v nu bit mt ncho php thi n vn tr thnh ngt ch mc d bit GIE = 0, nhng n ch c th cthc hin khi bit GIE =1). Bit GIE c gi tr mc nh = 0. c th t hoc xa bitGIE th ta s dng cc lnh logic nhAND,OR,XOR thanh ghi F vi gi tr thch hp.Tt nhin, phng php s dng y l phng php lp mt n. V d: khi ta mun

xa bit GIE th ta s dng lnh AND F,0FEh cn khi mun t bit GIE =1 th ta sdng lnh OR F,01h.

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3. Cc cng vo ra a chc nngCng vo ra a chc nng cung cp cho CPU mt giao din vi bn ngoi.

Chng i hi mt s lng ln thanh ghi cu hnh h tr cho nhiu ch hot ngvo / ra bao gm c s v tng t.

Bng 4-22: Cc thanh ghi vo ra a chc nngAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access0,xxh PRTxDR Data Register (Thanh ghi d liu) RW:000,xxh PRTxIE Bit Interrupt Enable (Bit cho php ngt) RW:000,xxh PRTxGS Global Select (La chn ton cc) RW:000,xxh PRTxDM2 Driver Mode 2 (Thanh ghi ch hot ng 2) RW:FF1,xxh PRTxDM0 Driver Mode 0 (Thanh ghi ch hot ng 0) RW:001,xxh PRTxDM1 Driver Mode 1 (Thanh ghi ch hot ng 1) RW:FF1,xxh PRTxIC0 Interrupt Control 0 (Thanh ghi iu khin ngt 0) RW:001,xxh PRTxIC1 Interrupt Control 1 (Thanh ghi iu khin ngt 1) RW:00

Ch : k t x sau du phy trong trng a ch c ngha l cc cng vo ra u c

ring bit cc thanh ghi trn. Mi mt cng th cc thanh ghi s c mt a ch ring.Nhng d hiu th ta ch xt chung cho trng hp tng qut.

Cc cng vo ra a chc nng u c rng l 8 bit/ 1 cng. Mi mt cngvo/ra bao gm 8 khi GPIO ging ht nhau. Mi mt khi GPIO u c kt ni vibit c s th t tng ng trong a ch v thanh ghi. Bi vy, nhng thanh ghi trongbng 4-22 thc s ch dnh cho mt cng (bao gm 8 khi GPIO). Trong th v trca bit s ch r l khi GPIO no trong 8 khi c iu khin vi cng vo ra.

Mi mt khi GPIO c th c s dng cho nhng kiu vo ra sau:

-Vo ra s (Vo ra s iu khin bi phn mm)-Vo ra ton cc (Vo ra cho cc khi PSoC s)-Vo ra tng t (Vo ra cho cc khi PSoC tng t)

Mi mt chn vo ra u c vi ch hot ng cng nhl kh nng to ngt.Trong khi tt c cc chn u c ni ng vo ra s th mt vi chn li khngc kt ni vi chc nng vo ra ca khi tng t hoc bus ton cc.

Vo ra sMt trong nhng chc nng hot ng c bn ca cng vo ra a chc nng l

chophp CPU gi thng tin ra ngoi chip v ly thng tin t bn ngoi vo. iu ny

c thc hin nh thanh ghi d liu cng (Port Data Register PRTxDR). Vic vitd liu vo thanh ghi PRTxDR s lu li trng thi d liu, mi bit cho mt chnGPIO. Trong ch thng (standard non-bypass) th mi chn GPIO s lp li bit dliu . Ngha l khi ta vit mt gi tr vo trong thanh ghi d liu PRTxDR th ura ca cng tng ng s c gi tr ging nhtrong thanh ghi d liu. in p thc chn ra ph thuc vo ch hot ng ca chn v ti bn ngoi c ni vo chn. (Xem cu trc ca 1 chn vo ra hiu r thm)

CPU c th c gi tr ca mt cng bng cch c gi tr ca thanh ghiPRTxDR. Khi CPU c gi tr ca PRTxDR th gi tr in p hin thi ca chn vora s c chuyn i sang gi tr logic v c tr v cho CPU. Hot ng ny s c

gi tr in p ca chn vo ra ch khng phi l c v gi tr cht ca thanh ghiPRTxDR.

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Vo ra ton cc (Global IO)Cc cng vo ra a chc nng cng c ni lin vi cc khi s thng qua cc

vo ra ton cc. Tnh nng vo ra ton cc ca mi cng c mc nh trng thitt. s dng tnh nng ny th c 2 thng s cn phi c thay i. Th nht cuhnh cho mt chn GPIO hot ng nhl mt u vo ton cc th bit la chn cngton cc cn phi c set yu cu GPIO s dng thanh ghi PRTxGS. Th hai l ch hot ng ca GPIO cn phi c a v trng thi cao tr. cu hnh cho mtchn GPIO hot ng nhl mt u ra ton cc th bit la chn cng ton cc cnphi c set ln na. Nhng trong trng hp ny th ch hot ng ca GPIO lbt k tr ch cao tr.

Vo ra tng tTn hiu tng t c th c truyn dn gia CPU v chn ca chp thng qua

chn AOUT ca khi. Chn ny c ni vi khi thng qua mt in tr (khong 300ohms). Chn vo ra a chc nng cn phi a v ch cao tr trong trng hp ny.

Cc ngt ca khi GPIO.Mi mt khi GPIO u c th c cu hnh mt cch c lp cho kh nng ngt.

Cc khi GPIO c cu hnh cho php la chn ngt cho tng chn v cng c th lachn kiu ngt ph hp. Ngha l cc khi c th sinh ra ngt khi chn mc logic cao,thp hoc khi n thay i so vi ln c trc. Cc khi u c mt u ra ngt ring(INTO), n c ni vi cc khi GPIO khc bng mt kiu ni dy loi OR.

Do tt c cc chn u c ni vi nhau theo kiu OR s dng chung mt hthng ngt GPIO. Nn nu mt ngt GPIO c chia s cho nhiu chn vo ra th trnhphc v ngt ca ngi s dng cn phi s dng vi k thut c thit k sn quyt nh xem l chn no c chn l ngun sinh ngt.

S dng mt ngt GPIO yu cu nhng bc sau:

1. t ch ngt cho khi chn GPIO.2. M bit ngt cho khi chn GPIO.3. M bit mt n ngt cho ngt GPIO.4. Xc nhn bit ngt ton cc GIE.

phm vi khi GPIO, xc nhn ng ra ngt ph thuc duy nht vo bit chophp ngt v trng thi ca chn quan h vi s la chn ch ngt. cp chip, dotrng thi t nhin ca cng ni dy OR, ngt GPIO khng phi l ngt nhy theo snhayngt nhy theo mc. Chng c th c la chn l nhy theo sn nhng nhytheo mc phi c tho b khi ng ra ngt ca cng ni dy OR.

Nu khng c ngt GPIO no ang xc nhn, th mt ngt GPIO s c sinh rabt c khi no bit cho php ngt ca mt chn GPIO c set v chn GPIO chuynsang cao hoc thp mt cch thch hp. Mt khi iu ny xy ra, ng ra ca ngtINTO s c ko xung thp xc nhn ngt GPIO (Gi nh rng cc iu kinsinh ngt ca h thng l cho php, nhl cho php ngt GPIO ton cc v cho phpngt ton cc). Lu rng cho php ngt chn c th xc nhn u ra ngt INTOngay lp tc, nu nhiu kin ch ngt sn sng xut hin chn.

Mt khi INTO c ko xung mc thp, n s tip tc gi INTO mc thp chon khi mt trong cc iu kin sau y thay i:

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- Bit cho php ngt chn c xa- in p chn chuyn i sang trng thi i lp- Trong ch thay i ngt, thanh ghi d liu c c, do thit lp mc

ngt ni ti sang trng thi i lp.

- Ch ngt b thay i do trng thi hin thi ca chn khng sinh ra ngt.Khi mt trong cc iu kin trn xy ra th u ra INTO c gii phng. Ti thi

im ny, cc chn khc (hoc chnh chn ny) c th xc nhn u ra ngt ca n,ko ng chung xung thp xc nhn mt ngt mi.

Lu rng nu mt chn ang xc nhn ng ra ngt INTO v khi mt chnkhc li xc nhn u ra ngt ca n th khi chn trc gii phng ng ra ngt ca nm chn th hai iu khin u ra ngt INTO ca n th s khng c s thay i noc pht hin ra u ra ngt INTO. Tc l s khng c ngt mi no c xc nhntrn ngt GPIO. Ch , s dng AND/OR trng thi ca chn GPIO v ca bit cho phpngt ton cc nm bt c ton b cc ngt ca cng ni dy OR trong khi GPIO.

3.1. M t cu trc ca mt chn vo ra a chc nngS khi chnh ca mt khi GPIO c minh ha trong hnh 4 -3. Lu rng

mt vi chn khng c cc chc nng nhhnh v, ph thuc vo kt ni bn trong.

Hnh 4 3 : S mt khi GPIO

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Hnh 4 - 4: S khi ch ngt ca GPIO

3.2. Cc thanh ghi ca GPIOi vi mt khi GPIO c la chn, nhng thannh ghi c lp c nh

a ch nhtrong bng 4 - 23. Trong phn tn ca thanh ghi, k hiu x l s th tca cng. c cu hnh theo cp chp (x=0 ti 7). DA[1:0] c quy vo 2 trng snh nht ca a ch thanh ghi.

Bng 4-23: a ch bit ca thanh ghi bn trong

XOI DA[1:0] Register Reset to: (Name) Function0 00b PRTxDR 0 DIN Data0 01b PRTxIE 0 IE Interrupt Enable

0 10b PRTxGS 0 BYP Global Select0 11b PRTxDM2 1 DM2 Driver Mode, Bit 21 00b PRTxDM0 0 DM0 Drive Mode, Bit 01 01b PRTxDM1 1 DM1 Driver Mode, Bit 11 10b PRTxIC0 0 IM0 Intrpt. Mask, Bit 01 11b PRTxIC1 0 IM1 Intrpt. Mask, Bit 1

3.2.1. Thanh ghi PRTxDRGhi d liu vo 1 bit trong thanh ghi PRTxDR s lm cho trng thi u ra ca

chn tng ng mc cao (DIN=1) hoc mc thp (DIN=0). Tr khi ch bypassc la chn (hoc I2C Enable =1 hay thanh ghi la chn ton cc c vit mc cao).

Vic c gi tr ca PRTxDR s tr v gi tr thc trng thi ca chn, cquan st bi b m u vo. Gi tr c th khng ging vi gi tr mong mun u ra nu nhti c ni vi chn qu ln.

3.2.2. Thanh ghi PRTxIEThanh ghi PRTxIE c dng m v ng vic cho php ngt ni ti ti mt

khi GPIO. Gi tr 1 s cho php ngt u ra INTO v gi tr 0 s khng cho phpngt u ra INTO do n c th trng thi cao tr.

3.2.3. Thanh ghi PRTxGSThanh ghi PRTxGS

c s dng la chn khi cho s kt ni ti u vohoc u ra ton cc. Vic vit gi tr logic cao vo thanh ghi ny s cho php globalbypass. Nu ch cng ra l cao tr th chn c la chn cho u vo ton cc.

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Nu ch cng ra khc ch cao tr th chn c la chn l u ra ton cc,b qua gi tr ca thanh ghi d liu. (gi s I2C enable = 0).

Nu thanh ghi c xa v khng th chc nng vo ra ton cc ca chn b kha

3.2.4. Thanh ghi PRTxDMxC 8 ch iu khin cho mi mt chn ca cng. Ba bit ch c s dng

la chn mt trong 8 ch ni trn. Ba bit ch c phn chia trong ba thanhghi khc nhau. (PRTxDM0, PRTxDM1,PRTxDM2). V tr tng ng ca bit trong bathanh ghi s tng ng vi v tr chn ra ca cng. (V d ba bit iu khin cho chnP2[1] s l bit PRT2DM0[1], PRT2DM1[1], PRT2DM2[2]). Tuy rng ba bit ny cphn chia trong ba thanh ghi khc nhau nhng chng li hay c s dng cng nhautheo cc cp bit tng ng. V d xt ch cho chn ra P2[1] th ta quan tm ncc bit trong DM2,DM1,DM0 hay DM[2:0]. Bng 4-22 s cho ta ci nhn tng quan vs phn chia ny.

Bng 4 - 24: Cc ch iu khin chn ra ca chp

Ch DM[2:0] Trng thi ca chn M t000b Resistive pull down Khe mc cao, in tr treo mc thp001b Strong driver Ch khe c mc cao v thp010b High Impedance Tr khng cao c mc cao v thp, cho php u vo s011b Resistive pull up Khe mc thp, in tr treo mc cao.100b Open drain high Chm, khe mc cao, tr khng cao mc thp101b Slow strong driver Ch chm, khe mc thp v cao.110b High Impedance, analog Ch cao tr cho c cao v thp, u vo s b kha,111b Open drain low Ch chm, khe mc thp, cao tr mc cao.

la chn u vo tng t, ch iu khin cng ra cn phi c chn lmt trong cc ch cao tr, c th l 010b hoc 110b. Ch 110b c mt u iml b m u vo khi s b kha, v th khng c dng in crowbar chy quangay c khi u vo tng t khng gn vi ng ngun. Khi u vo s c cnn trong nhng chn c dng nhu vo tng t th nn s dng ch 010b. Khich 110b c s dng th chn s lun c CPU c nhl mt gi tr khng vchn s khng th sinh ra c mt ngt hu ch. (Khng hon ton yu cu mtch cao tr cn phi c la chn khi hot ng vi tn hiu tng t).

Vi u vo ton cc s dng cng vi vo ra tng t th ch iu khin cn phic t l 010b.

Khi vo ra a chc nng GPIO cung cp mt ch cao tr mc nh. iu nyt c nh vo nh hng ca vic reset trng thi ca tt c cc thanh ghi

PRTxDM1 v PRTxDM2 v FFh.Ch iu khin resistive t mt in tr ni tip vi u ra bn trong, cho u

ra mc thp (ch 000b) hoc u ra mc cao (ch 011b). Ch khe (strong)001b cung cp mt sn ln nhanh nht v ch 101b cng cung cp mt sn xungnhanh nht. Ch open drain cng c dng iu khin tc sn xung. Cc ch cho php chc nng cc mng ng nh l ch I2C 111b. (mc d tc sn thp vn khng chm gp c ch I2C nhanh c nh ngha).

3.2.5. Thanh ghi PRTxICxCh ngt ca tng chn c quyt nh bi cc bt trong hai thanh ghi

PRTxIC0 v PRTxIC1. Chng c quy vo l IM0 v IM1 hay IM[1:0].

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C 4 ch ngt c th c cho chn ca cng. Hai bit ch c yu cu lachn cc ch ni trn v tng cp bit ny c phn chia trong 2 thanh ghi khcnhau (PRTxIC0 v PRTxIC1). V tr ca bit l tng ng vi v tr ca chn. V dchn 2 ca cng 1 s tng ng vi bit 2 trong c hai thanh ghi PRT1IC0 v PRT1IC1.Tng cp bit ny c xem nhl mt nhm. Bng sau s cho ta thy r hn v ccch ngt trong GPIO.

Bng 4 - 25: Ch ngt ca GPIO

Ch ngt IM[1:0] M t00b V hiu ha ngt, khng xc nhn u ra INTO01b Xc nhn ngt khi chn mc thp10b Xc nhn ngt khi chn mc cao11b Xc nhn ngt khi c s thay i trng thi logic ca chn

Ch 00b s v hiu ha ngt ca chn, k c khi bit cho php ngt GPIO l 1 (cathanh ghi PRTxIE).

Ch 01b c tc dng l khi GPIO s xc nhn mt ng ngt (INTO) khi in

p ca chn mc thp. Bit cho php

ng ngt ca khi GPIO

c t ln mc cao.Ch 10b c tc dng l khi GPIO s xc nhn mt ng ngt (INTO) khi in

p ca chn mc cao. Bit cho php ng ngt ca khi GPIO c t ln mc cao.

Ch 11b c tc dng l khi GPIO s xc nhn mt ng ngt (INTO) khiin p ca chn i lp so vi gi tr c trc . Ch ny thay i theo hai ch trn, ty thuc vo gi tr m trc n c c t cng trong qu trnh cthanh ghi d liu cng (PRTxDR). Nu trc n c gi tr 0 t GPIO th GPIO schuyn sang ngt mc cao. Cn nu gi tr n c c trc l 1 th GPIO schuyn sang ngt mc thp.

Gi tr tr

c ca chn l 0 Gi tr tr

c ca chn l 1

GPIO pin interrupt enable set : cho php ngt ca chn GPIO

Interrupt occus : xy ra ngt

Pin State Waveform : dng xung chn

Hnh 4 - 5: Ch ngt 11b ca GPIO

Hnh 4-5 gi thit rng bit cho php ngt ton cc GIE = 1, bit mt n ngt c t = 1, ch ngt ca GPIO l 11b. S thay i ch ngt khc vi cc ch khc, da vo gi tr m n c c trc ca chn quyt nh nu nhtrngthi ca chn thay i. V th, cng cha chn GPIO quan tm cn phi c c trongsut qu trnh phc v ngt. Nu cng khng c c th ch ngt s ch hot ng ch cao nu gi tr trc l 0 v ch mc thp nu gi tr trc l 1.

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4.Cc b to dao ng4.1. B to dao ng chnh bn trong (IMO - Internal Main Oscillator)

Bng 4 - 26: Thanh ghi ca b IMO

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

1,E8h IMO_TR Trim [7:0] W:00

u ra ca b IMO c 2 loi, mt loi l SYSCLK c th l ngun xung nhp24MHz bn trong hay ngun xung nhp bn ngoi, mt loi l SYSCLK2X c tn sxung nhp gp i SYSCLK. Khi khng c u vo chnh xc cao t b dao ngthch anh 32 kHz th chnh xc ca ngun xung nhp 24/48MHz bn trong s l +/-2.5% i vi di nhit v hai mc in p hot ng (3.3 V +/-0.3V v 5.0 V +/-5%).Khng cn thm mt thnh phn bn ngoi no t c mc chnh xc ny.

C mt la chn cht pha ca b dao ng bn trong ny sang b dao ngthch anh bn ngoi. V th vic la chn thch anh v chnh xc ca n s quytnh tnh chnh xc ca b dao ng bn ngoi. B dao ng thch anh bn ngoi cnphi c n nh trc khi cht tn s dao ng ca b dao ng chnh bn trong vongun xung nhp ny.

B IMO c th c kha khi s dng ngun xung nhp bn ngoi. Bi vy, mchnhn i tn s (SYSCLK2X) c th c ngt tit kim nng lng cho h thng.Lu rng khi s dng ngun xung nhp bn ngoi, nu nhSYSCLK2X c cn nth IMO khng th b kha.

4.1.1. Thanh ghi IMO_TR (Internal Main Oscillator Trim Register)Gi tr mc nh ca tn s chp cho ch hot ng 5 vn c ti vo thanh

ghi IMO_TR ti thi im khi ng. B IMO s hot ng vi sai lch ring trongdi in p t 4.75 n 5.25 vn khi gi nguyn gi tr ca thanh ghi ny. Nu nhchphotng in p thp, m ca ngi s dng cn phi thay i ni dung ca thanhghi ny. hot ng vi gii in p 3.0V +/-0.3V th phi thc hin vi mt lnhc bng ti SROM (Supervisor ROM), n c th cung cp mt gi tr ct tn s choch hot ng ny. hot ng gia hai gii in p, m ca ngi s dng c tht ng thm vo gi tr tt nht s dng hai gi tr ct tn s c sn ca nh sn xut.

Bit 7- 0: Trim.Nhng bit ny lu gi gi tr ct tn s ca b IMO, gi tr ca thanhghi cng ln th tn s dao ng ca b IMO cng ln.

4.2. B to dao ng tc thp ni ti (ILO - Internal Low Speed Oscillator)Bng 4 - 27: Thanh ghi ILO

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W:00

ILO l mt b pht xung nhp ni ti tc thp 32 kHz. N c kh nng sinh rangt nh thc ch ng v reset li ng h Watchdog. B to dao ng nycng c s dng nhl mt ngun xung nhp cho cc khi s.

B ILO c th hot ng ba ch : ch bnh thng, ch ngun gimhoc ch tt (khng s dng). Ch bnh thng tiu th nhiu nng lng hncho chnh xc ca tn s xung nhp. Ch ngun gim lun lun c dng khi

chp ang trng thi ngun gim (ngh) v c th c la chn khi chp ang hotng, nhng n s pht ra mt ngun xung nhp c chnh xc km hn so vi ch bnh thng.

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4.2.1. Thanh ghi ILO_TRThanh ghi ny t iu chnh cho ILO. Gi tr mc nh c t vo nhng

bit trim ca thanh ghi trong qu trnh khi ng. N da vo mc nh ca nh snxut. Nh sn xut khuyn co ngi s dng khng c thay i gi tr cathanh ghi ny.

Bit 7 v 6: dnh (khng dng n)Bit 5 v 4: Bias Trim. Hai bit c s dng t dng in bias trong ngun dngPTAT. Bit 5 c nghch o v th m ch bias trung bnh c la chn khi c haibit = 0. Dng in bias c t theo bng sau.

Bng 4 - 28: Dng in bias trong PTAT

Bias Current Bit 5 Bit 4Medium Bias 0 0Maximum Bias 0 1Minimum Bias 1 0Not Needed * 1 1

* Cao hn khong 15% so vi ch Minimum Bias.

Bit 3 ti bit 0: Freq Trim. Bn bit c s dng ct tn s. Bit 0 l bit c trng snh nht, bit 3 l bit c trng s ln nht. Bit 3 c nghch o bn trong thanh ghi,bi vy, m 8h s lm cho tt c cc ngun dng tt (tn s = 0 kHz). Mt m 0h s btngun dng c trng s ln nht (tn s = trung bnh). Mt m 7h s bt tt c ccngun dng (tn s = ln nht).

4.3. B to dao ng thch anh 32 kHz (ECO)Mch to dao ng thch anh 32 kHz cho php ngi s dng thay th b to dao

ng bn trong (ILO) vi mt b to dao ng bn ngoi vi chnh xc cao hn, githnh thp v nng lng tiu hao t.

Bng 4 - 29: Cc thanh ghi ca b dao ng thch anh

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed [2:0] RW: 001,EBh ECO_TR PSSDC[1:0] W: 00x,FEh CPU_SCR1 IRAMDIS RW: 00

Mch to dao ng thch anh s dng mt thch anh gi r v 2 t nh l thnhphn bn ngoi. Tt c cc thnh phn khc u nm trong chp PSoC. B to dao ngthch anh c th c cu hnh cung cp mt tham chiu n b to dao ng bn

trong (IMO) trong ch PLL (Phase Lock Loop) to ra ngun xung nhp h thng24 MHz vi chnh xc cao hn.

Chn XTALIn v XTALOut h tr kt ni vi thch anh 32.768 kHz. c ths dng b dao ng thch anh bn ngoi th bit 7 ca thanh ghi iu khin b daong OSC_CR0 cn phi c t = 1 (mc nh l 0). Thnh phn bn ngoi ch lmt thch anh v 2 t nh ni vi Vcc. (xem hnh v). Chuyn i gia b dao ngngoi v b dao ng trong c th lm cho bus h thng khng ng b.

Trong tin trnh kch hot b ECO, n cn mt khong thi gian tch ri trckhi c s dng nhl mt ngun xung nhp 32 kHz. Khong thi gian tch ri nyc b xung vo phn cng bng Sleep Timer. Vi chng trnh (Firmware - phnmm c np c nh trong chp) cn phi c thit lp thi gian ngh khong 1 giy(khong thi gian ln nht ca ECO), v sau cho php ECO bng thanh ghi

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OSC_CR0. Ti thi gian ngh 1 giy (ngt ca Sleep Timer), chuyn mch sang ECOc to ra bi phncng. Nu sau ECO khng hot ng th ILO s c kchhot li v chuyn mch s chuyn li vi ILO ngay lp tc.

Cc bc ca vi chng trnh cn phi thc hin trong vic chuyn i gia b phtxung nhp chm ni ti sang b pht xung nhp thch anh 32kHz nhsau:

1.

Ti thi im reset, chip bt u hot ng v n s dng b pht xung nhpchm ni ti.

2. La chn khong thi gian ngh 1 giy bng bit[4:3] trong thanh ghi OSC_CROnhl khong thi gian n nh b pht xung nhp.

3. Cho php b php xung nhp thch anh 32kHz bng cch t bit 7 trong thanhghi OSC_CR0 ln 1.

4. B pht xung nhp thch anh 32kHz tr thnh ngun xung nhp c la chnti im kt thc ca mt giy ngh ni trn. Khong thi gian ngh cho php bpht xung nhp c thi gian n nh trc khi n tr thnh ngun cung cp

xung nhp. Ngt Sleep khng

c m trong khi vic chuyn i ang din ra.Reset li Sleep Timer m bo khong thi gian ngh cn thit (nu nhnkhng giao tip vi bt c mt h thng thi gian thc no). Lu rng b phtxung nhp tc thp vn tip tc chy cho n khi chuyn hn sang b phtxung nhp ngoi nh vo ngt ca Sleep Timer.

5. Mt li khuyn l nn i ht mt giy b pht xung nhp n nh ri michophp ch PLL cht tn s b pht xung nhp ni ti vi tn s ca bpht xung nhp thch anh 32kHz.

Lu :

a.

B pht xung nhp ni ti s

c chuyn tr li ngay lp tc bng cch vit gitr 0 vo bit iu khin [32k Select].

b. Nu thit lp thch hp c la chn trong PSoC Designer th nhng bc trns c thc hin t ng trong file boot.asm

c. Chuyn i phm vi hai b pht xung nhp c th lm cho xung nhp bus hthng khng ng b. Nhng chc nng yu cu xung nhp 32k nn m sau khi chuyn i xong.

4.4. Vng cht pha - Phase Locked Loop (PLL)Bng 4 - 30: Thanh ghi ca Phase Locked Loop

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed [2:0] RW:001,E2h OSC_CR2 PLLGAIN EXTCLKEN IMODIS SYSCCKX2DIS RW:00

Chc nng PLL s pht ra xung nhp h thng vi chnh xc ca thch anh. Nc thit k cung cp mt b pht xung nhp 23.986 MHz khi s dng vi thchanh 32.768 kHz

Mc d PLL n theo chnh xc ca thch anh. N vn yu cu thi gian cht vo tn s chp khi khi ng ln u. di ca thi gian ph thuc voPLLGAIN c iu khin bi bit 7 trong thanh OSC_CR2. Nu bit ny c gi mc thp th thi gian cht s nh hn 10ms. Nu bit ny c gi mc cao th thigian cht s ln hn 50ms. Sau khi vic cht hon tt th bit ny c khuyn co l

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nn gi mc cao gim s bt n u ra. Nu c th vt qua c thi gian chtdi hn th bit PLLGAIN c th c gi mc cao trong sut thi gian cn li.

Sau khi b pht xung nhp thach anh bn ngoi c la chn v hot ng thnhng th tc sau y s cho php ch PLL v cho php cht tn s thch hp

a. Chn tn s CPU l 3 MHz hoc nh hnb. M ch PLLc. i 10 ms hay 50ms, ph thuc vo bit 7 trong thanh ghi OSC_CR2d. t tn s CPU ln cao hn nu mun. lm vic ny th ta thay i

gi tr cc bit CPU Speed trong thanh ghi OSC_CR0. Tn s ca CPU sc thay i ngay lp tc khi nhng bit ny c set.

Nu nhng thit lp thch hp c la chn trong PSoC Designer th nhng bctrn s c thc hin t ng trong file boot.asm

4.5. Sleep and WatchdogBng 4 - 31: Nhng thanh ghi ca Sleep v Watchdog.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access0,E0h INT_MSK0 VC3 Sleep GPIO Analog3 Analog2 Analog1 Analog0 V Monitor RW:000,E3h RES_WDT WDSL_Clear[7:0] W:00x,FEh CPU_SCR1 IRAMDIS RW:001,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed [2:0] RW:001,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W:001,EBh ECO_TR PSSDC[1:0] W:00x,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP RW:XX

Ch dn:X: Gi tr sau khi reset ngun l khng rx, K t x ng trc du phy trong trng a ch ch r rng thanh ghi ny c th c

truy nhp m khng cn bit l dy thanh ghi no ang c s dngMc ch ca ch ngh l gim nng lng tiu th trung bnh ca h thng

n mc c th. H thng i vo ch ngh c khi to v iu khin bi vi chngtrnh. Trong trng thi ny, CPU c dng li mt bin gii lnh v b pht xungnhp 24/48 MHz, modun b nh Flash v in p tham chiu band-gap gim nnglng tiu th. Khi PSoC duy nht cn hot ng l b pht xung nhp 32 kHz (bnngoi hoc bn trong). Khi PSoC bm gi t s la chn xung nhp 32kHz v mchtheo di in p cung cp.

Cc khi PSoC tng t c hai ch gim ngun c iu khin bi vi chng

trnh v c lp vi trng thi ngh. Khi continuous time analog c th vn hot ng,t khi chng khng yu cu ngun xung nhp. Tuy nhin, khi analog SC s khnghot ng t lc ngun xung nhp ni ti cung cp cho chng ngng hot ng.

H thng c th ch c nh thc khi ch ngh bng mt yu cu ngt hocs kin reset h thng. ng h ngh cung cp nhng ngt nh k cho php hthng thc dy, thm d ngoi vi, thc hin chc nng thi gian thc v sau li ivo ch ngh ln na. Ngt ca chn GPIO, ngt theo di ngun, ngt ca ct khitng t, v ngun xung nhp ngoi hay xung nhp 32k bn trong c s dng lmmu ng b ha nhng ngt c th c dng nh thc h thng dy.

Mch nh thi Watchdog c thit k sinh ra mt ngt cng ti chp sau mt

khong thi gian c lp trnh trc, tr khi n c phc v mt cch nh k trongvi chng trnh. Chc nng ny s reset h thng nu nhCPU hot ng sai. N cngc th reset nu nhh thng b treo.

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Mt khi b nh thi Watchdog c m th n ch c th b ng t mt s kinreset bn ngoi (XRES) hay mt s kin reset ngun (POR). Mt reset ca b nh thiWatchdog s vn watchdog hot ng. Bi vy, nu watchdog c s dng trongmt ng dng th tt c cc m (bao gm c m khi u) cn phi c vit nhth lwatchdog ang c m.

4.5.1.M t cu trcNhng thnh phn ca chp cn phi c khi hot ng ch ngh v watchdog

l la chn ngun xung nhp 32kHz (bn ngoi hoc bn trong), vi b nh thi sleep,bit sleep trong thanh ghi CPU_SCR0, mch sleep, mch lm ti band gap ( lm tiin p tham chiu mt cch nh k), v b nh thi watchdog.

4.5.1.1. La chn ngun xung nhp 32kHzMc nh ngun xung nhp 32kHz c ly t b pht xung nhp ni ti tc

thp (ILO). C th la chn ngun xung nhp ly t b pht xung nhp ngoi (ECO).Vic la chn ny c thc hin bng cch thay i gi tr bit 7 trong thanh ghiOSC_CR0. La chn ECO l ngun xung nhp 32kHz s cho php b nh thi sleep

v ngt ca n dng trong ng dng thi gian thc. Cho d ngun xung nhp no cla chn th ngun xung nhp 32kHz cng gi mt v tr then cht trong chc nngngh. N chy lin tc v thng xuyn nh thc h thng dy, n cng nh k lmti li in p band gap trong sut qu trnh ngh.

4.5.1.2. B nh thi nghB nh thi ngh l mt b m tin 15 bit bng ngun xung nhp 32kHz la

chn, c th l ILO hoc ECO. B nh thi ny lun lun c hot ng. Nu mt bICE hot ng ch g ri v bit Stop trong thanh ghi OSC_CR0 c set th bnh thi ngh s b v hiu ha. V th ngi s dng s khng c reset thng xuyn

ca watchdog khi mt im ngt

c tm ra trong tr

ng g ri.Nu ngt ca b nh thi ngh c cho php, mt ngt nh k ti CPU c

sinh ra da trn khong thi gian ngh la chn trong thanh ghi OSC_CR0. V mtchc nng th b nh thi sleep khng cn thit phi trc tip kt hp vi trng thingh. N c th c dng nhl mt ngt ca b nh thi a mc ch cho d hthng c ang trng thi ngh hay khng.

Trng thi reset ca b nh thi sleep l mt gi tr m n 0. C hai cch reset b nh thi Sleep. Mt l bt c reset phn cng no, v d nh reset ngun(POR), reset ngoi hay watchdog reset. Hai l reset b nh thi Sleep bng vi chngtrnh. Lnh vit gi tr 38h vo thanh ghi RES_WDT s reset b nh thi Sleep (lu :

bt c lnh ghi gi tr vo thanh ghi RES_WDT u reset li b nh thi watchdog).Xa b nh thi Sleep c th c lm bt c lc no ng b ha hot ng cab nh thi Sleep vi x l ca CPU. Mt v d hay ca vic ny l sau khi resetngun (POR), v d CPU c gi chm ch in p tng , cng rt quan trng.Hn na, mt phn quan trng ca phn m u chng trnh c th c yu cu.Trong khi th b nh thi Sleep s bt u m ngay sau khi POR v n s m nmt gi tr no ti thi im m ca ngi s dng c thi hnh. Trong trng hpny nn xa b nh thi Sleep trc khi cho php ngt khi u ca b nh thiSleep. chc chn rng khong ngh u tin s bng khong thi gian t trc.

4.5.1.3. Bit SleepCh ngh c khi u trong vi chng trnh bng cch thit lp bit Sleep

trong thanh ghi iu khin h thng (CPU_SCR0). nh thc h thng th bit ny

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cn phi c xa ng thi vi bt c mt ngt c php no. Tuy nhin, c hai tnhnng c bit ca bit ny m bo hot ng ca Sleep ng cch. Th nht, lnh ghi t bit ny ln 1 c ngn chn, nu mt ngt m nhim gii hn lnh . Thhai, c mt kha lin ng m bo rng mt khi n c set, bit sleep c thkhng b xa bi mt ngt n tr khi l mch ngh hon thnh xong mt chui skin ngh v tn hiu gim nng lng ca h thng c xc nhn. iu ny s ngn

chn mch sleep khi ngt trong gia tin trnh h thng ang trng thi gim nnglng v c l s h thng mt trng thi khng xc nh.

4.5.2.Lu khi s dng ch ngh trong ng dngNhng phn sau y s nu vi lu v ch ngh v lin h ca n vi vi

chng trnh v phn mm ng dng.

a. Nu mt ngt ang ch, c cho php v c lp lch thi hnh ti lnh cuicng sau khi vit vo bit sleep th h thng s khng i vo ch ngh. Lnh svn c thi hnh, nhng n s khng th set c bit sleep trong thanh ghiCPU_SCR0. Thay vo th lnh s c thi hnh v tc ng ca lnh ngh b

b qua.b. Bit cho php ngt ton cc khng cn thit phi c m nh thc h thng

khi trng thi ngh. Cc bit cho php ngt c lp vi nhau v c kh nngc thit lp trong thanh ghi mt n che ngt. Nu bit cho php ngt ton cckhng c set th CPU s khng thc hin trnh phc v ngt lin quan ti ngt.Tuy nhin, h thng s b nh thc v tip tc thi hnh cc lnh ti thiim m n i vo trng thi ngh. Trong trng hp ny th ngi s dng phixa ngt ch mt cch th cng, hoc c th m bit cho php ngt ton cc risau cho CPU thi hnh trnh phc v ngt. Nu mt ngt ch khng cxa th n s vn tip tc xc nhn, v mc d bit sleep c ghi v chui s

kin ngh c thi hnh, ngay khi chp i vo ch ngh, bit sleep s b xabi ngt ch v h thng s thot khi ch ngh.

c. Khi thc dy, lnh nm ngay sau lnh ngh s c thi hnh trc trnh phc vngt (nu cho php). Lnh nm ngay sau lnh ngh c dng li trc khi hthng i vo ch ngh. Bi vy, khi mt ngt xy ra v nh thc h thngdy th lnh ngay sau lnh ngh s c thi hnh v khi th trnh phc v ngtcng c thi hnh. (Nu bit cho php ngt ton cc c set, thc hin lnh sch tip tc ti ni m n b d trc khi i vo ch ngh.)

d. Nu ch PLL c m th tn s ca CPU cn phi c gim xung 3MHztrc khi i vo ch ngh. Khuyn co l nn i 10ms sau khi h thng thcdy m bo tn s hot ng bnh thng ca CPU c khi phc.

e. Nng lng ca phn tng t cn phi c tt bng vi chng trnh trc khii vo ch ngh. Ch ngh ca h thng s khng iu khin mng t ngt. Cnhiu cch iu khin ngun nng lng c lp cho mi khi tng tv nhiu cch iu khin ngun nng lng chnh trong khi tham chiu. Cchiu khin ngun nng lng cn phi c thc hin bi vi chng trnh.

f. Nu bit cho php ngt ton cc b ng, n ch c th c m mt cch an tonsau lnh vit vo bit sleep. N thng gy rc ri khi c mt ngt lnh cuicng ngay trc lnh ghi vo bit sleep. iu ny c ngha l ti thi im quay

v t ngt, lnh ngh s c thi hnh v c th b qua bt c mt s chun bno ca vi chng trnh cn thit phi thc hin theo trnh t i vo ch ngh. ngn chn iu ny th cn phi cm cc ngt trc khi i vo ch

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ngh. Sau khi chun b cho ch ngh, cho php ngt ton cc v vit vo bitsleep vi hai lnh lin tip sau:

and f,~01h // v hiu ha ngt ton cc

(chun b cho ch ngh, c th c nhiu lnh)

or f,01h // cho php ngt ton cc

mov reg[ffh],08h // a h thng vo ch ngh.

Do khong thi gian ca lnh cho php ngt ton cc l rt nh nn kh cth c mt ngt s xy ra ngay sau lnh trn. Ngt sm nht c th xy ra l saulnh tip theo (l lnh a h thng vo ch ngh) c thi hnh. Bi vy,nu mt ngt ang ch v lnh ngh c thi hnh nhc m t trong mc (a)th lnh ngh s c b qua. Lnh u tin c thi hnh sau trnh phc v ngts l lnh nm ngay sau lnh ngh.

4.5.2.1. nh thc h thng.Mt khi h thng trng thi ngh th s kin duy nht c th nh thc hthng l mt ngt. Bit cho php ngt ton cc trong thanh ghi CPU_F khng cn thit

phi c set. Bt c mt ngt khng b che no u c th nh thc h thng dy.Mt la chn cho CPU l c thi hnh ngt hay khng sau khi h thng b nh thc.

Dy s kin nh thc h thng c ng b vi xung nhp 32kHz vi mc chto tr khi khi ng li, cho php Module b nh Flash c thi gian khiphc li mc nng lng hot ng trc khi CPU pht ra lnh c u tin. Mt l dokhc cho s tr l cho php IMO, Bandgap, mch LVD /POR c thi gian nnh trc khi i vo hot ng. Dy s kin nh thc h thng c ch ra trongHnh 4-6 v c m t nhsau:

a. Khi mt ngt nh thc xy ra v c ng b ha vi sn m ca xung nhp32kHz.b. Ti sn dng tip theo ca ngun xung nhp, tn hiu gim ngun h thng

c o li. Module b nh Flash, IMO v mch bandgap c cp nng lng trng thi hot ng bnh thng.

c. Ti sn dng tip theo ca xung nhp 32kHz, gi tr chnh xc r rng caPOR v LVD n nh v c ly mu.

d. Ti sn m tip theo ca xung nhp 32kHz ( sau khong 15 us), tn hiu BRQc o li nh mch logic ngh. Trn sn tip theo ca CPUCKL, tn hiu

BRA c o li bi CPU v lnh thi hnh tip tc. Thi gian nh thc hthng l t 75 n 105 us.

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Hnh 4-6: Biu dy cc s kin nh thc h thng

4.5.2.2. Lm ti bandgapTrong sut qu trnh hot ng bnh thng, mch bandgap cung cp cho h

thng mt in p tham chiu (VREF) s dng cho cc khi tng t, b nh Flash

v mch pht hin in p thp (LVD). Bnh th

ng u ra ca bandgap

c ni trctip n tn hiu VREF. Tuy nhin, trong trng thi ng th khi sinh in p thamchiu v mch pht hin in p thp hon ton c gim nng lng. Khi bandgapv LVD c m li nh k trong sut qu trnh ngh theo di in p thp.

iu ny c thc hin bng cch bt bandgap mt cch nh k, cho mtkhong thi gian khi ng bng nguyn mt xung nhp 32kHz, v kt ni n tiVREF lm ti li in p tham chiu trong nguyn mt xung nhp 32kHz tip theonhc ch trong Hnh 4-7.

Trong khong thi gian xung nhp th hai ca chu k lm ti, mch LVD ccho php n nh trong sut khong thi gian xung nhp 32kHz mc cao. Trong

khong thi gian xng nhp th hai mc thp, ngt LVD c cho php xy ra.

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- Bandgap is turn on, but not yet connected to VREF: Bandgap c bt, nhngvn cha c ni vi VREF

- Bandgap output is connected to VREF. Voltage is refreshed: u ra bandgapc ni vi VREF

- Bandgap is powered down until next refresh cycle: Bandgap c gim nguncho n ch k lm ti tip theo.

- VREF is slowly leaking to ground: VREF b r r in p xung t mt cchchm chp.- Low voltage monitors are active during CLK32 low: B theo di in p thp

c kch hot trong xut qu trnh CLK32 mc thp.

Hnh 4-7: Hot ng lm ti bandgap

Tc lm ti t l vi tc xung nhp 32kHz v c iu khin bi chu knhim v ngh ca h thng. (Power System Sleep Duty Cycle). PSSDC, bit[7:6] cathanh ghi ECO_TR. Bng 4 - 32 lit k mt s gi tr c th la chn. Thit lp mc

nh (128 ln m cho b nh thi ngh) thch hp vi nhiu ng dng, dng in tiutn trung bnh di 5uA.

Bng 4-32: Bng la chn chu k nhim v ngh ca h thng

PSSDC S m ca b nh thi ngh Thi gian tng ng00b (mc nh) 256 8 ms

01b 1024 31.2 ms10b 64 2 ms11b 16 500 us

4.5.2.3. B nh thi Watchdog (WDT)Ti thi im khi ng chp, WDT khi u l b ng. Bit PORS trong thanh

ghi iu khin h thng s iu khin m WDT. Ti lc khi ng bit PORS khi uc t l 1, n ch r rng hoc s kin POR hay XRES xy ra. WDT c mbng cch xa bit PORS. Mt khi bit ny c xa v b nh thi watchdog i vohot ng th n s khng th b ng (v bit PORS khng th c set ln 1 bi vichng trnh, n ch c th b xa). Cch duy nht v hiu ha chc nng watchdogsau khi n c m l thng qua POR hay XRES. Mc d WDT b v hiu ha tlc POR hay XRES cho n ht m khi u, nhng ton b m chng trnh nn cvit nhth l n ang cm. (WDT cn phi c xa mt cch nh k). L do lv trong m khi u sau s kin WDR (watchdog reset), b nh thi watchdog cm v tt c cc m chng trnh cn phi bit iu ny.

B nh thi watchdog bng ba ln m u ra ngt ca b nh thi ngh v vvy, khong thi gian watchdog bng 3 ln khong thi gian la chn ca b nh thingh. Khi ngt ca b nh thi ngh c xc nhn, b nh thi watchdog bt utng. Khi b m m n ba, gi tr m cui c xc nhn. Gi tr m cui nyc ghi nhn bi xung nhp 32kHz. Bi vy, tn hiu reset Watchdog s chuyn lnmc cao sau xung nhp 32kHz tip theo v c gi xc nhn trong mt chu k. BFlip-Flop ghi nhn gi tr m cui ca WDT khng c reset bi tn hiu reset WDTkhi n c xc nhn, nhng li c reset bi bt c mt reset no khc.

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Hnh 4 - 8: Watchdog reset

Mt khi c cho php th WDT cn phi c xa mt cch nh k bi vichng trnh. iu ny c thc hin vi mt lnh vit vo thanh ghi RES_WDT.Lnh vit ny l mt gi tr khng ph thuc, v th bt c lnh ghi no u xa bnh thi watchdog. Nu v mt l do no m vi chng trnh khng xa watchdogtrong khong thi gian la chn th mch WDT s sinh ra mt WDR (watchdog reset)ti chp. WDR tng ng vi nhng reset khc. Tt c cc thanh ghi u c av gi tr mc nh. Mt iu quan trng cn phi nh v reset Watchdog l n l khiu RAM c th b ng (IRAM trong thanh ghi CPU_SCR1). Trong trng hp ny,thnh phn ca SRAM khng b nh hng, v th khi WDR xy ra th cc bin ca

ch

ng trnh tn ti xuyn qua s kin reset ny.Trong ng dng thc hnh th phi bit rng khong thi gian ca b nh thiWatchdog nm vo khong 2 n 3 ln khong thi gian ca b nh thi ngh. Cchduy nht m bo khong thi gian watchdog bng 3 ln khong thi gian cab nh thi ngh l xa b nh thi ngh khi xa thanh ghi WDT. Nhng iu ny lkhng th trong nhng ng dng s dng b nh thi ngh nh l mt ng h thigian thc. Trong trng hp ny th vi chng trnh xa thanh ghi WDT m khng xab nh thi ngh, iu ny c th xy ra ti bt c im no trong khong thi gianngh. Nu n xy ra gn gi tr cui ca b nh thi ngh th kt qu l khong thigian WDT s ch ln hn 2 ln khong thi gian ngh.

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Chng 5: H thng khi PSoC S

Cu trc ca h thng s.

Hnh v di y m t cu trc cao nht ca h thng s trong PSoC. Mi thnh

phn u c m t chi tit trong phn ny.

Hnh 5 - 1: S khi m t cu trc cc khi s trong PSoC

Cc thanh ghi s

Bng sau y lit k ton b cc thanh ghi s ca h thng s trong PSoC

Bng 5 - 1: Bng thng k cc thanh ghi s

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AccessGLOBAL DIGITAL INTERCONNECT (GDI) REGISTERS

1,D0h GDI_O_IN GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW : 001,D1h GDI_E_IN GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW : 001,D2h GDI_O_OU GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 001,D3h GDI_E_OU GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 RW : 00

DIGITAL ROW REGISTERSx,B0h RDI0RI RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00x,B1h RDI0SYN RI3SYN RI2SYN RI1SYN RI0SYN RW : 00x,B2h RDI0IS BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00x,B3h RDI0LT0 LUT1[3:0] LUT0[3:0] RW : 00x,B4h RDI0LT1 LUT3[3:0] LUT2[3:0] RW : 00x,B5h RDI0RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00x,B6h RDI0RO1 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00x,B8h RDI1RI RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00

x,B9h RDI1SYN RI3SYN RI2SYN RI1SYN RI0SYN RW : 00x,BAh RDI1IS BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00x,BBh RDI1LT0 LUT1[3:0] LUT0[3:0] RW : 00x,BCh RDI1LT1 LUT3[3:0] LUT2[3:0] RW : 00x,BDh RDI1RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00

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x,BEh RDI1RO1 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00DIGITAL BLOCK REGISTERS

Data and Control Register0,20h DBB00DR0 Data[7:0] # : 000,21h DBB00DR1 Data[7:0] W : 000,22h DBB00DR2 Data[7:0] # : 000,23h DBB00CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,20h DBB00FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,21h DBB00IN Data Input[3:0] Clock Input[3:0] RW : 001,22h DBB00OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 00

0,24h DBB01DR0 Data[7:0] # : 000,25h DBB01DR1 Data[7:0] W : 000,26h DBB01DR2 Data[7:0] # : 000,27h DBB01CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,24h DBB01FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,25h DBB01IN Data Input[3:0] Clock Input[3:0] RW : 001,26h DBB01OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,28h DBB02DR0 Data[7:0] # : 000,29h DBB02DR1 Data[7:0] W : 000,2Ah DBB02DR2 Data[7:0] # : 000,2Bh DBB02CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,28h DBB02FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,29h DBB02IN Data Input[3:0] Clock Input[3:0] RW : 001,2Ah DBB02OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,2Ch DBB03DR0 Data[7:0] # : 000,2Dh DBB03DR1 Data[7:0] W : 000,2Eh DBB03DR2 Data[7:0] # : 00

0,2Fh DBB03CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,2Ch DBB03FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,2Dh DBB03IN Data Input[3:0] Clock Input[3:0] RW : 001,2Eh DBB03OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,30h DBB10DR0 Data[7:0] # : 000,31h DBB10DR1 Data[7:0] W : 000,32h DBB10DR2 Data[7:0] # : 000,33h DBB10CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,30h DBB10FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,31h DBB10IN Data Input[3:0] Clock Input[3:0] RW : 001,32h DBB10OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,34h DBB11DR0 Data[7:0] # : 000,35h DBB11DR1 Data[7:0] W : 000,36h DBB11DR2 Data[7:0] # : 000,37h DBB11CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,34h DBB11FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,35h DBB11IN Data Input[3:0] Clock Input[3:0] RW : 001,36h DBB11OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,38h DBB12DR0 Data[7:0] # : 000,39h DBB12DR1 Data[7:0] W : 000,3Ah DBB12DR2 Data[7:0] # : 000,3Bh DBB12CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,38h DBB12FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,39h DBB12IN Data Input[3:0] Clock Input[3:0] RW : 001,3Ah DBB12OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 000,3Ch DBB13DR0 Data[7:0] # : 000,3Dh DBB13DR1 Data[7:0] W : 000,3Eh DBB13DR2 Data[7:0] # : 000,3Fh DBB13CR0 Function Control/Status bit for selected function[6:0] Enable # : 001,3Ch DBB13FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,3Dh DBB13IN Data Input[3:0] Clock Input[3:0] RW : 001,3Eh DBB13OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 00

Interrupt Mask Register

0,E1h INT_MSK1 DCB13 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00 RW : 00Ch dn: K hiu # c ngha l truy nhp theo mt cch ring.

K hiu x nm trong trng a ch cho bit thanh ghi c th c truy nhp mkhng cn bit dy thanh ghi no ang c s dng.

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1. Lin kt s ton cc(Global Digital Interconnect - GDI)

GDI l mt cu hnh kt ni trong dy tn hiu hn hp PSoC c mc chung nht.

Bng 5 - 2: Cc thanh ghi ca GDIAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

1,D0h GDI_O_IN GIONOUT7 GIONOUT6 GIONOUT5 GIONOUT4 GIONOUT3 GIONOUT2 GIONOUT1 GIONOUT0 RW : 001,D1h GDI_E_IN GIENOUT7 GIENOUT6 GIENOUT5 GIENOUT4 GIENOUT3 GIENOUT2 GIENOUT1 GIENOUT0 RW : 001,D2h GDI_O_OU GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 001,D3h GDI_E_OU GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4 GOEUTIN3 GOEUTIN2 GOEUTIN1 GOEUTIN0 RW : 00

GDI bao gm bn ng bus 8 bit. Hai ng bus l bus u vo cho php tnhiu i t chn ca chp vo CPU. Nhng bus ny c gi l Global Input Odd(GIO[7:0]) v Global Input Even (GIE[7:0]). Hai bus khc l bus u ra cho php tnhiu i t CPU n cc chn ca chp. Chng c gi l Global Output Odd(GOO[7:0]) v Global Output Even (GOE[7:0]). T Odd v Even trong phn tn

ca bus ch ra rng cng no ca chp c th

c kt ni vi bus. Nhng

ng Busc tn Odd c kt ni vi tt c cc cng c nh s l v nhng bus c tnEven c kt ni vi tt c cc cng c nh s chn. Lu rng t Odd v Eventrong tn bus m ch cc cng ch khng phi l cc chn.

C hai u ti tn hiu GDI v cc chn ca cng. Mt u u c cu hnhnhl mt ngun hay mt ch. V d, mt chn GPIO c th cu hnh cp tn hiucho u vo ton cc hay nhn tn hiu t mt u ra ton cc. C hai kiu tn hiuc kt ni vi bus ton cc. Nhng khi s c s dng nhl mt ngun hay chcho mng ton cc, v xung nhp h thng c th c dng cung cp xung nhpcho nhng thnh phn cn thit thng qua mng ton cc.

Bng 5-3: S sp xp bus ton cc ti cc cng

Global Bus PortsGIO[7:0], GOO[7:0] P1, P3, P5GIE[7:0], GOE[7:0] P0, P2, P4

V c nhiu cng cng kt ni vi mt ng bus ton cc nn c mt cch spt mt ti nhiu (one-to-many) gia cc ng ni ca mt bus ton cc v cc chnca cng vo ra. V d, Nu GIO[1] c s dng a mt tn hiu u vo ti mtkhi PSoC s th mt trong cc chn P1[1], P3[1], P5[1] c th c s dng. u racng tng t nhvy. V d, Nu GOE[3] c s dng mang mt tn hiu t khi

PSoC s n mt chn vo ra th bt c chn no trong cc chn P0[3], P2[3], P4[3]u c th c s dng.

1.1. M t kin trc.Mc ch chnh ca biu khi kin trc l trao i thng tin gia bus ton

cc v cc cng vo ra. Lu rng bt c u vo no u c th c ni vi u ratng ng ca n, s dng b m ba trng thi c t 4 gc ca hnh v. Hn na,u ra ton cc c th c ni tt vi u vo ton cc bng b m ba trng thi.Hnh ch nht nm gia ca hnh v i din cho dy cc khi PSoC s.

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Hnh 5-2: S cu trc lin kt vo ra s

1.2. Thanh ghi GDI_O_IN v GDI_E_INS dng bit thit lp trong cc thanh ghi GDI_x_IN, mng u vo ton cc c th

c cu hnh kch thch mng u ra tng ng ca n. V d, GIE[7] GOE[7].

C tt c 16 bit iu khin kh nng kt ni gia u vo ton cc v u ra toncc. Nhng bit ny nm trong thanh ghi GDI_O_IN v GDI_E_IN. Bng sau y litk ngha ca tng v tr bit trong thanh ghi GDI_O_IN v GDI_E_IN.

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Bng 5-4: Thanh ghi GDI_x_IN

GDI_x_IN[0] 0: Khng kt ni gia GIx[0] v GOx[0]1: Cho php GIx[0] kch thch GOx[0]



GDI_x_IN[3] 0: Khng kt ni gia GIx[3] v GOx[3]1: Cho php GIx[3] kch thch GOx[3]GDI_x_IN[4] 0: Khng kt ni gia GIx[4] v GOx[4]

1: Cho php GIx[4] kch thch GOx[4]GDI_x_IN[5] 0: Khng kt ni gia GIx[5] v GOx[5]

1: Cho php GIx[5] kch thch GOx[5]GDI_x_IN[6] 0: Khng kt ni gia GIx[6] v GOx[6]

1: Cho php GIx[6] kch thch GOx[6]GDI_x_IN[7] 0: Khng kt ni gia GIx[7] v GOx[]

1: Cho php GIx[7] kch thch GOx[7]

1.3. Thanh ghi GDI_O_OU v GDI_E_OU.Nhng bit cu hnh thm c a ra trong thanh ghi GDI_x_OU. N cho php

u ra ton cc kch thch u vo ton cc tng ng. V d, GOE[7] GIE[7].

C tt c 16 bit iu khin kh nng kt ni gia u ra ton cc v u vo toncc. Nhng bit ny nm trong thanh ghi GDI_O_OU v GDI_E_OU. Bng sau y litk ngha ca tng v tr bit trong thanh ghi GDI_O_OU v GDI_E_OU.

Bng 5-5: Thanh ghi GDI_x_OU

GDI_x_OU[0] 0: Khng kt ni gia GIx[0] v GOx[0]1: Cho php GOx[0] kch thch GIx[0]







GDI_x_OU[7] 0: Khng kt ni gia GIx[7] v GOx[]1: Cho php GOx[7] kch thch GIx[7]

Kh nng cu hnh ca GDI khng cho php ng ni chn v ng ni l hay

ng ni vi ch s khc nhau ni c vi nhau. Chng hn nhng kt ni sau y lkhng th c trong chp PSoC.

GOE[7]GIO[7]

GOE[0]GIE[7]

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2. Kt ni dy cc khi s(Array Digital Interconnect - ADI)

Dy cc khi PSoC s dng mt kin trc leo thang c thit k h tr t mtti bn hng khi PSoC s. Phn kt ni theo dy (ADI) khng c mt s kt ni c

th cu hnh no c, bi vy n cng chng s dng mt thanh ghi no c.2.1. M t kin trc

Kt ni dy khi s c ch ra trong Hnh 5-3. ADI khng th cu hnh c, bivy thng tin trong chng ny ch gip cho ngi c hiu v cu trc ca n m thi.

Hnh 5-3: Cu trc dy cc khi PSoC s

Nhng thnh vin khc nhau trong h PSoC s c s bin i s lng cc khiPSoC trong mt dy. Nhng khi ny c sp xp theo cc hng v ADI cung cpmt kin trc lin kt chung gia lin kt s ton cc (GDI) v lin kt khi s theohng (RDI). Khng cn bit s lng hng c trong mt chp, iu quan trng l cchng PSoC c lin kt vi vo ra ton cc theo mt cch ging nhau. S lin kt nyto ra mt v tr duy nht ca hng v c gii thch nhsau:

a. a ch thanh ghi: Cc hng v khi trong chp cn phi c mt a ch thanhghi duy nht.

b. Mc u tin ngt: Mi mt khi PSoC c mt vector ngt v mt mc u tinngt. V tr ca hng trong dy quyt nh u tin ca cc khi PSoC trongmt hng. Hng c nh s cng thp th u tin ngt cng cao v a chvector ngt cng thp.

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c. Truyn tin ph bin: Mi mt hng PSoC s c mt mng truyn tin bn trongv c th c s dng c lp bn trong bi mt trong bi bn khi PSoC s.Hoc c th c s dng bn ngoi, trong trng hp c ni cn s dngmng truyn tin t bn ngoi, ngun truyn tin c th l mt trong nhng hngkhc trong dy. Bi vy, ty thuc vo v tr ca hng trong dy, s c s lachn khc nhau cho vic s dng mng truyn tin ph bin.

d. V tr trong dy: Khi u tin trong hng u tin v khi cui cng trong hngcui cng khng c ni vi nhau, bi vy, dy cc khi s khng c dng nhl mt ng vng. Khi u tin trong dy c u vo t khi trc c hxung mc thp. Nu c hng th hai trong dy th u ra ti khi tip theo sc ni vi khi tip theo. Khi cui cng ca hng cui cng c u ra tikhi tip theo c h xung mc thp.

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3. Kt ni cc khi s theo hng(Row Digital Interconnect RDI)

Mc ny ch ni v mt hng khi PSoC s. N khng ni v chc nng, u vohay u ra cho nhng khi PSoC ring bit.

Bng 5-6: Thanh ghi hng PSoC sAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

x,xxh RDI0RI RI3[1:0] RI2[1:0] RI1[1:0] RI0[1:0] RW : 00x,xxh RDI0SYN RI3SYN RI2SYN RI1SYN RI0SYN RW : 00x,xxh RDI0IS BCSEL[1:0] IS3 IS2 IS1 IS0 RW : 00x,xxh RDI0LT0 LUT1[3:0] LUT0[3:0] RW : 00x,xxh RDI0LT1 LUT3[3:0] LUT2[3:0] RW : 00x,xxh RDI0RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00x,xxh RDI0RO1 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00

Ch dn: K t x trc du phy trong trng a ch cho bit rng thanh ghi ny c c hai dy thanh ghiK t xx sau du phy trong trng a ch cho bit rng c nhiu thanh ghi nhvy.

C rt nhiu tn hiu gh qua hng PSoC s trn ng i ca n hoc t nhngkhi PSoC ring bit. Tuy nhin, c mt s lng nh cc tn hiu gh qua mch cuhnh c trn ng i ca n ti v t cc khi PSoC s. Mch cu hnh c chophp kt ni mm do hn gia khi s v bus ton cc.

3.1. M t kin trcTrong Hnh 5-4, bn trong mt hng khi PSoC s, c bn khi PSoC. Hai khi

u l loi C bn (DBB). Hai khi sau l loi truyn thng (DCB). Hnh v m t ktni gia cc khi PSoC trong mt hng.

Hnh 5-4: Chi tit v nhm bn khi s PSoC

Trong Hnh 5-5, chi tit v nhm bn khi PSoC c thay bng mt hp tmca hnh v vi tn gi 4 PSoC Block Grouping

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Hnh 5-5: Cu trc mt hng khi PSoC s3.2. Cc thanh ghi c nh ngha

Hai u vo duy nht ti hng khi PSoC s c th cu hnh c l hai ngbus 8 bit u vo ton cc Global Input Even v Global Input Odd. Hai u ra duy nhtc th cu hnh c ca hng khi PSoC s l hai ng bus 8 bit u ra ton ccGlobal Output Even v Global Output Odd. Hnh 5-5 minh ha mi lin h gia tnhiu ton cc v tn hiu ca hng.

Ch pha bn tri ca Hnh 5-5 l u vo ton cc (GIE[n] v GIO[n]) lnhng u vo ti b chn a thnh phn vo 4 ra 1. u ra ca nhng b chn ny li

l u vo ca hng (RI[x]). Do c bn b chn vo 4 ra 1 nn mi b c mt s uvo nht nh nn mt hng c th truy nhp n tt c cc ng u vo ton cctrong chp PSoC.

3.2.1. Thanh ghi RDIxRI.Nhng bit la chn dng iu khin bn b chn c t trong thanh ghi

RDIxRI, k t x biu th cho ch s hng tng ng. Bng 5-7 lit k ngha ca bnthit lp c th cho mi b chn a thnh phn.

Bng 5-7: Thanh ghi RDIxRI

RI0[1:0]

0h: GIE[0]

1h: GIE[4]2h: GIO[0]3h: GIO[4]0h: GIE[1]

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RI1[1:0] 1h: GIE[5]2h: GIO[1]3h: GIO[5]

RI2[1:0]0h: GIE[2]1h: GIE[6]2h: GIO[2]3h: GIO[6]

RI3[1:0]

0h: GIE[3]

1h: GIE[7]2h: GIO[3]3h: GIO[7]

3.2.2. Thanh ghi RDIxSYNMc nh mi u vo ca hng u c ng b vi xung nhp h thng. Tuy

nhin, ngi s dng c th la chn v hiu ha s ng b ha ny bng cchthit lp bit thch hp trong thanh ghi RDIxSYN.

Bng 5-8: Thanh ghi RDIxSYN

RI3SYN 0: u vo ca hng th 3 c ng b ha vi xung nhp h thng 24MHz1: u vo ca hng th 3 khng ng b ha vi xung nhp ca h thng




Thanh ghi RDIxRI v RDIxSYN l hai thanh ghi duy nht tc ng n tn hiuu vo ca hng khi PSoC s. Tt c cc thanh ghi khc u lin quan ti cu hnhtn hiu u ra.

3.2.3. Thanh ghi RDIxISNh c cp, mi mt bng tra cu (Lookup table - LUT) c hai u vo, mt

u vo c th cu hnh c (u vo A) cn mt u vo c nh vi u ra ca hng. uvo c th cu hnh c ca LUT chn gia mt u ra n v mt u vo n. Bng 5-9lit k la chn cho mi LUT trong mt hng. Nhng bit ny c t tn l IS (InputSelect). u vo c nh ca LUT lun lun l RO[s ca LUT + 1]. V d, u vo c nhca LUT0 l RO[1], u vo c nh ca LUT1 l RO[2] v LUT 3 l RO[0].

Bng 5-9: Thanh ghi RDIxIS

BCSEL[1:0] 0: Hng 0 iu khin mng truyn tin ni b1: Hng 1 iu khin mng truyn tin ni b

2: Hng 2 iu khin mng truyn tin ni b3: Hng 3 iu khin mng truyn tin ni bIS3 0: u vo 3 ca LUT 3 l RO[3]

1: u vo 3 ca LUT 3 l RI[3]IS2 0: u vo 2 ca LUT 2 l RO[2]



1: u vo 0 ca LUT 0 l RI[0]

Khi gi tr ca BCSELL bng vi s hng th b m ba trng thi s iu khin mng truyntin ca hng c v hiu ha t u vo la chn ca b Mux v v th mt khi trong hng cth mng truyn tin ni b.

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3.2.4. Thanh ghi RDIxLTxu ra t hng PSoC s l mt bit phc tp hn u vo. Hnh 5-5 miu t u ra

ca hng PSoC s. Ch trong hnh v th khi c t tn l Lx. Khi ny i dincho mt bng tra cu 2 u vo (LUT). LUT cho php ngi s dng nh r mt trongs 16 hm logic c th p dng vi hai u vo. u ra ca hm logic s quyt nh gi

tr s

c

a ti bus u ra ton cc Global Output Even v Global Output Odd.Bng 5-10 miu t mi quan h gia bn bit cu hnh ca bng tra cu v kt qu cahm logic. Mt s ngi s dng nhn ra rng rt d quyt nh thit lp bit thchhp bng cch nh cc bit cu hnh i din theo ct u ra trong mt bng chn lgm 2 u vo. Bng 5-10 lit k by gi tr minh ha cho mi lin h gia ct u raca bng chn l vi bit cu hnh u vo.

Bng 5-10: V d v bng chn l LUT

A B AND OR A+B A& B A B True

0 0 0 0 1 0 0 0 10 1 0 1 0 0 0 1 11 0 0 1 1 1 1 0 11 1 1 1 1 0 1 1 1

LUT[3:0] 1h 7h Bh 2h 3h 5h Fh

Bng 5-11: Thanh ghi RDIxLTx

LUTx[3:0] 0h: 0000: FALSE1h: 0001: A .AND. B

2h: 0010: A .AND. B 3h: 0011: A

4h: 0100: A .AND B5h: 0101: B6h: 0110: A .XOR. B7h: 0111: A .OR. B8h: 1000: A .NOR. B9h: 1001: A .XNOR. B

Ah: 1010: B

Bh: 1011: A .OR. B

Ch: 1100: A

Dh: 1101: A .OR. BEh: 1110: A .NAND. BFh: 1111: TRUE

3.2.5. Thanh ghi RDIxROx.Nhng bit cu hnh cui cng cho u ra t dy cc khi PSoC s c cho trong

hai thanh ghi RDIxROx. Hai thanh ghi ny lu gi 16 bit v c th c lp cho phpb m ba trng thi kt ni vi tt c 8 ng ra chn v 8 ng ra l. iu ny cngha l bt c hng no u c th kt ni vi u ra ton cc. Lu rng b kchthch ba trng thi c dng kch thch ng ra ton cc. Bi vy, i vi chp chn mt hng khi PSoC s c nhiu b kch thch trn mt ng ra ton cc thtrch nhim ca ngi s dng l phi khng nh rng chp cha c cu hnh vinhiu b kch thch trn bt c mt u ra ton cc no.

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4. Cc khi PSoC s(Digital Blocks)

Bng 5-12: Thanh ghi ca khi PSoC s

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access

Thanh ghi iu khin v d liu0,xxh DBB00DR0 Data[7:0] # : 000,xxh DBB00DR1 Data[7:0] W : 000,xxh DBB00DR2 Data[7:0] # : 000,xxh DBB00CR0 Function Control/Status bit for selected function[6:0] Enable # : 00

Thanh ghi mt n che ngt0,E1h INT_MSK1 DCB13 DCB12 DBB11 DBB10 DCB03 DCB02 DBB01 DBB00 RW : 00

Thanh ghi cu hnh1,xxh DBB00FN Data Invert BCEN End/Single Mode[1:0] Function[2:0] RW : 001,xxh DBB00IN Data Input[3:0] Clock Input[3:0] RW : 001,xxh DBB00OU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 00

Ch dn: # truy nhp bit theo mt cch ringxx k t i sau du phy trong trng a ch cho bit rng c nhiu thanh ghi nhvy

Tt c cc khi PSoC s u c th c cu hnh thc hin bt c mt chc

nng no trong 5 chc nng c bn sau: b nh thi, b m, b iu ch rngxung, PRS, kim tra chu k tha (CRC). Nhng chc nng ny c s dng bngcch cu hnh mt khi PSoC c lp hay mt chui vi khi PSoC lin nhau thchin chc nng ln hn 8 bit. Cc khi PSoC s truyn thng c thm hai chc nngna l: SPI ch, SPI t hay truyn thng khng ng b hai chiu.

Mi mt chc nng ca khi PSoC s u c lp vi cc khi chc nng khc.C ti 7 thanh ghi c s dng quyt nh chc nng v trng thi ca khi PSoC.Nhng thanh ghi ny c a ra trong Bng 5-12. Cc thanh ghi chc nng ca khis lun lun kt thc vi ch FN, tn ca nhng thanh ghi u vo lun lun kt thcvi ch IN v cui cng tn ca thanh ghi u ra lun lun kt thc vi ch OU.

Mi khi PSoC c ba thanh ghi (DR0, DR1, DR2) v mt thanh ghi iu khin(CR0). ngha ca nhng bit trong thanh ghi ny ph thuc nhiu vo chc nng mn m nhim. Ngoi 7 thanh ghi iu khin chc nng v trng thi ca khi PSoC scn c thm mt bit che ngt cho mi mt khi s. Mi mt khi PSoC c duy nhtmt vector ngt v v vy c th to cho n mt trnh phc v ngt.

4.1. M t cu trc mc cao nht, nhng thnh phn chnh ca khi PSoC s l ng d liu, b

chn u vo, b chia u ra, bus ba trng thi PRSCRC, giao din bus h thng, ccthanh ghi cu hnh, v di tn hiu.

4.1.1. B chn u voNhn chung, mi mt chc nng u c mt u vo xung nhp v mt u vo

d liu c th c la chn t nhiu ngun khc nhau. Mi mt u vo c lachn vi mt b chn vo 16 ra 1. Hn na, c mt b chn vo 4 ra 1 cung cp mtu vo ph cho chc nng SPI Slave, chc nng yu cu 3 u vo: Xung nhp, dliu, v SS_ (tr khi l SS_ c bt p hot ng cng vi bit cho php vo ra ph).u vo b chn ny d nh c la chn t u vo GPIO.

4.1.2. ng b ha li xung nhp u vo.Nhng khi PSoC s cho php la chn xung nhp t 1 trong 16 ngun. Ngun c

th l xung nhp h thng (VC1, VC2, VC3, SYSCLK v SYSCLKX2), cc chn uvo, u ra t cc khi PSoC khc. qun l c lch xung v m bo rng giaodin gia cc khi c tnh ton thi gian ph hp trong tt c cc trng hp, tt c

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cc u vo xung nhp ca khi s cn phi c ng b ha li vi xung nhp hthng SYSCLK hoc SYSCLKX2. Xung nhp SYSCLK hoc SYSCLKX2 cng c thc s dng trc tip. Bit AUXCLK trong thanh ghi DxBxxOU c s dng chr u vo ng b. Vic ng b ha u vo c thc hin theo cc lut sau:

a. Nu xung nhp u vo bt ngun t SYSCLK (c th c chia nh) th sc khi PSoC s ng b ha li vi xung nhp SYSCKL. Hu ht cc xung

nhp trong chp bt u thuc loi ny. V d, VC1, VC2b. Nu xung nhp u vo bt ngun t SYSCLKX2, th n s c ng b ha

vi xung nhp SYSCLKX2

c. Chn trc tip t xung nhp SYSCLKd. Chn trc tip t xung nhp SYSCLKX2e. ng b ha Bypass. Rt it khi la chn iu ny, bi v nu xung nhp khng

c ng b th chng c th bt u sai vi lnh c v ghi ca CPU. Tuynhin, n c th xy ra vi trng hp mt chn ngoi pht xung nhp cho khi

s trng thi khng ng b. V d, nu ng

i s dng mun ng b tcng ca CPU bng ngt hay bng mt k thut no khc.

Nhng lu sau y lit k nhng cu hnh khng c cho php, mc d phncng khng h ngn cm chng. Bng tm tt ca nhng lu ny l b chia xungnhpkhng c cu hnh nhl mt cch to xung nhp u ra bng vi SYSCLKhay SYSCLKX2.

1. Khi VC1 c cu hnh l chia bi 1 th la chn xung nhp VC1 l khng chophp. Vic cu hnh ny to ra mt xung nhp bng vi xung nhp h thngSYSCLK. Bi vy, SYSCLK nn c dng trc tip bng cch t cc bitAUXCLK trong thanh ghi DxBxxOU ln 11b.

2. Khi c VC1 v VC2 u c cu hnh chia bi 1 th cng tng t vic chnxung nhp VC2 l khng cho php. Bi vy, s dng xung nhp trc tip nhtrn.

3. Khi VC3 c cu hnh sao cho u ra c tn s bng vi xung nhp h thngSYSCLK hay SYSCLKX2 th vic chn xung nhp t VC3 cng khng cphp. Bi vy, cng phi s dng xung nhp trc tip SYSCLK hoc SYSCLK.

Tt c nhng vn c cp trong phn ti ng b xung nhp thc cmiu t trong Hnh 5-6.

Hnh 5-6: Ti ng b xung nhp u vo

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Bng 5-13:Nhng la chn bit AUXCLK

M M t S dng00 Bypass Ch s dng thit lp ny cho u vo trng thi khng ng b. Cng c

s dng khi SYSCLK2 (48M) c la chn.01 Ti ng b vi

SYSCLK (24M)S dng thit lp ny cho bt c xung nhp no da trn SYSCLK. VC1, VC2,VC3 c iu khin bi SYSCKL, cc khi s vi ngun xung nhp da trnSYSCLK, mng truyn tin vi ngun da trn SYSCLK , u vo v u rahng vi ngun da trn SYSCLK.

10 Ti ng b viSYSCLKX2 (48M)

S dng thit lp ny cho bt c xung nhp no da trn SYSCLK2. VC3 ciu khin bi SYSCLK2, cc khi s vi xung nhp da trn SYSCLK2, bustruyn tin vi ngun da trn SYSCLK2, u vo v u ra ca hng vingun da trn SYSCLK2

11 SYSCLK trc tip S dng thit lp ny pht xung nhp SYSCKL trc tip ti cc khi s.Lu rng thit lp ny hon ton khng lin h vi xung nhp ti ng bnhng t k t th SYSCLK khng th ti ng b vi chnh n. N chophp mt xin trc tip iu khin ngun SYSCLK

4.1.3. B phn ly u raHu ht cc chc nng c hai u ra, mt u ra chnh v mt u ra ph. Mi

mt u ra u c iu khin trn hng bus u ra. Mi mt b phn ly c thihnh vi 4 b kch thch 3 trng thi. C hai bit la chn mt trong bn b kchthch v mt bit thm vo cho php b kch thch.

Clock Select: La chn xung nhpData Select: La chn d liu voAux Data Select: La chn u vo d liu vo phInternal Signals for Carry, Compare, Enable, Capture, and Gate chaining form previous block:Tn hiu trong cho Nh, So snh, Cho php, Chp, v Cng t khi trc .Primary Function Output clock chaining to next block: u ra chc nng chnh pht xung nhp tikhi tip theo trong chui.Block Interrupt: Ngt ca khiBroadcast Output: u ra truyn tin ph binInternal Signals for Data, Carry, Compare, and Gate chaining to next block: Tn hiu trong cho

D liu, Nh, So snh, v Cng ti khi tip theo.Hnh 5-7: S khi m t mc cao nht ca cc khi PSoC s.

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4.1.4. Tn hiu ni chui cc khiMi mt khi PSoC s c kh nng ni thnh chui to ra nhng chc nng c

rng ln hn 8 bit. C nhng tn hiu truyn b thng tin nh l So snh, Nh,Cho php, Chp v Cng t mt khi ti mt khi tip theo thi hnh chc nng vi chnh xc cao hn. S la chn trong thanh ghi chc nng quyt nh xem tn hiuno l thch hp vi chc nng mong mun. Nhng Module c thit k thi hnh

chc nng s vi rng ln hn 8 bit s t ng la chn tn hiu ni chui, khngnh thng tin chnh xc chy gia cc khi.

4.2. Nhng ngoi vi c to bi khi PSoC s Cc b nh thi 8,16,24,32-bit vi cc c im sau:

Hnh 5-8: S nguyn l ca b nh thi

- rng thanh ghi 8, 16, 24, 32 bit, s dng 1,2,3,4 khi PSoC theo th t

- Xung nhp ngun ln ti 48 MHz

- T ng np li chu k khi m xong

- Kh nng chp (capture) ti 24 MHz

- u ra m kt thc c th c s dng nhl u vo xung nhp cho cc chcnng s v tng t khc

- La chn ch ngt khi m kt thc, chp, hoc l khi b m t mt gi trt trc.

Cc Module b nh thi l nhng b m li vi chu k c th lp trnhc, c kh nng chp gi. Xung nhp v cc tn hiu cho php c th c lachn t ngun ngoi hoc t xung nhp h thng. Sau khi khi ng, B nhthi hot ng lin tc v t ng ti chu k t thanh ghi chu k mi khi m ktthc. Cc s kin c th chp gi gi tr m hin thi ca Timer bng cch xc

nhn sn xung ca tn hiu chp gi u vo. Trong mi chu k, b nh this so snh gi tr m vi gi tr so snh t trong thanh ghi compare kimtra iu kin Less than hay Less than or Equal To. Cc ngt c th c sinhra da trn tn hiu m kt thc hoc iu kin so snh.

Cc b m 8, 16,24,32 bit vi nhng c im sau:- rng thanh ghi m 8,16,24,32 bit, tng ng chim 1,2,3,4 khi PSoC.

- Xung nhp c th ln ti 48 MHz

- T ng ti li chu k khi m kt thc

- rng xung c th lp

1811 tai lieu ve psoc.minhhagroup

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