1/6 aadithya v. karthik feb 2014, bears lightning talk, berkeley abcd: “booleanizing” analog...
TRANSCRIPT
1/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
ABCD: “Booleanizing” AnalogSystems for Verifying Chips
Aadithya V. Karthik,
Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko,Robert Brayton, and Jaijeet Roychowdhury
EECS Dept., The University of California, Berkeley
Feb 2014, BEARS, Berkeley
2/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
The Problem: Verifying a Chip
Specification
Chip designers
Chip
3/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
Surrounded byDigital Logic
Example: SERDES
Analogparts
PLL
CDR I/O
The Problem: AMS Verification
Want to verify complete systemo e.g., eye opening height > 1V?
Proof or counter-example needed
>1V
4/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
Our approach: “Booleanize” the analog parts
Best verification tools = all Boolean, no continuous
Digital componentsVerification tools accept
Analog components
Challenge: Analog models Digital models+Continuous Boolean
(don't mix)
SAR-ADC Boolean T/Happroximation Boolean
comparatorapproximation
Boolean DACapproximation
ALLBOOLEAN
Formal verification, high-speed simulation, test pattern generation, ...
ABCD: Booleanapproximation
… for the full combined system!
Fast
5/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
ABCD in action
Analog CircuitPurely Boolean
ModelABCD
Bit Sequence
Example: Channel + Equalizer
6/6Aadithya V. Karthik <[email protected]> Feb 2014, BEARS lightning talk, Berkeley
Circuits Successfully Booleanized
Charge pump
Equalizer
Delay line
Power grid
SAR-ADC
I/O signaling system