Control Voltage

VCC

VCC

Hi-Z

SYNC

GVDD

GAIN/SLV

GND

HI-Z

GND

DRV595

MODSEL

SDZ

FAULTZ

IN+

IN-

PVCC

BSP

OUTP

FS2

FS1

FS0

SYNC

OUTN

BSN

PVCC

AVCC

VCC

VCCShutdown Control

LOAD

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

15V/±4A High-Efficiency PWM Power DriverCheck for Samples: DRV595

1FEATURES • Thermally Enhanced Package– DAP (32-pin HTSSOP Pad-down)

2• ±4 A Output Current• –40°C to 85°C Ambient Temperature Range• Wide Supply Voltage Range: 4.5 V – 26 V

• High Efficiency Generates Less HeatAPPLICATIONS

• Multiple Switching Frequencies• Power Line Communications (PLC) Driver– Master/Slave Synchronization• Thermoelectric Cooler (TEC) Driver– Up to 1.2 MHz Switching Frequency• Laser Diode Biasing• Feedback Power Stage Architecture with High• Motor DriverPSRR Reduces PSU Requirements• Servo Amplifier• Single Power Supply Reduces Component

Count• Integrated Self-Protection Circuits Including

Over-Voltage, Under-Voltage, Over-Temperature, and Short Circuit with ErrorReporting

DESCRIPTIONThe DRV595 is a high-efficiency, high-current power driver ideal for driving a wide variety of loads in systemspowered from 4.5V to 26V. PWM operation and low output stage on-resistance significantly decrease powerdissipation in the amplifier.

The DRV595 advanced oscillator/PLL circuit employs multiple switching frequency options; this is achievedtogether with a Master/Slave option, making it possible to synchronize multiple devices.

The DRV595 is fully protected against faults with short-circuit, thermal, over-voltage, and under-voltageprotection. Faults are reported back to the processor to prevent devices from being damaged during overloadconditions.

SIMPLIFIED APPLICATION CIRCUIT

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

SDZ

Hi-Z

TTLBuffer

GainControl

GAIN

OUTP_FB

IN+

IN–

GainControl

OUTPN_FB

FAULTZ

SYNC

GAIN/SLV

FS<2:0>

AVCC

PVCC

LDORegulator

GND

AVDD

GVDD

RampGenerator

Biases andReferences

Startup ProtectionLogic

SC Detect

ThermalDetect

UVLO/OVLO

GND

BSN

OUTP

GND

OUTN

OUTN_FB

BSP

OUTP_FB

PVCCGVDD

PVCC

GateDrive

PVCCGVDD

PVCC

GateDrive

PWMLogic

Modulation Select

+

–

+

–

+

–

+

–

+

–

+

–

ThermalPad

PVCC

GVDD

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

SYSTEM BLOCK DIAGRAM

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Product Folder Links: DRV595

FAULTZ

SDZ

SYNC

FS0

FS1

Hi-Z

GND

GND

GVDD

IN–

GVDD

IN+

AVCC

OUTP

PVCC

BSN

GND

OUTN

PVCC

OUTN

BSN

PVCC

OUTP

BSP

MODSEL

BSP

GND

GND

PVCC

GND

GAIN/SLV

FS2

32

31

30

29

19

13

14

15

16 17

18

20

1

2

3

4

5

6

7

8

9

10

11

12 21

22

23

24

28

27

26

25Thermal

PAD

Bottom

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

PINOUT CONFIGURATIONDRV595

32-PIN HTSSOP Package (DAP)(Top View)

Pin FunctionsPIN

TYPE DESCRIPTIONNO. NAME

1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1SPW mode). TTL logic levels withcompliance to AVCC.

2 SDZ I Shutdown logic input (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels withcompliance to AVCC.

3 FAULTZ DO General fault reporting. Open drain. See Table 3FAULTZ = High, normal operationFAULTZ = Low, fault condition

4 IN+ I Positive differential input. Biased at 3 V.

5 IN– I Negative differential input. Biased at 3 V.

6, 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to anycomponent other than a 1 µF X7R ceramic decoupling capacitor and the GAIN/SLV resistor divider.

8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.

9, 10, 11 GND G Ground

12 Hi-Z I Input for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logiclevels with compliance to AVCC.

13 FS2 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz.

14 FS1 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz.

15 FS0 I Frequency Selection input, used to select oscillator frequencies from 400kHz to 1200kHz.

16 SYNC DIO Clock input/output for synchronizing multiple devices. Direction determined by GAIN/SLV terminal.

17 AVCC P Analog Supply, can be connected to PVCC for single power supply operation.

18, 19 PVCC P Power supply

20, 24 BSN BST Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUTN

21 OUTN PO Negative output

22 GND G Ground

23 OUTN PO Negative output

25 GND G Ground

26, 30 BSP BST Boot strap for positive output, connect to 220 nF X5R, or better ceramic cap to OUTP

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DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

Pin Functions (continued)

PINTYPE DESCRIPTION

NO. NAME

27 OUTP PO Positive output

28 GND G Ground

29 OUTP PO Positive output

31, 32 PVCC P Power supply

33 Thermal G Connect to GND for best system performance. If not connected to GND, leave floating.Pad orPowerPAD™

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted) (1)

VALUE UNIT

Supply voltage, VCC PVCC, AVCC –0.3 to 30 V

IN+, IN– –0.3 to 6.3 V

Input voltage, VI GAIN / SLV, SYNC –0.3 to GVDD+0.3 V

SDZ, MODSEL –0.3 to PVCC+0.3 V

Slew rate, maximum (2) FS0, FS1, FS2, HI-Z, SDZ, MODSEL 10 V/msec

Operating free-air temperature, TA –40 to 85 °C

Operating junction temperature range, TJ –40 to 150 °C

Storage temperature range, Tstg –40 to 125 °C

Electrostatic discharge: Human body model, ESD ±2 kV

Electrostatic discharge: Charged device model, ESD ±500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) 100 kΩ series resistor is needed if maximum slew rate is exceeded.

THERMAL INFORMATIONDRV595

DAPTHERMAL METRIC (1) UNITS2 Layer PCB (2)

32 PINS

θJA Junction-to-ambient thermal resistance 22

ψJT Junction-to-top characterization parameter 0.3 °C/W

ψJB Junction-to-board characterization parameter 4.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.(2) For the PCB layout please see the DRV595EVM user guide.

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RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

VCC Supply voltage PVCC, AVCC 4.5 26 V

VIH High-level input voltage FS0, FS1, FS2, Hi-Z, SDZ, SYNC, MODSEL 2 V

VIL Low-level input voltage FS0, FS1, FS2, Hi-Z, SDZ, SYNC, MODSEL 0.8 V

VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V

FS0, FS1, FS2, Hi-Z, SDZ, MODSELIIH High-level input current 50 µA

(VI = 2 V, VCC = 18 V)

RL Minimum load Impedance Output filter: L = 10 µH, C = 3.3 µF 1.6 ΩMinimum output filter inductance under short-circuitLo Output-filter Inductance 1 µHcondition

ELECTRICAL CHARACTERISTICSTA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 5 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output offset voltage (measured| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mVdifferentially)

| IIH | High-level input current VCC = 24 V, VI = VCC 50 µA

SDZ = 2 V, No load or filter, PVCC = 12 V 30ICC Quiescent supply current mA

SDZ = 2 V, No load or filter, PVCC = 24 V 50 65

SDZ = 0.8 V, No load or filter, PVCC = 12 V <50Quiescent supply current in shutdownICC(SD) µAmode SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 65

Drain-source on-state resistance,rDS(on) PVCC = 21 V, Iout = 500 mA, TJ = 25°C 60 mΩmeasured pin to pin

R1 = open, R2 = 20 kΩ 19 20 21dB

R1 = 100 kΩ, R2 = 20 kΩ 25 26 27G Gain (MSTR) See Table 1

R1 = 100 kΩ, R2 = 39 kΩ 31 32 33dB

R1 = 75 kΩ, R2 = 47 kΩ 35 36 37

R1 = 51 kΩ, R2 = 51 kΩ 19 20 21dB

R1 = 47 kΩ, R2 = 75 kΩ 25 26 27G Gain (SLV) See Table 1

R1 = 39 kΩ, R2 = 100 kΩ 31 32 33dB

R1 = 16 kΩ, R2 = 100 kΩ 35 36 37

Full power bandwidth 60 kHz

ton Turn-on time SDZ = 2 V 10 ms

tOFF Turn-off time SDZ = 0.8 V 2 µs

GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V

IO = ±1 A, rds(on) = 60 mΩ 11.85VO Output voltage (measured differentially) V

IO = ±3 A, rds(on) = 60 mΩ 11.55

200 mVPP ripple at 1 kHz, Gain = 20 dB, InputsPSRR Power supply ripple rejection –70 dBAC-coupled to GND

VICM Input common-mode range 0.5 4.5 V

CMRR Common-mode rejection ratio PVCC = 12 V –56 dB

FS2=0, FS1=0, FS0=0 376 400 424

FS2=0, FS1=0, FS0=1 470 500 530

FS2=0, FS1=1, FS0=0 564 600 636

FS2=0, FS1=1, FS0=1 940 1000 1060Oscillator frequencyfOSC kHz(with PWM duty cycle < 96%) FS2=1, FS1=0,FS0=0 1128 1200 1278

FS2=1, FS1=0, FS0=1

FS2=1,FS1=1, FS0=0 Reserved

FS2=1, FS1=1,FS0=1

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DRV595

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ELECTRICAL CHARACTERISTICS (continued)TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 5 Ω (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output resistance in shutdown SDZ = 0.8 V 60 kΩPower-on threshold 4.1 V

Power-off threshold 28 V

Thermal trip point 150+ °C

Thermal hysteresis 15 °C

Over current trip point 7.5 A

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Product Folder Links: DRV595

0

10

20

30

40

50

60

70

80

90

100

4 6 8 10 12 14 16 18 20 22 24 26 28Supply Voltage (V)

Dra

in−

Sou

rce

On−

Sta

te R

esis

tanc

e (m

Ω)

IO = 1ATA = 25°C

G003

0

10

20

30

40

50

60

70

80

90

100

−40 −20 0 20 40 60 80 100 120 140150Temperature (°C)

Dra

in−

Sou

rce

On−

Sta

te R

esis

tanc

e (m

Ω)

PVCC = 12VIO = 1ATA = 25°C

G004

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10

Load Resistance (Ω)

Pow

er E

ffici

ency

(%

)

PO =1WPO =5WPO =10W

Gain =20dBTA = 25°CfS = 1MHz

G001

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10

Load Resistance (Ω)P

ower

Effi

cien

cy (

%)

PO =1WPO =5WPO =10W

Gain =20dBTA = 25°CfS = 500kHz

G001

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS

Efficiency (%) Efficiency (%)vs vs

RL - Load Resistance - Ω RL - Load Resistance - Ω

Figure 1. Figure 2.

rDS(on) - Drain-Source On-State Resistance mΩ rDS(on) - Drain-Source On-State Resistance mΩvs vs

VDD - Supply Voltage - V TA - Ambient Temperature - °C

Figure 3. Figure 4.

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−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

10 100 1k 10k 100kFrequency (Hz)

kSV

R (

dB)

Gain =20dBPVCC = 24V + 200mV p−pTA = 25°CRL = 5Ω

G008

10 100 1k 10k 100k−30

−20

−10

0

10

20

30

−300.0

−200.0

−100.0

0.0

100.0

200.0

300.0

Frequency (Hz)

Gai

n (d

B)

Pha

se (

°)GainPhase

Gain =26dBPVCC = 12VTA = 25°CRL = 5ΩLF = 10 µHCF = 3.3 µF

G009

12

14

16

18

20

22

24

26

28

4 6 8 10 12 14 16 18 20 22 24 26 28Supply Voltage (V)

Sup

ply

Cur

rent

(m

A)

TA = 25°CNo Load

G006

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

10 100 1k 10k 100kFrequency (Hz)

kSV

R (

dB)

Gain =20dBPVCC = 12V + 200mV p−pTA = 25°CRL = 5Ω

G007

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

TYPICAL CHARACTERISTICS (continued)Iq - Supply Current - mA PSRR-Supply Ripple Rejection Ratio (dB)

vs vsVDD - Supply Voltage - V f - Frequency - Hz

Figure 5. Figure 6.

PSRR-Supply Ripple Rejection Ratio (dB) Gain - V/V; Phase - °vs vs

f - Frequency - Hz f - Frequency - Hz

Figure 7. Figure 8.

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Product Folder Links: DRV595

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8Common−Mode Input Voltage (V)

Inpu

t Offs

et V

olta

ge (

mV

)

Gain =20dBTA = 25°CPVCC = 24VNo Load

G014

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8Common−Mode Input Voltage (V)

Inpu

t Offs

et V

olta

ge (

mV

)

Gain =20dBTA = 25°CPVCC = 12VNo Load

G014

10 100 1k 10k 100k−30

−20

−10

0

10

20

30

−300.0

−200.0

−100.0

0.0

100.0

200.0

300.0

Frequency (Hz)

Gai

n (d

B)

Pha

se (

°)

GainPhase

Gain =26dBPVCC = 24VTA = 25°CRL = 5ΩLF = 10 µHCF = 3.3 µF

G010

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

TYPICAL CHARACTERISTICS (continued)Gain - V/V; Phase - ° VIO - Input Offset Voltage - mV

vs vsf - Frequency - Hz VIC - Common-Mode Input Voltage - V

Figure 9. Figure 10.

VIO - Input Offset Voltage - mVvs

VIC - Common-Mode Input Voltage - V

Figure 11.

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Product Folder Links: DRV595

0 2 ƒw = p ´

FL

0

22 C

R2

2

´ =

´ ´ w

Lx

o

2 RL

2

´

=

w

L1

L2

C13.3 µF

C23.3 µF

CFTEC

2

1H(s)

s 2s 1=

+ +

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

APPLICATION INFORMATION

OUTPUT FILTER CONSIDERATIONS

The DRV595 can be used to drive a TEC element. The typical circuit used for this application is to have twofeedback loops – one for constant current, and the second to monitor the temperature, and provide adjustmentsto keep a constant temperature on the laser diode. An error amplifier is used to combine the two feedback loops,along with a control signal from the system. The output of the error amplifier is then fed into the DRV595.

An output filter needs to be used to prevent excessive ripple from reaching the TEC element. Some TECelements may be damaged by ripple; design the filter using the TEC specification to reduce the switchingwaveform enough to prevent TEC damage. This filter also reduces the amount of electrical noise coupled ontothe TEC element.

For most applications, a second-order Butterworth low-pass filter with the cut-off frequency set to a few kilohertzshould be sufficient. See Figure 12 for example filter designed with Equation 2, Equation 3, and Equation 4 .

Second-Order Butterworth LPF Transfer Function

(1)

Using Half-Circuit Analysis

Figure 12. Second Order Butterworth Low-Pass Filter Configuration

(2)

(3)

(4)

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Product Folder Links: DRV595

FS

2

FS

1

FS

0

GA

IN/S

LV

OU

TN

OU

TP

OU

T+

OU

T–

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

C3

FC

220u

fd/3

5V

+C

4

060

3X

7R

0.1

ufd

/50V

C5

060

3C

OG

1000p

fd/5

0V

C9

060

3X

7R

0.1

ufd

/50V

C10

060

3C

OG

1000p

fd/5

0V

C6

060

3X

5R

0.2

2u

fd/2

5V

C7

060

3X

5R

0.2

2u

fd/2

5V

R12

060

31

00

K/5

%R

13

060

3100

K/5

%R

14

060

31

00

K/5

%

GN

DC

8

FC

220u

fd/3

5V

+

GN

D

C11

121

0X

7R

3.3

fd/3

5V

µ

C13

121

0X

7R

3.3

µfd

/35V

FS

1

GN

D

GN

D

PV

CC

Red

GN

DB

lack

FS

0

FS

2

C1

060

3X

7R

1.0

ufd

/16V

GN

D

JP

3

FA

UL

TO

ran

ge

R5

080

51/8

W1

00

.0K

20.0

K0

80

51

/8W

R6

GN

D

PV

CC

PV

CC

PV

CC

OU

T+

Re

d

OU

T-

Bla

ck

100

K/5

%0

60

3

R1

JP

2

100

K/5

%0

603

R3

SH

UT

DO

WN

C2

060

3C

OG

47p

fd/5

0V

47K

/5%

060

3

R9

GN

D

GN

D

10u

H/5

.8A

D12

8C

L2

12

10u

H/5

.8A

D12

8C

21

L1

SY

NC O

range

GN

D

PV

CC

PV

CC

HT

SS

OP

32

-DA

P

U1

DR

V5

95

DA

P

Po

werP

AD

GN

D

PV

CC

HT

SS

OP

32-D

AP

U1

DR

V5

95

DA

P

9

32

31

30

29

27

26

22

24

23

21

20

19

18

3 8 16

15

14

13

12

11

10

765421

17

28

25

Red

IN+

Bla

ck

IN-

100

K/5

%0

60

3

R8

100

K/5

%0

603

R4

JP

1P

VC

C

R10

060

3D

NP

PV

CC

GN

DDN

P060

3

R11

PV

CCG

ND

GN

D

100

K/5

%0

603

R2 R

7

060

31

00

K/5

%

AN

AL

OG

OU

TP

UT

S

DN

P

DN

P

AN

AL

OG

INP

UT

S

PO

WE

RS

UP

PL

Y

FR

EQ

UE

NC

YS

EL

EC

TIO

N

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

DEVICE INFORMATION

TYPICAL APPLICATION

Figure 13. Schematic

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Product Folder Links: DRV595

7

8

9

10

GVDD

GAIN/SLV

GND

12

2 1

51 kΩR2

51 kΩR1

10 ms

PVCC

AVCC

IN– / IN+

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

START-UP SEQUENCING

To ensure proper operation on power up, wait 10ms after PVCC and AVCC are stable before using the analoginputs, IN– and IN+. Figure 14 illustrates this sequence.

Figure 14. Start-Up Sequencing (1)

(1) NOTE: The timing relationship between PVCC assertion and AVCC assertion is not critical.

GAIN SETTING AND MASTER / SLAVE

The gain of the DRV595 is set by the voltage divider connected to the GAIN/SLV control pin. Master or slavemode is also controlled by the same pin. An internal ADC is used to detect the 4 input states. The first four statesset the DRV595 in Master mode with gains of 20, 26, 32, 36 dB respectively, while the next four states set theDRV595 in Slave mode with gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-upand cannot be changed while the device is powered. Table 1 shows the recommended resistor values for eachmode and gain combination:

Table 1. GAIN and MASTER/SLAVE

MASTER / SLAVE GAIN R1 (to GVDD) R2 (to GND) INPUT IMPEDANCEMODE

Master 20 dB OPEN 20 kΩ 60 kΩMaster 26 dB 100 kΩ 20 kΩ 30 kΩMaster 32 dB 100 kΩ 39 kΩ 15 kΩMaster 36 dB 75 kΩ 47 kΩ 9 kΩSlave 20 dB 51 kΩ 51 kΩ 60 kΩSlave 26 dB 47 kΩ 75 kΩ 30 kΩSlave 32 dB 39 kΩ 100 kΩ 15 kΩSlave 36 dB 16 kΩ 100 kΩ 9 kΩ

In Master mode, the SYNC terminal is an output, in Slave mode, the SYNC terminal is an input for a clock input.TTL logic levels with compliance to GVDD.

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INPUT IMPEDANCE

The DRV595 input stage is a fully differential input stage and the input impedance changes with the gain settingfrom 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance ofthe input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ.

Table 2. Recommended Input AC-Coupling Capacitors

GAIN INPUT IMPEDANCE

20 dB 60 kΩ26 dB 30 kΩ32 dB 15 kΩ36 dB 9 kΩ

START-UP/SHUTDOWN OPERATION

The DRV595 employs a shutdown mode of operation designed to reduce supply current (Icc) to the absoluteminimum level during periods of non use for power conservation. The SDZ input terminal should be held high(see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low willput the outputs to Hi-Z and the amplifier to enter a low-current state. It is not recommended to leave SDZunconnected, because amplifier operation would be unpredictable.

GVDD SUPPLY

The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supplythe GAIN/SLV voltage divider. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The GVDD supply isnot intended to be used as an external supply. It is recommended to limit the current consumption by usingresistor voltage dividers for GAIN/SLV of 100 kΩ or more.

BSP AND BSN CAPACITORS

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for thehigh side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for atleast 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuitdiagram in Figure 13.) The bootstrap capacitors connected between the BSx pins and corresponding output pinsfunction as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During eachhigh-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

DIFFERENTIAL OR SINGLE-ENDED INPUTS

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. Touse the DRV595 with a differential source, connect the positive lead of the signal source to the IN+ input and thenegative lead of the signal source to the IN– input. To use the DRV595 with a single-ended source, use avoltage divider to bias IN- to 3.0V, and apply the single-ended signal to IN+.

Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: DRV595

> 1.4sec

mP DRV595

SDZ

Hi-Z

FAULTZ

SDZ

Hi-Z

FAULTZ

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

DEVICE PROTECTION SYSTEM

The DRV595 contains a complete set of protection circuits carefully designed to make system design efficient aswell as to protect the device against permanent failures due to short circuits, overload, over temperature, andunder-voltage. The FAULTZ pin will signal if an error is detected according to the fault table below:

Table 3. Fault Reporting

TRIGGERING CONDITION LATCHED/SELF-FAULT FAULTZ ACTION(typical value) CLEARING

Over Current Output short or short to PVCC or GND Low Output high impedance Latched

Over Temperature Tj > 150°C Low Output high impedance Latched

Under Voltage on PVCC < 4.5V – Output high impedance Self-clearingPVCC

Over Voltage on PVCC > 27V – Output high impedance Self-clearingPVCC

SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

The DRV595 has protection from over current conditions caused by a short circuit on the output stage. The shortcircuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a highimpedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZpin through the low state.

If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to theSDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the short-circuit protection latch.

Figure 15. Timing Requirement for SDZ

THERMAL PROTECTION

Thermal protection on the DRV595 prevents damage to the device when the internal die temperature exceeds150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds thethermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault.

Thermal protection faults are reported on the FAULTZ terminal as a low state.

If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZpin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermalprotection latch.

DRV595 MODULATION SCHEME

The DRV595 has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSELpin.

MODSEL = GND: BD-modulation

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Product Folder Links: DRV595

OUTP

OUTN

OUTP–OUTN

Load Current

Load Current

Load Current

OUTP

OUTN

OUTP–OUTN

OUTP

OUTN

OUTP–OUTN

0V

0V

PVCC

No Output

Positive Output

Negative Output

0A

0A

0V

–PVCC

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

This is a modulation scheme that allows for smaller ripple current through the TEC load. Each output switchesfrom 0 volts to the supply voltage. With no input, OUTP and OUTN are in phase with each other so that there islittle or no current in the load. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% forpositive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negativeoutput voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing theswitching current, which reduces any I2R losses in the load.

Figure 16. BD Mode Modulation

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Product Folder Links: DRV595

OUTP

OUTN

OUTP–OUTN

Load Current

Load Current

Load Current

OUTP

OUTN

OUTP–OUTN

OUTP

OUTN

OUTP–OUTN

0V

0V

PVCC

No Output

Positive Output

Negative Output

0A

0A

0V

–PVCC

DRV595

SLOS808A –DECEMBER 2012–REVISED MARCH 2013 www.ti.com

MODSEL = HIGH: 1SPW-modulation

The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penaltyin ripple current and more attention required in the output filter selection. In 1SPW mode the outputs operate at~15% modulation during idle conditions. When an input signal is applied one output decreases and oneincreases. The decreasing output signal quickly rails to GND at which point all the modulation takes placethrough the rising output. The result is that often only one output is switching. Efficiency is improved in this modedue to the reduction of switching losses. The resulting output signal at each half output has a discontinuity eachtime the output rails to GND. This can cause ringing in the output filter unless care is taken in the selection of thefilter components and type of filter used.

Figure 17. 1SPW Mode Modulation

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TA TJ θJA PDISS

PDISS IOUT2 rDS(on), total

DRV595

www.ti.com SLOS808A –DECEMBER 2012–REVISED MARCH 2013

POWER DISSIPATION AND MAXIMUM AMBIENT TEMPERATURE

Though the DRV595 is much more efficient than traditional linear solutions, the power drop across the on-resistance of the output transistors does generate some heat in the package, which may be calculated as shownin Equation 5:

For example, at the maximum output current of 3 A through a total on-resistanceof 60 mΩ (at TJ = 25°C), the power dissipated in the package is 1.1 W. (5)

Calculate the maximum ambient temperature using Equation 6:

(6)

PRINTED-CIRCUIT BOARD (PCB LAYOUT)

It is necessary to take care when planning the layout of the printed circuit board. The following suggestions willhelp to meet EMC requirements.• Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC

and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors shouldbe placed near the DRV595 on the PVCC supplies. Local, high-frequency bypass capacitors should beplaced as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly foran excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality tothe PVCC connections at each end of the chip.

• Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected atthe IC GND, which should be used as a central ground connection or star ground for the DRV595.

For an example layout, see the DRV595 Evaluation Module (DRV595EVM) User Manual. Both the EVM user'smanual and the thermal pad application report are available on the TI Web site at http://www.ti.com.

spacerREVISION HISTORY

Changes from Original (December 2012) to Revision A Page

• Changed Title From: 15V/±3A High-Efficiency PWM Power Driver To: 15V/±4A High-Efficiency PWM Power Driver ....... 1

• Changed Feature From: ±3 A Output Current To: ±4 A Output Current .............................................................................. 1

• Changed the Over current trip point TYP value From: 3 A To: 7.5 A ................................................................................... 6

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PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

DRV595DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV595

DRV595DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV595

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DRV595DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DRV595DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2013

Pack Materials-Page 2

http://www.ti.com/lit/slma002

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