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8254 Timer/Counter

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8254 Timer/Counter

Programmable interval counter

The Intel 8254 is a programmable counter /

timer chip designed for use as an Intel

microcomputer peripheral.

It uses N-MOS technology with a single +5V

supply and is packaged in a 24-pin plastic DIP.

It is organized as 3 independent 16-bit

counters, each with a counter rate up to 2 MHz.

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Block diagram of 8254

D0-D7 Data bus

CLKn Clock gate inputs

GATEn Counter gate input

OUTn Counter output

RD Read

WR Write

CS Chip select

A0-A1 Counter select

Vcc/GND +5 V supply / Ground

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1. Data bus buffer:-

Bidirectional 8 bit data bus buffer and is used to

interface 8254 data bus with system bus2. Read/write logic:-

used for read and write operation

3. CS-Chip select4. counters:-

Three independent 16 bit down counters. Eachcounter is having 2 input i.e. CLK and GATE

CLK is used as an input to counter

GATE is used to control the counter.

Counter gives output on OUT pin

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5. Address lines A0 and A1 :-

A1 A0 Selection

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control word register

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Control word register format

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Read back command:-

Powerful command which allows the user tocheck the count value , programmed mode

and current mode and current status of the

counter

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Mode 0:-Interrupt on Terminal Count

In this mode, the counter will start counting from the

initial COUNT value loaded into it, down to 0. Countingrate is equal to the input clock frequency.

Mode 1:-Hardware-Triggered One Shot

In this mode 8254 can be used as mono-stable multi-

vibrator.GATE input is used as trigger input.

OUT will be initially high. OUT will go low on the CLKpulse following a trigger to begin the one-shot pulse,

and will remain low until the Counter reaches zero.OUT will then go high and remain high until the CLKpulse after the next trigger.

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Mode 2 (X10): Rate Generator

In this mode, the device acts as a divide-by-n

counter, which is commonly used to generate areal-time clock interrupt.

Mode 3 (X11): Square Wave Generator

This mode is similar to mode 2. However, the

duration of the high and low clock pulses of theoutput will be different from mode 2.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the

output will remain high until the counter reacheszero. The counter will then generate a low pulse for1 clock cycle (a strobe) - after that the output willbecome high again.

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Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, thecounting process is triggered by the GATE input.

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Applications:-

Used for controlling real-time events such as

real-time clock, events counter, and motor

speed and direction control

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Interfacing of 8254 with 8085

8254 interfacing in I/O mapped I/O

In I/O mapped I/O scheme the address

of the I/O ports is of 8 bits. The A0-A7 contents

are copied on A8-A15

A15/7 A14/6 A13/5 A12/4 A11/3 A10/2 A9/1 A8/0 Operations

0 0 Counter 0

0 1 Counter 1

1 0 Counter2

1 1 Control register

Used to enable

the decoder

Used as input to

decoder

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A15/7 A14/6 A13/5 A12/4 A11/3 A10/2 A9/1 A8/0 Operations Port address

0 1 1 0 1 0 0 0 Counter 0 68H

0 1 1 0 1 0 0 1 Counter 1 69H

0 1 1 0 1 0 1 0 Counter2 6AH

0 1 1 0 1 0 1 1 Control register 6BH

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8254 interfacing in I/O mapped I/O

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8254 interfacing in memory mapped

schemeA15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Port

sel.

1 0 0 1 0 0 0 Counter

0

1 0 0 1 0 0 1 Counter

1

1 0 0 1 0 1 0 Counter

2

1 0 0 1 0 1 1 Control

register

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