12×12 multiplier reduction (dsd)
DESCRIPTION
Reduction techniques for multipliersDigital system DesignTRANSCRIPT
ABBOTTABAD Assignment#02
Subject: Digital System Design
Submitted By: Naveed Mazhar FA09-BEE-143
Submitted To:
Sir Shahid Nawaz
Date: 31st October, 2012
1-Carry-Save Reduction The 12×12 Multiplier reduction using Carry-Save technique is shown step by step in
following figure:
Result: The Figure shows that
(I) No. of Full Adders = 109
(II) No. of Half Adders = 11
(III) Time Delay in reduction = 10 (F.A.)
2-Dual Carry-Save Reduction
Result: The Figure shows that
(I) No. of Full Adders = 104
(II) No. of Half Adders = 21
(III) Time Delay in reduction = 6 (F.A.)
3-Wallace Reduction Tree
Result: The Figure shows that
(I) No. of Full Adders = 102
(II) No. of Half Adders = 34
(III) Time Delay in reduction = 5 (F.A.)