12×12 multiplier reduction (dsd)

5
ABBOTTABAD Assignment#02 Subject: Digital System Design Submitted By: Naveed Mazhar FA09-BEE-143 Submitted To: Sir Shahid Nawaz Date: 31st October, 2012

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Reduction techniques for multipliersDigital system Design

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Page 1: 12×12 Multiplier reduction (DSD)

ABBOTTABAD Assignment#02

Subject: Digital System Design

Submitted By: Naveed Mazhar FA09-BEE-143

Submitted To:

Sir Shahid Nawaz

Date: 31st October, 2012

Page 2: 12×12 Multiplier reduction (DSD)

1-Carry-Save Reduction The 12×12 Multiplier reduction using Carry-Save technique is shown step by step in

following figure:

Page 3: 12×12 Multiplier reduction (DSD)

Result: The Figure shows that

(I) No. of Full Adders = 109

(II) No. of Half Adders = 11

(III) Time Delay in reduction = 10 (F.A.)

Page 4: 12×12 Multiplier reduction (DSD)

2-Dual Carry-Save Reduction

Result: The Figure shows that

Page 5: 12×12 Multiplier reduction (DSD)

(I) No. of Full Adders = 104

(II) No. of Half Adders = 21

(III) Time Delay in reduction = 6 (F.A.)

3-Wallace Reduction Tree

Result: The Figure shows that

(I) No. of Full Adders = 102

(II) No. of Half Adders = 34

(III) Time Delay in reduction = 5 (F.A.)