12101121.docx
TRANSCRIPT
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Given: A MIPS-based computer system with 2 GB of main memory that is built on a sinle
circuit board! It is desined with a sinle control sinal between the "P# chip and main memory$
i!e! one bit of control that is set to one for %ead operations and &ero for 'rite operations!
a( )ow many bits wide is the main memory data bus*
b( )ow many bits wide is the main memory address bus when +-ban,s memory interleaved is
used*
c( )ow lon does it ta,es to fetch words from the memory to MIPS reisters usin the memory
confiuration in .b(* Assume that one cycle is re/uired to place the address and one cycle to
transfer one word and 01 cycles for memory access!
d( ind the memory bandwidth and compare it to memory bandwidth when no memory
interleaved is used
Answer:
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"omin to the concept of time ta,en by the system to access the data$ read the data and write it
bac, to the system$ we need to consider all the re/uired parameters such as$ the time re/uired to
read a bloc, of word$ to write the bloc, of word and the interleavin used!
3he interleavin is used to minimise the read and write access! In this process the memory is
divided into the individually different chun,s to process out the operation of its own word!
Accordin to the problem iven$ we assume that each read and write operation ta,es one cycle!And in addition we have used + ban,s of memory for interleavin!
Initially$ without interleavin$ time re/uired was .040401( 506 cycles7word!
i!e 8ne cycle to place the address$ one cycle to transfer one word and 01 cycles for memory
access!
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9ow$ y the concept of interelavin the time re/uired would be:-
0 4 01 4 2 .+ 0( 5 2+ cycles!
As per the /uestion as,ed$ + ban,s of memory interleavin is used$ and altoether we hav to
transfer word of data$ therefore the formula has been modified above!
3hus$ the total time re/uired to fetch words would be 2+ cycles
a( data bus was bits wide
b(;0 bits wide
c(it will ta,e 2 sec to fetch words from the memory
d( the difference is 20 bits when compared no memory is interealved