12 vlsicad timing
TRANSCRIPT
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VLSI CAD:Logic to Layout
Rob A. RutenbarUniversity of Illinois
Lecture 12.1
ASIC Timing:Basics
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Our Topics for ASIC TimingLogic-side
Static Timing Analysis How do we estimate the worst-case
timing through a logic network?
Layout-side Interconnect Delay Analysis
We place the gates, route the wires:how do we estimate wire delays?
Slide 3
t=0
V
V
V
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ASIC Timing: Logic SideLogic-side
Static Timing Analysis How do we estimate the worst-case
timing through a logic network?
Slide 4
All problems look like longest(or shortest) paths through a
graphthat properly modelsthe gates, and (maybe) the wires
Surprisingly the maze routing
idea reappears, in a very nice way
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Our Topics for ASIC Timing Layout-side Interconnect Delay Analysis
We place the gates, route the wires:how do we estimate wire delays?
Slide 5
t=0
V
V
V
The problem starts as anelectrical circuit model
(This is unavoidable)
However, we skip circuit details,and just show key results
Surprisingly it all turns into
another computational walkon another special tree!
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VLSI CAD:
Logic to Layout
Rob A. RutenbarUniversity of Illinois
Lecture 12.2
ASIC Timing:Logic-Level Timing:
Basic Assumptions & Models
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Timing Analysis at the Logic Level Goal: Verify timing behavior of our logic design
I give you a gate-level netlist I give you sometiming modelsof the gates and (after place/route) the wires too You tell me:
When signals arriveat various points in the network Longest delays through gate network Does the netlist satisfythe timing requirement? If not whereare key problems?
This is surprisingly complicated in the real world...Slide 7
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Acknowledgements Early versions of this lecture used material from:
Karem Sakallah (U Michigan) and Tom Szymanski(AT&T Bell Labs) This version of lecture has benefited extensively by inputs from
David Hathaway(IBM Essex Junction, VT) Aside: Hathaway is the principal designer of Einstimer, IBMs static timing tool Current version also benefited from versions my VLSI CAD lectures taught jointly by
John Cohn (IBM) and Dave Hathaway(IBM) at University of Vermont Dept of EE.
Manythanks to Karem, Tom, John, and especially Dave for allthe inputs on this material
Slide 8
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Analyzing Design Performance Assume design is synchronous
All storage is in explicit sequential elements, eg, flip-flop elements Consequence: for us, we can just focus on delays through combinations gates
Combinational
Logic
(No feedbackloops)F
lipF
lops
F
lipF
lops
CommonClock
Slide 9
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Question: Cant We Just Simulate Logic? What logic simulation does
Determine hows a system will behave, simulates the logical function Gives the most accurate answer (with good simulation models) !but it is (practically) impossible to give a complete answer especially timing
Requires examination of an exponential number of cases All possible input vectors ! With all possible relative timings ! Under all possible manufacturing variations !
We need a different, faster solution...Slide 10
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Timing Analysis: Gate Delay Models First: we need a model of delaythrough each logic gate
Slide 12
network delay == ?
Gate delay !== ?
!
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In Real World: This isAmazinglyComplex
Slide 13
Gate typeaffects delay
! !"
Gate loadingaffects delay
! !"
Waveform shapeaffects delay
! !"
Transition directionaffects delay
! !"
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Our Model: Pin-to-Pin Delay This lecture, keep it simple: Fixed, pin-to-pin delay model
No slopes, electricity, distributions. Loading effects pushed back into gate delay itself Per-pin delays are essential, but well usejust 1 value per gate, for simplicity
Turns out this is enough to see all the interesting algorithm ideas
Slide 15
!=3
!=3
!=4.1
!=4.1
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Next: Do We Consider Logical Function? Does this matter? Try an example, where we erase gates
In this example: PI= Primary Input, PO= Primary Output
Slide 16
!=8
!=1
!=2
!=8
!=1
!=2
!=1
PI
PI
PI
PO
Longest delay is
8+2+8+2=20
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Now, Suppose We Know Logic Gates
Slide 17
You cannot sensitizethis path: cannot make a logic change atthis input propagate down this path to change this output
!=8
!=1
!=2
!=8
!=1
!=1
PI
PI
PI
PO
2:1 mux 2:1 mux
0
1!=2
0 0Conflict!1
0
1
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Topological vs Logical Timing Analysis When we ignore logic, this is called Topological Analysis
We only work with the graph and the delays dont consider the logic We can get wrong answers: what we found was called a False Path
Going forward: weignore the logic (Too tough to deal with) Assume that all paths are statically sensitizable
Means: Can find a constant pattern of inputs to otherPIs that makes someoutput sensitive to some input
Reminder: this is exactly the Boolean Differenceconcept of sensitivity
This timing analysis has a name: Static Timing Analysis (STA)Slide 18
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VLSI CAD:
Logic to Layout
Rob A. RutenbarUniversity of Illinois
Lecture 12.3
ASIC Timing:Logic-Level Timing:
STA Delay Graph,ATs ,RATs, and Slacks
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Delay Graph Common convention: Add Source / Sinknodes
Add 1 source (SRC)node that has a 0-weight edge to each PI Add1 sink (SNK)node with 0-weight edge from each PO Why do this?
Now, the network has exactly 1 entry node, and 1 exit node All the longest (or shortest) path question have same start / end nodes
Slide 21
a
d
c
b
e
2
2
3
3
SNK0SRC
0
0
0
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Representation: Delay Graph What about interconnectdelay?
Can still use delay graph: model each wire as a special gate that just has a delay
Slide 22
PI=a
PI=b
c
PI=d
ex
y
w
z
q=PO
!=2 !=3
!=1.2
!=1.6
!=1.5
!=1.0
!=1.8
a
d
c
b
e
x
y
w
z
qSRC
0
0
SNK0
0
1.2
1.6
2
2
1.5
1.0
31.8
3
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So how do we use this graph to do timing analysis? What we do notdo: Try to enumerateall the source-to-sink paths Why not? Exponential explosion in number of paths, even for small graph
Theres a smarter answer: Node-orientedtiming analysis Find, for each nodein delay graph, worstdelay to the node along any path
Operations on Delay Graph
Slide 23
0 1 2 3 n
How manypaths from
0 to n? 2n!
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Define Values on Nodes in Delay Graph Slackat node n: Slack(n) = RAT(n) AT(n)
Amount of timing margin for the signal: positive is good, negative is bad Determined by longest path through node Amount by which a signal can be delayed at node and not increasethelongest
paththrough the network Can increase delayat node (to minimize power, circuit area) with positive slackand
notdegrade overall performance
Slack(n) = RAT(n) - AT(n)
Slide 25
SRC SNKn
other paths
ATs RATs
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Slack is HugelyImportant in Timing Analysis About slacks
Defined so negative slack alwaysbad --, it indicates a timing problem Measures sensitivity of network to this nodes delay
Positive slack Good: I can change something at this node, and not hurt networks overall timing Example: I can make this node slower, maybe save some power, not hurt timing
Negative slack Bad: I have problem at this node; more negative the slack, bigger the problem Looking for a node to fix to help timing? These nodes are where to look first.
These affect my critical paths the most
Slide 26
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How To Compute ATs? Recursively
succ(n)
Slide 27
SRC SNKn
-
p
-
-
s
-
!(p,n)
pred(n)predecessors of n
predeces
sor
paths
AT(n) = maximum delay to n=
0 if n== SRC
MAX AT(p) + !(p,n) elsep pred(n)
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A Quick Concrete AT Example
Big idea If we know the longest path to each predecessor of n, its a simple Maximum
operation to compute the longest path to nitself. (Yes, its just Dijkstra again!)
MAX { AT(x) + !(x,n)}x {p, q, r}
= MAX {5+7, 10+1, 5+5 }
= 12
Slide 28
n
p
q
r
SRC
!=7AT(p) =5
!=1AT(q)=10
!=5AT(r)=5
AT(n) =
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How To Compute RATs? Recursively
pred(n)
predeces
sor
paths
Slide 29
SRC SNKn
-
p
-
-
s
-
!(n,s)
succ(n)successors of n
RAT(n) =
Latest timein cycle
where ncould changeand signal would still
propagate to sink
before end of cycle
Cycle Time if n== SNK
MIN RAT(s) - !(n,s) elses succ(n)
=
Cycle Time
CLOCK
RATsare
defined relative
to clock cycle
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ATs versus RATs: Look at Clock Cycle Why the differences between AT and RAT definitions?
Slide 30
Cycle Time if n== SNK
MIN RAT(s) - !(n,s) elses succ(n)
0 if n== SRC
MAX AT(p) + !(p,n) elsep pred(n)
AT(n) RAT(n)
AT(n)
AT: longestlogicdelay after launch
edge of clock
RAT(n)RAT: longest logicdelay to the capture
edge of clock, but it isexpressed relativeto
the Cycle TimeCLOCK: Cycle TimeLaunch
Capture
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Signal arrives too late,and there is too much
delay from node to output
Signal does not arrive atflip flip input before the
capture edge of clock
Bad Things Happen When We See THIS SLACK = RAT AT = Negative
Slide 31
AT(n)
RAT(n)
CLOCK: Cycle Time
LaunchEdge
CaptureEdge
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VLSI CAD:
Logic to Layout
Rob A. RutenbarUniversity of Illinois
Lecture 12.4
ASIC Timing:Logic-Level Timing:
A Detailed Example,and the Role of Slack
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Lets Do a Bigger Example Delays are on edges; let clock cycle be 12
Compute the min/max delays by eye for now AT=longest path from SRC TO node; RAT=(cycle time 12) (longest path FROM node to SNK) Slack= RAT - AT
Slide 33
Cycle=12
1
4
1
2 3 5
2
315
3 2
4SNKSRC
0
0
0 0
0
0
PIs POs
a
b
c
d
e
f
g
h
j
k
n
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Lets Do a Bigger Example: ATs
Slide 34
Cycle=12
1
4
1
2 3 5
2
315
3 2
4SNKSRC
0
0
0 0
0
0
PIs POs
AT RAT slack = (RAT AT)
Compute ATs fromSRC toSNK
0
0
0
0 6
1
2
4
10
12
7
15
15f
a
b
c
d
e
g
h
j
k
n
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Lets Do a Bigger Example: ATs
Slide 35
Cycle=12
1
4
1
2 3 5
2
315
3 2
4SNKSRC
0
0
0 0
0
0
PIs POs
AT RAT slack = (RAT AT)
0
0
0
0
1
6
2
4
10
12
7
15
15
Compute RATs fromSNK toSRC
12
12
12
12
10
7
3
-2
4
-3
-1
2
-3a
b
c
d
e
g
h
j
k
n
f
Bug fix:RAT=+2,
not -2
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Lets Do a Bigger Example: Slacks
Slide 36
Cycle=12
1
4
1
2 3 5
2
315
3 2
4SNKSRC
0
0
0 0
0
0
PIs POs
AT RAT slack = (RAT AT)
0
0
0
0
1
6
2
4
10
12
7
15
1512
12
12
12
10
7
3
-2
4
-3
-1
2
-3 -3
-3
-1
2
-3
2
-3
6
-3
5
0
-3
-3
Worst (most negative slack) is -3. Trace worst path, SRC!SNK
a
b
c
d
e
g
h
j
k
n
f
Bug fix:RAT=+2, and
Slack=+2also
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Analyzing this Example Look at those slacks
A negative slack at an output (PO) means a missedrequirement A negative slack on internal node nmeans it feedsa problem PO
So, there is a path from nto some problem PO
Big result: the negative slackappears along this entire worst path Your worsttiming violation at an output (PO) = the most negative slackvalue You can always tracea path with this slack value back to a PI
So, slacks are hugely useful Beyond just knowing what is the worst path; slackstell us problem gates on this pathSlide 37
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VLSI CAD:
Logic to Layout
Rob A. RutenbarUniversity of Illinois
Lecture 12.5
ASIC Timing:Logic-Level Timing:
Computing ATs, RATs,Slacks, and Worst Paths
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Answer this: What are all the too-slow paths that violate timing? Most useful answer:
Report paths in order, fromslowest to fastest
In other words: Enumeratethese paths, in delay order
The Most Typical STA Problem
Slide 39
Logic
FlipF
lops
FlipF
lop
s
1 ns
CLOCK
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What Do We Need? Calculate all the ATs Calculate all the RATs Calculate all the Slacks #do all of this very efficiently: Delay graphs are huge!
#the enumeratethe violating paths, in worst delay order
Slide 40
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Computational Strategy One approach: Topological sortingthe delay graph
Sort the vertices in the delay graph into one single ordered list Essential property: if there is an edge ps, pappears beforesin sorted order
Compute ATsby going forwardthrough the sorted list Compute RATsby going backwardthrough the sorted list
Legal Topological Sort OrdersSRC,B,D,C,E,SNK
SRC,B,C,D,E,SNK
SRC,B,C,E,D,SNKSRC,C,B,D,E,SNK
SRC,C,B,E,D,SNK
Slide 41
B D
SNK
EC
SRC
3
5
6
159
11
4
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Topological Sorting (Topsort) Pretty easy application of depth-first-search (DFS)
Slide 42
From: Wikipedia: Topological Sorting
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Assume Have Topsort: Compute ATs
computeATs() {
AT(SRC) = 0;
foreach( nin topsort order ) {
AT(n)= -";
foreach( nodepin pred(n)) {
AT(n)= max( AT(n), AT(p)+ !(p,n));}
}
Slide 43
pred(n)predecessors of n
succ(n)
predeces
sor
paths
successorpaths
SRC SNKn
-
p
-
-
s
-
!(p,n)
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computeRATs() {
RAT(sink)= CycleTime;
foreach (node nin reversetopsort order ) {
RAT(n)= ";
foreach (successor sin succ(n))
RAT(n) = min( RAT(n), RAT(s) - !(n,s));}
}
Computing RATs Trick:
Pretend all edges are reversed,they point from SNK to SRC,
and walk graph backwards
Slide 44
pred(n) succ(n)successors of n
predeces
sor
paths
successorpaths
SRC SNKn
-
p
-
-
s
-
!(n,s)
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Using Slack For Path Reporting
Useful slack property: all nodes on longest path have same slack Surprising result: Let us find N worst paths, even though we did nottracethem allSlide 45
B D
SNK
EC
SRC
3
5
6
159
114
Slack=23-8=15
Slack=5-4=1
Slack=0
Slack=0
Slack=0
Slack=0
RAT=5 RAT=14
RAT=29
RAT=23RAT=3
RAT=0
AT=3 AT=8
AT=4 AT=14
AT=29AT=0
Cycle=29
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Worst Case Path Reporting: ExampleHeap starts as
=
Slide 47
B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Heap
Minimum
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Worst Case Path Reporting: ExampleReach B,reach C
Slide 48
B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Heap
Minimum
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Worst Case Path Reporting: ExampleExpand SRC-BE, Reach SNK
with
so 1stworst path delay=29
Slide 50
B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Heap
Minimum
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B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Worst Case Path Reporting: ExampleExpand SRC-C, Reach E
Slide 51
Heap
Minimum
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B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Worst Case Path Reporting: ExampleExpand SRC-CE, Reach SNK
with
so 2ndworst delay is 28
Slide 52
Heap
Minimum
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B D
SNK
EC
SRC
3
5
6
159
11
4
Slack=15
Slack=1
Slack=0
Slack=0
Slack=0
Slack=0
Worst Case Path Reporting: ExampleExpand SRC-BD, Reach SNK
with
so 2ndworst delay is 14
Slide 53
Heap
Minimum
Note: only 3 possible pathsfrom source to sink in graph,
snd we found them correctlyin delay order!
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Static Timing Analysis: Summary STA is a very importantstep in design of complex ASICs
Its a critical sign offstep, which means: you dont get to fabricate unless you pass
Several big ideas Gate level delay models matter, and can be pretty complex in real world Logical #Topologicalpath analysis (which == STA) Build delay graph, calculate ATs, RATs, slacksrecursively Concept of slackis big: lets us locate worst paths, and problem gates on path Idea very like maze routing lets us find worst paths in delay order
Slide 54
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Static Timing Summary: Aside STA is a huge topic several things we did notcover
STA for sequential elements How do we model flip flops and latches, so we can verify, eg, that setup and hold
times are met? More tricks with the delay graph
Early mode versus late mode timing Our development was only so-called late modetiming, where we care about
longest path. Early modefocuses on shortest paths, and is critical for more
advanced timing optimizations, eg, with transparent latches
Incremental STA In practice, you change 10,000 gates out of 1,000,000 gates, you dont want to
redo the whole STA analysis. Advanced methods can update incrementally
Slide 55
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VLSI CAD:
Logic to Layout
Rob A. Rutenbar
University of Illinois
Lecture 12.6
ASIC Timing:Interconnect Timing:
Electrical Models ofWire Delay
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Interconnect (Wire) Delay Modeling The problem
You place the logicit puts the pins at a certain distance apart You route the wires, each wire has an input-to-output delay Wheredoes the delay come from? How accurately can wepredictthis delay? How efficiently can we modelthis delay for use in layout or synthesis or STA?
Slide 57
x
x
x
t=0
V
V
V
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Sources of Delay: Model 1 Delay = Finite speedsignal propagation through physical wires Model = Length
Delay proportional to length; shorter = better Analysis
Good: This is really easy, qualitatively OK Bad: Not quantitatively accurate, extremely crude
Slide 58
xx
x Delay $Bounding Box!X + !Y
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Sources of Delay: Model 2 Add: Delay affected by electrical circuit drivelimitations Model = Wire load
Delay proportional to length, fanout, capacitance of the driven pins Analysis
Good: Qualitatively better, not too hard to curve fit models from data Bad: Still focuses mostly on the pins, not on the wire; can be off bylots
Slide 59
xx
x
Delay = F ( bounding box !X + !X,size of driver gate, fanout,
capacitance of pins on driven gates, ...)
Fanout is 2, account for
loading due to 2 pins
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Sources of Delay: Model 3 Add: Delay comes from electrical loadingof the interconnectDepends critically on exact geometryof the wired net
Model = Electrical Circuit Interconnect must be modeled as a circuit, analyzed as a circuit
Slide 60
SiliconInsulator
First-level
metal wire At nanoscale, the
interconnect geometry
Is largerelative to
the devices themselves
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Interconnect Model: RC Trees Most popular interconnect model used in layout applications First: Interconnect Circuit
Slide 61
Silicon height d
W
L
H Metal
Metal wire has resistance = Rto current flowing down its length
current
Physics: R = $L / WH
ASIC: R = r L / W
We control
L, Wof a wire
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Aside: About Real Capacitance (Cap)! Note: this model is very simplistic
You really get capacitance between any pair of conducting surfaces So, in a multi-layer metal process you get Caps between all the layers Vertically adjacent conductors create Overlap Cap Laterally adjacent conductors (next to you or below you) create Fringe Cap
Slide 63
M4
M5
M3
Fringe capbetween2 adjacent wires
on the same layer
Overlap capbetween
2 adjacent wires onthe same layer
crosssection
view
Sidewall fringe capfromside of one layer
to the conductors below it
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Interconnect Models: RC Trees Typical circuit model: "model (pi model) Accounts for the resistance R and the capacitance Cof wire segment Symmetric (note: splitcapacitance in two halves); small model, only need 2numbers
Slide 64
Silicon
height d
W
L
H Metal
current
R = r L/W
C = (1/2) cWLC = (1/2) cWL
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From Wire Segments to RC Tree Big idea: Replace everystraight wire segment with pi model
Slide 65
Each wire
segment creates
its own RC circuit
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Using RC Trees for Interconnect Analysis Lots of nice Electrical Engineering detail we could do, now#
!except not everybody in the class has this circuits-oriented background
Useful thing about RC tree model It starts as a circuit! !but it turns into a simple treeobject And a special computational walkon tree gives us all the delay information we need! So, (almost) no circuitsfor us. Just the computational recipe for how to usetree
Slide 68
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This is It: RC Tree RC Tree general form Atree of resistors(no loops); capacitors hanging offall intermediate tree nodes Rootof tree is where signal is input; Leavesof tree are the driven outputs
Slide 69
RC Tree:drawn as a
circuit
a b
c
d
e
f R
RR
RR
C C
C
C C
C
RC Tree:drawn as a
grapha b
c
d
e
f
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RC Trees: Delay Estimation Missing circuits detail: need to model driver, drivengates Voltage source + resistoras input at root (this models drivinggate) Capacitor as loadat each leaf (each models a drivengate)
Slide 70
RR
R
R
RC C
C
C C
C
+-
t =0
V=1
V1
+
-
V2
+
-
V1
V2
Driving input
Driven load
a b
c
d
e
f
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Summary: Gates + Wires!
RC Tree
Slide 71
+
-
t =0
V=1
V1
Next: Use tree tocompute a delay
number for each
output of tree
V2
We get a uniquedelaynumber for
each output
RR
R
R
RC C
C
C C
C
a b
c
d
e
f
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RC Trees: The Elmore Delay Famous formula:
Elmore delay
Derived in 40s for circuits applications Resurrected in 80s by Penfield,
Rubenstein, Horowitz for RC trees
Very simple, very useful Easy computational recipe
Slide 72
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Elmore Delay !: Tree Walk Computing Recipe
Do this: Set != 0; walk down path of resistors from Rootto Leafwhere you want delay At each resistor, do != !+ R &(all capacitors downstream) Downstream capacitor = any Cthat is reachable in tree below this resistor
Slide 73
1
Ri = 2
2 1
1
314
1
13
5
Example: at Ri=2resistorin our RC tree,
the term we wouldadd to Elmoredelay!
on a tree walk through Ri
= 2'(2+1+1+1+3)
a b
c
d
e
f
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Elmore Delay !: Tree Walk Computing Recipe
Example: Set != 0; walk down path of resistors from Rootto Leafwhere you want delay At each resistor, do != !+ R &(all capacitors downstream)
Slide 74
1
2
2 1
1
314
1
13
5
Delay!= 0
+5(1+2+1+1+3+1)
+2(2+1+1+3+1)+4(1+3)
+1(3)
= 45+16+16+3= 80
a b
c
d
e
f
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Insight: Stream Analogy Think of RC tree like a branching stream, current like water Goal: You are downstream, trying to fill your bucket; how fastcan you fill it? Unfortunately, at everybranch point, somebody else has a bucket The farther you are downstream, the less water you get from upstream. What matters here?
Widthof the upstream branches. Sizeof all the other buckets
Slide 75
Water in(fixed, limited supply)
YOU
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Water!
Circuits
Slide 76
Water in
YOU
Driving gateWire capacitance Wire resistance
Current Driven gate
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Circuits Aside: What Is Elmore Delay? If you could model the path from input to an output as a simplified
circuit with exactly one R and one C, the best RC value = Elmore !
Slide 77
1
2
2 1
1
314
1
13
5
V(e)
+
-
V(e)Vin ( 1 - e
-t /!))
a b
c
d
e
f
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VLSI CAD:
Logic to Layout
Rob A. Rutenbar
University of Illinois
Lecture 12.8
ASIC Timing:Interconnect Timing:
Elmore Delay Examples
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Using the Elmore Delay The Elmore delay formulas are immenselyuseful
Simple enough for layout folks to use them in algorithms Accurate enough that they beat simple length-based schemes (Unfortunately, not so accurate that you can avoid later verification with what are
called higher order models that incorporate more than one time constant)
Applications Numerous! But for us: can take a real routed wire, and build a good delay model for STA
Slide 79
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Elmore Example
Simple tree with 4 leaf nodes Electrical parameters: r = 1 , c = 2 So, for each segment, total R = r L / W, C = c W L
W=1, L = 20
W=1, L = 5
W=1, L = 2
Slide 80
Remember: AddCs at eachnode in the tree! 3Cs to add
at this node!
a
b
c d
e f g h
R=1(5/1)
= 5
5=C/2
5=C/2
C=2(1*5)=10b
d
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Elmore Example
RC Tree for the interconnect alone Again: Remember to add up Cs hanging off each internal node of tree
Slide 81
W=1, L = 20
W=1, L = 5
W=1, L = 2
20
5 5
2 2 2 2
20
30
9 9
2 2 2 2
a
b
c d
e f g h
a
b
c d
e f g h
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Elmore Example Add driver and driven gates
2+1 = 3
Slide 82
20
5 5
2 2 2 2
20
30
9 9
W=1, L = 20
W=1, L = 5
W=1, L = 2
R0 = 20
Cload = 1
20
a
b
c d
e f g h
a
b
c d
e f g h
aa
aa
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Elmore Example: Compute Delay to Each Leaf
Since symmetric, only need to compute 1 pathRemember the recipe:
1. Set != 0, walk from root to leaf
2. At each R,!
+= R &(all Cs downstream)
Slide 83
3
20
5 5
2 2 2 2
20
30
9 9
20
3 3 3
!= 0+20(20+30+2*9+4*3)
+20(30+2*9+4*3)+5(9+2*3)
+2(3)= 2881
a
b
c d
e f g h
aa
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New Elmore Example What can layout(ie, placement, routing) do to wiring?
Change the lengthof a wire, or even the widthof a wire Try example: change Lon 1 segment
R=40
40=C/2
40=C/2
R & Cincreasefor longer wire
Slide 84
W=1, L = 20
W=1,L = 40
W=1, L = 2
R0 = 20
Cload = 1
b
d
b
d
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New Elmore Example OK, now what is delay to each leaf?
Slide 85
20
20
5 40
2 2 2 2
20
65
9 44
3 3 3 3
Right side:!=7606
Left side:
!=5681
Note:
Extra Cof longerwire also loadsthe
leftside of tree,increasing the delay
Left Right
a
b
c d
e f g h
aa
b
d
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New Elmore Example, version 2
How about instead we change W=widthon 1 segment?
Slide 86
W=1, L = 20
W=10, L = 5
W=1, L = 2
R0 = 20
Cload = 1
R smaller, C bigger
Left Right
Right side:!=6436
Left side:
!= 6481
a
b
c d
e f g h
aa
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Elmore Applications
Do people really use this delay metric? Yes! Timing verification
Can use this to give realistic wire delays, post layout, for final STA
During placement Estimate wire shape(eg, a simple Steiner) you can get very quickdelay estimate Analytical placers use to adjust weightson wires, coerce critical wires to be short
Slide 87
PIPI
PO! !!
!
!!
!
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Summary
Interconnect has a hugeimpact on chip speed Cannot ignore delays caused by the electical properties of real wires
Layout tools responsible for part of timing guarantee Upstream tools determine levels of logic, gate count, fanouts, etc Physical design tools responsible for how long the wires end up All of these impact wire length and distribution
Individual wires are today modeled as complex circuits RC tree is the most useful model; Elmore delay is easiest to compute There are sophisticated estimators beyond Elmore... Can use for both verification, and for layout optimizations (eg clock)
Slide 88