11/3/2004 EE 42 fall 2004 lecture 27 1

Lecture #27 MOS

• LAST TIME: NMOS Electrical Model– Describing the I-V Characteristics– Evaluating the effective resistance R– Switching behavior

• TODAY: NMOS physical structure: W and L and dox, PMOS

– Transistor Geometry and capacitance– Scaling of properties with size: ID and C

11/3/2004 EE 42 fall 2004 lecture 27 2

The circuit symbol

NMOS as a Switch - Summary

G

S

DID

N ChIDS

ID

VDS

VDD

The value of RDN is chosen to predict the correct timing delay.

Then we can essentially replace the transistor with the simple switch model (valid of course only for predicting timing delays).

Electrical Model

D

S

G

RDN

If VGS = 0.

ID for VGS = maximum (VDD)

We have an equation for ID in the saturation region.

11/3/2004 EE 42 fall 2004 lecture 27 3

For simple digital circuit calculations the MOS transistor will be

essentially off (VGS < VT ) or fully turned on (VGS = VDD ), the power

supply voltage).

In the saturation region we describe the variation of ID with VDS with the

empirical equation :

MOS “Theory”

VGS

SG

VDS

iD+ +-

D

ID = IDS X (1+ VDS)

IDS is the intercept with ID axis

is intercept with VDS axis) IDS is slope

IDS

ID

VDS

VGS = VDD

off

on

Then we can estimate the effective resistance in terms of and IDS

11/3/2004 EE 42 fall 2004 lecture 27 4

The effective resistance with VGS = VDD

The MOS transistor discharges C. (VDD to VDD /2)

As VOUT goes from VDD to VDD /2, the average voltage VDS is (3/4) VDD.

Since ID = IDS( 1+XVDS) The average current is IDS( 1+X(3/4)VDD) .

Using a resistance of this value we get discharge time estimate which is less than 4% different from the correct answer obtained by direct integration

-

VIN =3V VOUT+

-

DG

S

C+ -

IDS

ID

VDS

VGS = VDD

VGS = 0

VDDVDD/2

Thus the average effective resistance is the ratio:

(3/4) VDD / IDS( 1+X(3/4)VDD) = RDN

slope = 1/RDN

11/3/2004 EE 42 fall 2004 lecture 27 5

For simple digital circuit calculations the MOS transistor will be

essentially off (VGS < VT ) or fully turned on (VGS = VDD ), the power

supply voltage).

MOS I-V Characteristics in more detail

VGS

SG

VDS

iD+ +-

D

ID = IDS X (1+ VDS)

IDS

ID

VDS

VGS = VDD

off

on

But if VGS = VDD the value of IDS depends on VGS, so we need some more theory. In particular we want to:

1) Describe dependence of IDS on VGS and geometry

2) Describe the “break point” in VDS above which ID saturates.

11/3/2004 EE 42 fall 2004 lecture 27 6

A little more MOS “Theory”

We have two regions: the resistive region at smaller VDS and the saturation region at higher VDS .

ID

VDS

VGS

In the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturation

In the saturation we have a small gradual increase of I with VDS

VGS

SG

VDS

iD+ +-

D

We call the boundary between the regions VDSat.

VDSat

Now we wish to describe the dependence of the current on VGS

11/3/2004 EE 42 fall 2004 lecture 27 7

n

P

oxide insulatorn

drain

- +

source

gate

Below threshold

VGS < Vt

Below threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions

11/3/2004 EE 42 fall 2004 lecture 27 8

n

P

oxide insulatorn

drain

- +

source

gate

NMOS in the linear (Triode) region

VGS > Vt

If the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistor

The electrons move under the influence of the

Electric field at a velocity: ν=μE where E=volts/distance

And they must travel a distance L to cross the gate

Since the total charge is Q=CVgs, we will have a current

Id=μCgateVds (Vgs-Vth)/L2= μ(εox/dox)Vds (Vgs-Vth)W/L

11/3/2004 EE 42 fall 2004 lecture 27 9

n

P

oxide insulatorn

drain

- +

source

gate

NMOS with increasing Vds

VGS > Vt

As the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel

11/3/2004 EE 42 fall 2004 lecture 27 10

Saturation

• As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate

• When the voltage across the device at the drain end goes below threshold, the current is pinched off.

• If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source.

• These two effects cause a small region to form near the drain which limits the current. This is called saturation

11/3/2004 EE 42 fall 2004 lecture 27 11

n

P

oxide insulatorn

drain

- +

source

gate

NMOS in saturation

VGS > Vt

When the voltage from the source to the drain gets high enough, the channel gets “pinched” In the pinch region, the carriers move very fast, but the current is determined by the triangular region, which does not change much as the drain voltage is changed, so the current saturates

11/3/2004 EE 42 fall 2004 lecture 27 12

Submicron MOS

• In the last few years, transistors have become so small that some of these approximations are breaking down:

• As the transistors get short, the difference between the triode region and saturation has become blurred, with no clear saturation

• Because gate oxides are so thin, some current goes through the gate in a process called tunneling

• Sub-Threshold currents are increasing, causing the transistors to conduct a small amount even when they are supposed to be off.

11/3/2004 EE 42 fall 2004 lecture 27 13

MOS “Theory”, con’tIn the saturation region (VDS >VDSat ) all the curves are described by ID = IDS X (1+ VDS) but IDS is a function of VGS.

In modern devices the saturation current is proportional to (VGS-VT). The simple field effect gives us the idea for this proportionality: As we increase VGS there is some “threshold”, VT. above which electrons accumulate on the surface. The current is of course proportional to the number of these electrons, so it is proportional to (VGS -VT).

In figure below VT = 1V. Note that the current is proportional to (VGS -VT), for example the current at VGS =3V is double that at VGS =2V.The intercepts with the current axis (IDS) depends not only on the gate

voltage, but also on device geometry. We will next discuss how IDS depends on device geometry.

ID

VDS

VGS

VDSat1/

VGS = 4

VGS = 3

VGS = 2

11/3/2004 EE 42 fall 2004 lecture 27 14

NMOS TRANSISTOR STRUCTURE•NMOS = N-channel Metal Oxide Silicon Transistor

nP-type Silicon

oxide insulatorgaten

“Metal” gate (Al or Si)

W

L

Contact to Source

Contact to Drain

11/3/2004 EE 42 fall 2004 lecture 27 15

gate length

•The gate length, L, is the distance the electrons have to travel. It is generally set at the minimum value (eg .18 micron) for nearly all logic transistors

•As the gate length gets shorter, the gate capacitance gets smaller

•As the gate length gets shorter, the current drive of the transistor also gets larger.

•However, leakage current also increases

11/3/2004 EE 42 fall 2004 lecture 27 16

Gate width

•The gate width, W, is determined by the circuit designer. One uses a wider gate to get more current (and thus charge a capacitor faster). For example doubling W is the same as putting two equal-sized transistors in parallel, and thus doubles the current at any given voltage.

11/3/2004 EE 42 fall 2004 lecture 27 17

• The capacitance is proportional to W and L (for logic, mostly L is fixed, so in effect C is proportional to the gate width W that the designer chooses. It is inversely proportional to dOX .

nP-type Silicon

oxide insulatorgaten

“Metal” gate (Al or Si)

W

L

Contact to Source

Contact to Drain

• The gate is insulated from the rest of the transistors, but it has a substantial capacitance to the source as it builds up charge in the channel

dOX = oxide thickness

NMOS TRANSISTOR CAPACITANCE

11/3/2004 EE 42 fall 2004 lecture 27 18

MOS TRANSISTOR – TOP VIEW

Thin oxide

Gate (over oxide)

Drain contact

Source contact

What are device dimensions? Gate Length = L and is fixed for any technology. (Such as the .09-0.18 m technology in manufacturing today).

Gate Width = W and is selected by the circuit designer for the current required.

LW

The device current is proportional to W as well as (VGS -VT), so we express IDS as a constant times ( IDS' ) times W times (VGS -VT). ( Thus the units of the constant IDS' are A/V-m.) We multiply IDS' by the gate width W and by (VGS -

VT). to get the value of IDS in A.ID = IDS X (1+ VDS) and IDS = W X IDS' (VGS -VT).

Example: a “1/4m device” with IDS' = 75 A/V-m , W = 5m, = 0.02 V-

1, VT = 0.5V and in a circuit with VDD = 2.5V. If the device were 5m wide and the gate were at VDD then IDS = 5 X 75 (2.5 -0.5) = 750A.

11/3/2004 EE 42 fall 2004 lecture 27 19

MOS TRANSISTOR – TOP VIEW

Gate Capacitance: The dimensions of the capacitor are area = W X L and thickness = dOX . A typical value, say for “1/4 m” technology, is 5nm.

LGate (over oxide)

Drain contact

Source contact

W

The capacitance formula from physics is C=εA/d = W X L X OX / dOX.

The dielectric constant for oxide, OX, is 3.9 O = 3.45X10-13 f/cm.

If dOX = 5nm then OX / dOX =7fF/m2 of capacitor so C=7W X L (fF) with W and L in m.

Example: The same “1/4m device” device with, W = 5m. The gate capacitance is 5 X 0.25 X 7 fF = 8.6 fF.

11/3/2004 EE 42 fall 2004 lecture 27 20

VIN jumps from 0V to 3V

Controlled Switch Model of Inverter (Lect. 18)

If there is a capacitance at the output node (there always is) then VOUT responds to a change in VIN with our usual exponential form.

VOUT

t

Output whenVIN jumps from 3V to 0V

RN

+

--

VDD = 3V

VSS = 0V

VIN =3V

VOUT

+

--

VDD = 3V

VSS = 0V

VIN =0V RP

VOUT

3

0

This is what we use the NMOS for

11/3/2004 EE 42 fall 2004 lecture 27 21

Purpose of the NMOS Switch

The MOS transistor discharges C (some load).

The NMOS switch is great for discharging a node to ground. When VIN goes high (VDD ) then VOUT goes from VDD to ground. When it reaches VDD /2 we call that time the stage delay.

But we also need a switch to charge a node, i.e. bring it from ground up toward VDD . That’s where we need another type of transistor, the PMOS. It makes the ideal switch to charge the node.

-

VIN =3V VOUT+

-

DG

S

C+ -

IDS

ID

VDS

VGS = VDD

VDDVDD/2

11/3/2004 EE 42 fall 2004 lecture 27 22

NMOS circuit symbol

CIRCUIT SYMBOLS

G

S

D

A small circle is drawn at the gate to remind us that the polarities are reversed for PMOS.

PMOS circuit symbol

G

S

D

11/3/2004 EE 42 fall 2004 lecture 27 23

n

P

oxide insulatorn

drain

- +

source

gate

NMOS =device which carrier current using electrons but on the surface of a p-type substrate (p-type substrate

means that no electrons are available)

n

P

oxide insulatorn

drainsource N-MOS In this device the gate controls electron flow from source to drain.

(in the absence of gate voltage, current is blocked)

gate

VGS > Vt

If we increase gate voltage to a value greater than Vt

then a conducting channel forms between source and drain. (“Closed switch”)

11/3/2004 EE 42 fall 2004 lecture 27 24

CMOS = Complementary MOS(PMOS is a second Flavor)

n

P

oxide insulatorn

drainsource N-MOS

In this device the gate controls electron flow from source to drain.

The NEW FLAVOR! P-MOS

It is made in p-type silicon.

It is made in n-type silicon. (In n-type silicon no positive charges (“holes”) are normally around.)

In this device the gate controls hole flow from source to drain.

gate

source drain

n-type Si

P-MOSgate

p p

11/3/2004 EE 42 fall 2004 lecture 27 25

PMOS

The body is n-type silicon.

In this device the gate controls hole flow from source to drain.

source

drain

n-type Si p

gate

+ -

p

What if we apply a big negative voltage on the gate?

If |VGS |>|Vt | (both negative)

then we induce a + charge on the surface (holes)

source drain

n-type Si

P-MOSgate

p p

|VGS |>|Vt |

11/3/2004 EE 42 fall 2004 lecture 27 26

NMOS and PMOS Compared

NMOS“Body” – p-typeSource – n-typeDrain – n-type VGS – positive

VT – positive

VDS – positive

ID – positive (into drain)

PMOS“Body” – n-typeSource – p-typeDrain – p-type VGS – negative

VT – negative

VDS – negative

ID – negative (into drain)G

n nID

DS

p

B

G

p pID

DS

nB

ID

4321VDS

VGS=3V1 mA

VGS=0

(for IDS = 1mA)

4321VDS

VGS= 3V1 mA

VGS=0

ID

(for IDS = -1mA)

11/3/2004 EE 42 fall 2004 lecture 27 27

PMOS Transistor Switch Model

Operation compared to NMOS: It is complementary.

For PMOS for the normal circuit connection is to connect S to VDD (The function of the device is a “pull up”)

VG = VDD

Switch is open : Drain (D) is disconnected from Source (S) when VG = VDD

VG =0

Switch is closed: Drain (D) is connected to Source (S) when VG =0

G

S

D

VDD

VDD

Switch OPEN

VDD

G

S

D

V=0

Switch CLOSED

S

D

G

11/3/2004 EE 42 fall 2004 lecture 27 28

PMOS Model RefinementPMOS transistor has an equivalent resistance RDP when closed

The circuit symbol

G

D

S

P Ch

S

D

G

RDP

The Switch model

CGS

There is also a gate capacitance CGS, just as in NMOS

11/3/2004 EE 42 fall 2004 lecture 27 29

CMOS

Challenge: build both NMOS and PMOS on a single silicon chip

NMOS needs a p-type substrate

PMOS needs an n-type substrate

Requires extra process steps

oxide

P-Si n-well

p p n n

GDG DSS