11/11/2003 Update on Pomone 1

Update on Pomone

Dario Menasce, Stefano Magni, Lorenzo Uplegger

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Update on Pomone

• A new custom-built PCI driver has been implemented and tested. This makes the project completely Open Source compliant (no longer need for license, fully portable).

• Added CRL functionalities: entries into the CRL from run conditions can be entered automatically.

• Improved the error message handling: fatal errors or important conditions are now reported to user in popup windows as well as stored in the usual log file.

• A new utility has been added to browse the data archive and get basic information from already collected data.

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• The new driver has all the functionalities of the old WinDriver by Jungo.

• Its integration in our system has been seamless, since the driver class was designed as a virtual class from the beginning.

• Users can choose between the two drivers before compilation of the producer takes place (just define the environmental variable JUNGODRIVER or remove it).

• The driver works as expected, but we are still fully debugging ad fine tuning it to optimise performances.

• In particular, by fine tuning parameters of the kernel concerning I/O we were able to get a 30% increase in transfer rate

On Intel P6 family processors (Pentium Pro, Pentium II and later) the Memory Type Range Registers (MTRRs) may be used to control processor access to memory ranges. This is most useful when you have a video (VGA) card on a PCI or AGP bus. Enabling write-combining allows bus write transfers to be combined into a larger transfer before bursting over the PCI/AGP bus. This can increase performance of image write operations 2.5 times or more.

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Measured transfer rate:

• On an AMD Athlon processor (1.3 GHz) with a PTA card directly attached to the host PCI’s slot the read-out of this single card proceeds at 25 Mb/sec.

• On a somewhat slower AMD Athlon processor (1 GHz) and using a bus expander, just the read-out of a single PTA card significantly slows down 3.7 Mb/sec.

• Running the full system in a real environment, (1 GHz processor and bus-expander) including event-builder, we were able to sustain ~250 Kb/sec using two PCI cards

This is without taking advantage of the spill structure (idle period between spills wereonly the even-builder needs CPU cycles).

Assuming 2 bytes per hit and about 10 hits per track (event), we should be able to write events to disk at a rate of

250000 / 40 ~ 6250 events per second

Pixel07 is a 1.5 GHz dual processor; the above estimate is thus a conservative number

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Users can customize name and port ofthe server PC runningthe CRL.

Messages are sent as XML messagesthrough a network socket

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Whenever a run startsa popup window willaccept begin-runcomments as entriesto both the CRL andthe current data file.

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Error messages of fatal category alwaysresult in a popup window

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To do• Expand the number of messages to be sent to the CRL

automatically. Define a uniform syntax and establish priorities.

• Check the functionality of this procedure at MTEST with the real CRL (tested so far in Milano with nc instead of the real CRL)

• Take data

• Take data

• Take data