11 nocs 09 panel mike kishinevsky, sat chatterjee, umit ogras strategic cad labs, intel 13 may 2009

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1 NoCs 09 panel Mike Kishinevsky, Sat Chatterjee, Umit Ogras Strategic CAD Labs, Intel 13 May 2009

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Page 1: 11 NoCs 09 panel Mike Kishinevsky, Sat Chatterjee, Umit Ogras Strategic CAD Labs, Intel 13 May 2009

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NoCs 09 panel

Mike Kishinevsky, Sat Chatterjee, Umit Ogras

Strategic CAD Labs, Intel

13 May 2009

Page 2: 11 NoCs 09 panel Mike Kishinevsky, Sat Chatterjee, Umit Ogras Strategic CAD Labs, Intel 13 May 2009

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Message from the field

•Designers do NOT like the term Network-on-chip – Associate with high overhead of multi-layered protocols– Something bulky and inefficient– Do not understand how this is different from what they do

today and did yesterday– Perhaps more education is needed on both sides

•However “NoCs” are omnipresent in industrial chips– Just nobody calls them so

•The term used: “Communication Fabrics”

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What is a Communication Fabric?

• Part of the design that pushes data around

• Glue between different IP blocks

• Include not only wires, but also…– switches, arbiters, routers, buffers and queues, addressing logic,

logic managing credits, logic for cache coherency, starvation and deadlock prevention, clock and power down logic etc.

• Often has regular parts (e.g. ring or mesh topology), but need not be

Page 4: 11 NoCs 09 panel Mike Kishinevsky, Sat Chatterjee, Umit Ogras Strategic CAD Labs, Intel 13 May 2009

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What it is not

Communication Fabric Pages©

Communication Fabric pages are:    Durable    Washable    Available to fit two standard note book sizes.    Equipped with three metal, rust-proof grommets    Double Sided with VELTEX® Brand fabric

Page 5: 11 NoCs 09 panel Mike Kishinevsky, Sat Chatterjee, Umit Ogras Strategic CAD Labs, Intel 13 May 2009

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Many Communication Fabrics at Intel

• High-end interconnect– Connects cores in high-end chips– Implements cache coherence

• IO/Mem fabrics– PC MCH (Memory Control Hub), PCH, SCH

– Implements PCI-compatible memory-mapped IO– SOC chips

– System Interconnect – Memory Controller– Often simpler than PCI: no configuration, etc.

• Message fabrics– Power messages, sideband wires, etc. in

most designs– Don’t care about performance

Core i7-based

Platform

Atom-based Platform

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Canmore media processor SOC

Display Processing Engine

Graphics Engine

Audio & Video Decoder

IA Core

Pentium M 800M+

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Protocols and FabricsA typical communication stack spans multiple levels of abstraction

SoftwareSoftware

PCIe TLPCIe TL

On-die fabricOn-die fabric

Software level: IO/Mem Reads and Writes

Transaction level: Read/Write transactions and Completions

Link level: Cycle-by-cycle signaling protocol

More

Abst

ract

We can capture, analyze, verify at any of these levels of abstraction

• Higher levels are closer to distributed algorithms

• Lower levels are closer to micro-architecture (resources and latencies are important)

• When specify, validate and optimize link level cannot ignore transaction level (e.g. ordering requirements between Reads/Writes)

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Research Vectors

• Validation– Hard to get correct due to tricky distributed interaction

• Design space exploration– Wide range of product requirements– Need to explore fast and optimize well

• Communication fabrics are highly important design objects that are here today– Learn them– Focus on specification, validation, exploration, optimization– Dramatic protocol changes which would require large redesign

are risky; incremental changes are more easily acceptable– Show value on systems of today (i.e. products in 2-5 years)– Then move to systems of “tomorrow”, 1000 cores, etc

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Domain: MPSoC vs. CMPs• Traditional application domains

– MPSoCs target embedded domains with specific application requirements– CMPs target general purpose computing

• Trends– MPSoCs became more programmable (SoCs for media processing and

communication)– CMPs became more heterogeneous (MC and GPU integration).

Homogeneous “CMPs” do not exist

• Common– Need for high memory bandwidth– Power efficiency, display, system control

• Different– Aggressive optimization of MPSoCs based on application-specific information– More irregularity of MPSoCs– Tighter cost and time to market

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Workloads and over-hype of NoCs• We certainly over-hype “NoCs”, but we under-hype

importance of new design practices for communication fabrics

• E.g. – who in academic community works on verifying deadlocks and

livelocks for fabrics in presence of message dependencies?– who works on understanding the impact of communication on

floorplan and their co-design?

• We do see high demand on memory BW, but to comprehend the demand one needs to analyze protocol flows and message dependencies

• Significant memory BW growth per generation in Graphics

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Programming model and beneficiaries

•SW is longer and harder to develop then HW, hence only backward compatible programming models can survive

•Who would benefit from NoCs. We should not care

•What we should care about: how to improve design and validation practices for communication systems on and off die

•All systems will benefit from better on-chip

communication

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• Given: a class of communication fabric & message ordering constraints & flow control details

Prove: every message gets delivered

• Given: The number and sizes of IP blocks & communication requirements & message ordering constraints & flow control rates

Find: Optimal floorplans & communication fabrics in (perf, area, energy) space

Industrial benefits, benchmarking & education

• Benchmarking is useful if domain is well defined (e.g. SAT, logic synthesis, placement (but failed in timing driven for many years)). Need to carve sub-domains when clear. Need high-quality public domain infrastructures (think SIS)

• Education VLSI and CA graduates should be all trained to design and validate communication on chip. Preferably using new methods (not just another piece of RTL)

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NoCs in 2009– NoCs based on RF on die– NoCs based on wireless on die– NoCs based on photonics on die

Next big thing

NoCs in 2012 NoCs based on teleporting on die

First NoC based on quantum teleportation between light and matterThe New York Times, 13 May 2012

The concept of quantum teleportation - the disembodied complete transfer of the state of a quantum system to any other place - was for the first time used to demonstrate an on-die network-on-chip that delivers 500 ExaByte (500 1018 B) of memory bandwidth. A team of scientists headed by Prof. Com Fabric at the Teleporting International Institute demonstrated how their prototype Teleporting NoC can be used to beam three simultaneous streams of holographic 3D movies onto a wall size volumetric display.

First quantum teleportation between light and matter. Nature, 4 October 2006The concept of quantum teleportation - the disembodied complete transfer of the state of a quantum system to any other place - was first experimentally realised between two different light beams. Later it became also possible to transfer the properties of a stored ion to another object of the same kind. A team of scientist headed by Prof. Ignacio Cirac at MPQ and by Prof. Eugene Polzik at Niels Bohr Institute in Copenhagen has now shown that the quantum states of a light pulse can also be transferred to a macroscopic object, an ensemble of 10 to the power of 12 atoms.

Physorg.com

This is the first case of successful teleportation between objects of a different nature - the ones representing a "flying" medium (light), the other a "stationary" medium (atoms). The result presented here is of interest not only for fundamental research, but also primarily for practical application in realising quantum computers or transmitting coded data (quantum cryptography).