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DIF – Digital Imaging Fast

Ali Nuhi and Everett Salley

EEL4924 Senior Design

Date: 02 March 2011

Project Description

• Image Processing using an FPGA– Implementing edge detection algorithms in

hardware– Actual application for all the theory learned in

Signal Processing Courses– Would need a high speed DSP to achieve the

same effect

• User defined outputs– Direct video, Edges, possibly posterization

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System Overview

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LCD Screen

• LQ043T3DX02 – PSP Screen

• 24bit data signals (8bit*RGB)

• 9MHz clock

• 480x272x3

• Cheap, well documented

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Camera

• TCM8230MD – CMOS Color Camera– Meets VGA format requirments

• Camera module will be responsible for providing RGB pixel data– 25Mhz clock, 30fps max– Outputs RGB 5:6:5– 8bits at a time

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FPGA

• EP3C16E144C8N – 144PIN EQFP

• 84 I/O Pins (also a 160 I/O version)

• 15,408 Logic Elements

• 516,096 RAM Bits

• 112 9bit multipliers

• Crossing Clock Domains– Camera, LCD, Memory

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2D Convolution

Data

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Kernel Result

• Common operation in many 2D filters

Convolution in hardware

• You don’t need to know the entire image, only the local pixels

• For a 3x3 kernal, the result of 2D convolution is the sum of 9 multiplies.

• Ex) Sobel Edge detection requires two 3x3 convolutions (as well as a few other operations)

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Preliminary Datapath

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