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VeLoVeLoL1 Read OutL1 Read Out

Guido Haefeli

VeLo Comprehensive Review 27/28 January 2003

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VeLo Read Out SystemVeLo Read Out System

VeLo

TTCrx Driver

Repeater board

Equaliser

ADC

TTC

40m

Analog

electrical links

Read out board

Event Sync

L1 PreProcessor L1B

DAQ IF

FEM

TTC

Sh

ield

ing

wal

lTTCrx

To L1T To DAQ

ECS

1m

I2C

VREG

Crate balcony

15m

CAT6

Measured for 60m

Attenuation 10db@40MHz

Crosstalk

-64db@40MHz

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VeLo ROB board functionalityVeLo ROB board functionality

Reads 64 channels or 2048 detector strips. Individual clock delay and reference voltage for

each channel. Event synchronization and consistency check

based on a FE-chip located on each board. Individual strip pedestal correction . L1 buffering during 64ms. Advanced common mode and zero suppression

for the L1 trigger. Zero suppression for the DAQ.

CC-PC based ECS TTCrx

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VeLo digitizer board functional overviewVeLo digitizer board functional overview

L1Decision

SyncError detection

TTCrx

FEemulator

TFCLink

L1TCluster

FragmentLink

L1 zero suppression,clusterization

To L1T eventbuildingnetwork

L1 Buffercontroller

L1 Buffer

DAQInterface DAQ

ClusterFragment

Link

ToDAQ

Del

ay

Vre

f

JTAG

CtrlInterfaceI2C

Parallel ctrlECS

Ethernet

Error

Flagged

ADC

An

alog

dat

a

ADC

ADC

ADCThrottle

Clk

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Common mode suppression algorithmsCommon mode suppression algorithms

LCMS (Linear Common Mode Suppression) Applied on 1 analog channel (32 detector channels ). 8 bit precision. The LCMS

algorithm is now the baseline version for the CM suppression. It has shown very good performances.

Regions (RCMS) These are the same algorithm as LCMS but the linear correction are applied to 8

or 16 detector channels only. Its performance is of course better for non linear CM noise suppression.

Finite Impulse Response (FIR) filter Its performance for suppressing non linear noise is by its nature much better than

the LCMS type. With a FIR filter algorithm fine tuning can be done in order to suppress non linear CM.

Tested by mixing "noise" coming from test beam data and

"signal" B from Monte-Carlo (See LHCb VeLo 2001-043)

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PrototypingPrototyping

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RB2 RB2

4 analog channelsTTCrx module

ALTERA FLEX FPGA for simpledata processing

VME interface for data acquisition and board control

2048 word sample buffer

8-bit ADC @ 40MHz

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RB2 SummaryRB2 Summary

RB2 has been tested in the lab and in testbeams for performance measurements

(see LHCb note 2002-033).

To improve from RB2:

Improve clock distribution on the board (hardware modification have been implemented on existing RB2s ).

Introduce a clock adjustment for each ADC channel to cope with the delay skew on the cable.

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L1 Link FPGA

L1 Link cardFE Emulator

DAQ Link FPGA

Sync FPGA

TTCrx

4 CH ADC Card

L1 Pre Processor

L1B and DAQI Connector

ECS

RB3 Readout board

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RB3 tests RB3 tests

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Beetle setupBeetle setup

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Outlook to the final ROB (64 Channel Digitizer Board)Outlook to the final ROB (64 Channel Digitizer Board)

Common project for several sub-detectors in LHCb.

The board can also be used with optical receiver cards.

Specification is in preparation, release February 2003

Pre-production September 2003

Testing until April 2004

Final board production July 2004

32 Channel ADC

Sync

CC-PC

TTCrx

Power

Input

32 Channel ADC

Input

PP

PP

PP

PP

L1T

DAQ Link

R A M

R A M

R A M

R A M