Tanner Lab Manual (S-edit and L-edit)…

EXPERIMENT-1 Creating a CMOS Inverter using S-Edit To launch S-Edit in one of the LAB PCs, go to START > PROGRAMS > ELECTRICAL > TANNER > S-EDIT

The following window will open up.

Now we will create an inverter schematic and symbol.

INVERTER SCHEMATIC A CMOS inverter needs an NMOS, a PMOS, Vdd, Gnd and I/O pads.

Click on Module > Symbol Browser or click on to launch the symbol browser window.

On public machines, the Libraries might not immediately be loaded. To add library to your design. Click on Add Library button on the Symbol Browser window.. Browse to library folder within the Tanner folder and choose spice.sdb. Since we want to be able to simulate our inverter design using SPICE, we want pre-built MOSFETS, Power and Gnd sources that will be understood by SPICE. So always use the modules from the SPICE library.

Find the MOSFET_N (a four-terminal NMOS) from the list. Since you will be using this device in your other designs, you might want to add it to your Quick Pick by clicking on Add to Quick Pick. Choose your device and click on Place. Do the same for MOSFET_P, Vdd and Gnd symbols.

You might have to move your parts around to make the schematic look the way you want it. When you click on a particular part on the schematic, the function of the THREE-BUTTON MOUSE is shown at the bottom-left corner. So to Move a part around the schematic, select the part with either Left or Right mouse button and use the Central button to move.

Once we have the main parts in place, it is time to add I/O pins and wire the parts together. Select and place an Input Pad and an Output pad on the schematic and give the pads a unique name.

Now using the wiring tool make appropriate connections. After clicking on the wiring tool, a SINGLE MOUSE CLICK starts the wiring. If you want to end wiring at a particular location, DOUBLE CLICK.

Completed inverter schematic should look like this.

So we have made the connections. Now it is time to go change the length and width of the MOS devices as per the specifications. If you want to ZOOM INTO a part you can use the + key or a - key to ZOOM OUT. The default Length and Width of MOS devices in Tanner is 2u and 22u respectively. Lets change the width of the PMOS device to 11u.

With your mouse select module MOSFET_P in your schematic. Go to Edit > Edit Objects or click on on the toolbar. The following window will appear. You can change any parameter that you need. Select OK when done.

INVERTER SYMBOL Using the polygon and drawing tools from the left hand side, draw the usual symbol for an inverter. Add the input and output ports. Make sure to give the ports the same name that you used in the schematic i.e. in and out. Now using lines (not wires) connect the ports to the inverter symbol. You should have something that looks like:

The creation of the symbol might be helpful for doing hierarchical design.

CREATING SPICE NETLIST FROM THE SCHEMATIC

Go to File > Export

Specify the Output filename. (usually S-Edit automatically places <name_of_module>.sp as the output filename).

EXPERIMENT-2 Creating a CMOS Inverter Layout using L-Edit To launch L-Edit in one of the LAB PCs, go to START > PROGRAMS > ELECTRICAL > TANNER > L-EDIT

The following window will open up.

Create a new layout file by going to File > New. The following dialog box will appear.

Under the Copy TDB setup from file area, use the browse button to locate the mamin08.tdb file

Go to Setup > Design. Leave everything on the dialog box as it is. This dialog box shows the relationship between lambda and microns, specifies the grid settings and shows the type of technology being use.

Now that we have setup the technology, we will layout a simple CMOS inverter with PMOS sized W=12 lambda, L = 2 lambda and NMOS sized W=6 lambda, L=2 lambda.

In Tanner, in order to layout either an NMOS or a PMOS, a series of layers must be laid out. Here are the requirements:

• PMOS: First layout a n-well (n-substrate). Then put a layer of P-select. On area designated P-select, add an appropriate sized Active layer. Now put a layer of Poly for gate.

• NMOS: First layout a p-well (p-substrate). Then put a layer of N-select. On area designated N-select, add an appropriate sized Active layer. Now put a layer of Poly for gate.

• The substrate/bulk needs to be connected to Vdd for PMOS and Gnd for NMOS. For PMOS, place a small N-select (NOT P-select) on the n-well substrate, add a small Active layer. From this active layer put a contact to a

Metal 1 layer that connects to VDD. For NMOS, on the p-well substrate (i.e. just the background grid) place a small P-select, followed by an Active layer. From this active layer put a contact to a Metal 1 layer that connects to Gnd.

Now using the shape tool from the top bar and the layer-pallet from the side-bar, and the requirements mentioned above draw a PMOS. Similarly draw the NMOS (remember you do not need to draw the P-well). Before you go any further, it is important to note that your design is not correct until you connect your substrate.

Check your layout using a the design rule check function. Click the DRC button on the top toolbar. It is a good idea to run DRC at each stage of your design so that you can fix any error along the way.

Once you have your NMOS and PMOS done, layout an inverter as shown below: Use the design rules (from Digital Integrated Circuits: A Design Perspective - color leaflet between pages 10 and 11) to properly space the objects.

Notice how compact the above inverter design is. The goal is to create a minimum physical implementation of all the layout designs, and to use minimal wires, transistors, contacts, etc. Not doing so will decrease circuit speed and performance as well as increase circuit size.

Label the Input, Output ports and the Power ports using button on the top-toolbar. On the final design run DRC. If there is a Design Rule Violation, a dialog box will open pointing out what the error is. If you click on the error message, it will show exactly where on the design the problem resides.

Fix any DRC error before proceeding. Keep in mind that passing the DRC test does not guarantee that your design will work as you expect. A DRC Pass just means that there are NO DESIGN RULE violations.

Now that we have a complete error free design, it is time to extract the SPICE netlist for the layout. Click on the button on the toolbar. Browse to the correct Extract Definition File

Click on the output tab on the Extract dialog box. Uncheck everything except: Write terminal names for subcircuits, and Write nodes and devices as Names. Also make sure the SPICE include statement textbox is empty.

Click Run. You might get an error message similar to:

Ignore all warning messages related to Capacitances.

Extracted SPICE Netlist .control destroy all echo TRAN 0.001m 2m

plot output+6 input .endc .MODEL MNMOSIS NMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.236187E+14 VTO=0.858153 KP=5.048000E-05 GAMMA=0.198 + PHI=0.6 UO=596.729 UEXP=7.029586E-02 UCRIT=10266.7 + DELTA=2.7371 VMAX=65701.4 XJ=0.250000U LAMBDA=1.843384E-02 + NFS=1.086360E+12 NEFF=1 NSS=1.000000E+10 TPG=1.000000 + RSH=28.760000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.838441E-10 + CJ=8.997900E-05 MJ=0.783638 CJSW=5.524800E-10 MJSW=0.285064 PB=0.800000 .MODEL MPMOSIS PMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.309300E+15 VTO=-0.889271 KP=1.908000E-05 GAMMA=0.6289 + PHI=0.6 UO=216.28 UEXP=0.218144 UCRIT=62664 + DELTA=0.164572 VMAX=100000 XJ=0.250000U LAMBDA=5.011626E-02 + NFS=9.266623E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000 + RSH=66.820000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.727276E-10 + CJ=2.981300E-04 MJ=0.556944 CJSW=3.002100E-10 MJSW=0.243045 PB=0.800000 * WARNING: Layers with Unassigned AREA Capacitance. * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * WARNING: Layers with Unassigned FRINGE Capacitance. * <Pad Comment> * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * <Poly1-Poly2 Capacitor> * WARNING: Layers with Zero Resistance. * <Pad Comment> * <Poly1-Poly2 Capacitor> * <NMOS Capacitor> * <PMOS Capacitor> VVin Vdd 0 DC 5 Vinput input 0 PULSE(0 5 0 0 0 0.0005 .001) M1 output input Vdd Vdd MPMOSIS L=2u W=6u AD=42p PD=26u AS=36p PS=24u * M1 DRAIN GATE SOURCE BULK (41 29 43 35) M2 output input 0 0 MNMOSIS L=2u W=3u AD=39p PD=26u AS=33p PS=24u * M2 DRAIN GATE SOURCE BULK (41 11 43 14) * Pins of element D3 are shorted: * D3 Vdd Vdd D_lateral AREA=6p * D3 PLUS MINUS (34 29 35 35) * Pins of element D4 are shorted: * D4 0 0 D_lateral AREA=6p

* D4 PLUS MINUS (35 10 36 16) * Total Nodes: 4 * Total Elements: 4 * Extract Elapsed Time: 0 seconds .END

EXPERIMENT-3 Creating a NAND Gate Schematic and Layout

2-Input NAND Schematic

2-Input NAND Layout

NAND gate

A B output

0 0 10 1 11 0 11 1 0

Table. NAND gate output

Extracted SPICE Netlist .control destroy all echo TRAN 0.001m 2m plot output+12 input1 input2+6 .endc .MODEL MNMOSIS NMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.236187E+14 VTO=0.858153 KP=5.048000E-05 GAMMA=0.198 + PHI=0.6 UO=596.729 UEXP=7.029586E-02 UCRIT=10266.7 + DELTA=2.7371 VMAX=65701.4 XJ=0.250000U LAMBDA=1.843384E-02 + NFS=1.086360E+12 NEFF=1 NSS=1.000000E+10 TPG=1.000000 + RSH=28.760000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.838441E-10 + CJ=8.997900E-05 MJ=0.783638 CJSW=5.524800E-10 MJSW=0.285064 PB=0.800000 .MODEL MPMOSIS PMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.309300E+15 VTO=-0.889271 KP=1.908000E-05 GAMMA=0.6289 + PHI=0.6 UO=216.28 UEXP=0.218144 UCRIT=62664 + DELTA=0.164572 VMAX=100000 XJ=0.250000U LAMBDA=5.011626E-02 + NFS=9.266623E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000 + RSH=66.820000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.727276E-10 + CJ=2.981300E-04 MJ=0.556944 CJSW=3.002100E-10 MJSW=0.243045 PB=0.800000 * WARNING: Layers with Unassigned AREA Capacitance. * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor>

* WARNING: Layers with Unassigned FRINGE Capacitance. * <Pad Comment> * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * <Poly1-Poly2 Capacitor> * WARNING: Layers with Zero Resistance. * <Pad Comment> * <Poly1-Poly2 Capacitor> * <NMOS Capacitor> * <PMOS Capacitor> VVin Vdd 0 DC 5 Vinput1 input1 0 PULSE(5 0 0 0 0 0.0005 .001) Vinput2 input2 0 PULSE(0 5 0 0 0 0.001 .002) M1 output input1 Vdd Vdd MPMOSIS L=2u W=6u AD=30p PD=22u AS=12p PS=16u * M1 DRAIN GATE SOURCE BULK (25 27 27 33) M2 output input2 Vdd Vdd MPMOSIS L=2u W=6u AD=12p PD=16u AS=36p PS=24u * M2 DRAIN GATE SOURCE BULK (21 27 23 33) M3 output input1 temp temp MNMOSIS L=2u W=3u AD=66p PD=48u AS=78p PS=52u * M3 DRAIN GATE SOURCE BULK (45.5 11 47.5 14) M4 temp input2 0 0 MNMOSIS L=2u W=3u AD=66p PD=48u AS=78p PS=52u * M4 DRAIN GATE SOURCE BULK (21 11 23 14) * Pins of element D5 are shorted: * D5 2 2 D_lateral AREA=6p * D5 PLUS MINUS (52.5 9 53.5 15) * Pins of element D6 are shorted: * D6 2 2 D_lateral AREA=6p * D6 PLUS MINUS (28 9 29 15) * Pins of element D7 are shorted: * D7 1 1 D_lateral AREA=6p * D7 PLUS MINUS (32 27 33 33) * Total Nodes: 6 * Total Elements: 7 * Extract Elapsed Time: 0 seconds .END

EXPERIMENT-4 Creating a CMOS NOR Gate Schematic and Layout

2-Input NOR Schematic

2-Input NOR Layout

NOR gate

A B output

0 0 1 0 1 0 1 0 0 1 1 0

Table . NOR gate output

.control destroy all echo TRAN 0.001m 2m plot output+12 input1 input2+6 .endc .MODEL MNMOSIS NMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.236187E+14 VTO=0.858153 KP=5.048000E-05 GAMMA=0.198 + PHI=0.6 UO=596.729 UEXP=7.029586E-02 UCRIT=10266.7 + DELTA=2.7371 VMAX=65701.4 XJ=0.250000U LAMBDA=1.843384E-02 + NFS=1.086360E+12 NEFF=1 NSS=1.000000E+10 TPG=1.000000 + RSH=28.760000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.838441E-10 + CJ=8.997900E-05 MJ=0.783638 CJSW=5.524800E-10 MJSW=0.285064 PB=0.800000 .MODEL MPMOSIS PMOS LEVEL=2 LD=0.250000U TOX=418.000008E-10 + NSUB=9.309300E+15 VTO=-0.889271 KP=1.908000E-05 GAMMA=0.6289 + PHI=0.6 UO=216.28 UEXP=0.218144 UCRIT=62664 + DELTA=0.164572 VMAX=100000 XJ=0.250000U LAMBDA=5.011626E-02 + NFS=9.266623E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000 + RSH=66.820000 CGDO=3.097916E-10 CGSO=3.097916E-10 CGBO=3.727276E-10 + CJ=2.981300E-04 MJ=0.556944 CJSW=3.002100E-10 MJSW=0.243045 PB=0.800000 * WARNING: Layers with Unassigned AREA Capacitance. * <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * WARNING: Layers with Unassigned FRINGE Capacitance. * <Pad Comment> * <Poly Resistor>

* <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor> * <N Well Resistor> * <P Base Resistor> * <Poly1-Poly2 Capacitor> * WARNING: Layers with Zero Resistance. * <Pad Comment> * <Poly1-Poly2 Capacitor> * <NMOS Capacitor> * <PMOS Capacitor> VVin Vdd 0 DC 5 Vinput1 input1 0 PULSE(0 5 0 0 0 0.0005 .001) Vinput2 input2 0 PULSE(0 5 0 0 0 0.001 .002) M1 temp input1 Vdd Vdd MPMOSIS L=2u W=6u AD=84p PD=52u AS=72p PS=48u * M1 DRAIN GATE SOURCE BULK (24 39 26 45) M2 output input2 temp temp MPMOSIS L=2u W=6u AD=84p PD=52u AS=72p PS=48u * M2 DRAIN GATE SOURCE BULK (51 39 53 45) M3 output input1 0 0 MNMOSIS L=2u W=3u AD=6p PD=10u AS=33p PS=24u * M3 DRAIN GATE SOURCE BULK (47 22.5 49 25.5) M4 output input2 0 0 MNMOSIS L=2u W=3u AD=39p PD=26u AS=6p PS=10u * M4 DRAIN GATE SOURCE BULK (51 22.5 53 25.5) * Pins of element D5 are shorted: * D5 1 1 D_lateral AREA=6p * D5 PLUS MINUS (41 21.5 42 27.5) * Pins of element D6 are shorted: * D6 2 2 D_lateral AREA=6p * D6 PLUS MINUS (44 39 45 45) * Pins of element D7 are shorted: * D7 2 2 D_lateral AREA=6p * D7 PLUS MINUS (17 39 18 45) * Total Nodes: 6 * Total Elements: 7 * Extract Elapsed Time: 0 seconds .END