1 read out & data analysis of the mvd demonstrator s. amar-youcef, m. deveaux, i. fröhlich, j....
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Read out & data analysis of the MVD demonstratorS. Amar-Youcef, M. Deveaux, I. Fröhlich, J. Michel, C. Müntz,
C. Schrader, S. Seddiki, T. Tischler, and J. Stroth
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Outline
Goals Read out & data analysis software First measurements
Test of data consistency Quality of the analog readout chain
Summary
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Goals of the software
Validation of the demonstrator Build C++ platform to test data sparsification
algorithms and to compare with FPGA-implementation.
Interfacing the demonstrator with CBM-Root and the Strasbourg pixel telescope
Option to interface this algorithm with the CBMRoot digitizer to test it in simulation
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Data acquisition & Demonstrator Analysis Software (DAS)MIMOSA - chip
HDD
AD conversion
Raw data transfer(Mode 0)
ReaderReader +
Offline data sparsification
Analog/Digital cluster finder
Strasbourg pixelbeam telescope
Reader
Digitizer datasparsification
GEANT+MVD Digitizer
Dedicated analysis,validation, radhardness, …
CBMRoot interfaceMVD-clusters or MVD-hits
FPGA data sparsification(Mode 1)
HDD
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HDD
StatusMIMOSA - chip
AD conversion
Raw data transfer(Mode 0)
Reader + Offline data sparsification
Analog/Digital cluster finder
Dedicated analysis,validation, radhardness, …
Reader
Strasbourg pixelbeam telescope
Reader
Digitizer datasparsification
GEANT+MVD Digitizer
CBMRoot interfaceMVD-clusters or MVD-hits
FPGA data sparsification(Mode 1)
HDD
Analog cluster finder
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First usecase of the DASValidation of analog readout chain of the
demonstrator
Demo-AUX
analogue output
sync. signals
data transfer: OP
-link
monitoring
MAPS add-on board
Trb2(TRBnet)
File Server
data transfer: I/O-card
or
Test-setupTest-setup
Mi20 board(Previously tested with Strasbourg reference system)
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Test of data consistency Constant pixel sequence in frames,
Since data is rearranged
Any shift in pixel order reflect the dynamic range!
If correctly arranged: CDS eliminates the dynamic range.
Frame 0Frame 1
Sig
nal
(A
DC
uni
ts)
Sig
nal
(A
DC
uni
ts)
rowrow
column column
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Tested for several 1000consecutive frames
=> OK
Performing CDSFrame 0 Frame 1
CDS
row
column
Sig
nal
(A
DC
un
its)
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Test of data consistency Hit distribution reproduces illumination spot by 55Fe-
source
Order of pixels seems to be OK!
Picture of the collimator of the Fe55-source
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Quality of the analog readout chain Significant parameters
Particle detection ability Gain Noise
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Particle detection ability
Cluster-building for charge spectrum (55Fe-source)1. Significant hits (amplitude > 5*noise) → seed candidate2. Test seed candidates: no adjacent pixel with larger amplitude3. Seed found: take all adjacent pixels to build cluster
Margin Hits
Diode Hits
As expected from reference system => OK
CDS-Signal (ADC)
En
trie
s
Hit-Cluster
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Gain test Using photons from 55Fe-source for ADC
calibration
Gain = 6e/ADC
Small, irrelevant variation with respect to reference system(Expected K-Peaks at 400ADC)
=> OKMargin Hits
Kα
Kβ
CDS-Signal (ADC)
En
trie
s
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Noise measurementNoise: RMS of the fluctuations of the pixels over time
F0-F1
RMS of Individual pixels
Mean noise = 33e => Expected 25e
Origin of additional noise was identified (preliminary analog cable).Building an dedicated cable is in progress, expect results within two weeks.
rowcolumn
Sig
nal
(A
DC
un
its)
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Summary The Demonstrator Analysis Software (DAS) is a software to
analyse the data of the MVD-demonstrator within CBMRoot. It will allow to test the same data sparsification algorithms with
real data and simulated data. It will interface the MVD + the Strasbourg pixel telescope with
CBMRoot DAS was used to validate the FPGA-board of the MVD-
demonstrator using a tested MIMOSA-20 chip. The data consistency of the FPGA-board was confirmed. The hit finding ability of the FPGA-board was confirmed. The source of a small additional noise with respect to the slower
reference system was identified and will be fixed within the next weeks.
The tests performed confirm the validity of the design of the FPGA-Board