1

PSP Family of Compact ModelsOverview and Recent DevelopmentsMOS-AKDecember 13th, 2008

G. Gildenblat, W. Wu, X. Li, Z. Zhu, W. Yao, Q. Zhou, G. Dessai, and A. Dey

G.D.J. Smit, A.J. Scholten, and D.B.M. Klaassen

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OutlinePSP project overview

Introduction to bulk PSP

Recent developments in bulk PSP

PSP-SOI

PSP-MGFET

ConclusionsMOSFET characteristics shown in this presentation are from Philips/NXP, Freescale and IBM (presented with permission)

Further information about PSP can be found on PSP website: http://pspmodel.asu.edu

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PSP Family of Models PSP: industry (CMC) standard for bulk MOSFETs

PSP-based varactor model: industry (CMC) standard

PSP-SOI-PD: submitted to CMC for evaluation (sponsored by IBM)

PSP-SOI-DD: submitted to CMC for evaluation (sponsored by Freescale)

PSP-MGFET

PSP-LT: PSP model for the extended temperature range for space applications (NASA/JPL)

PSP-R2H: PSP-based model for the physics-based real-time evaluation of radiation, EMP and reliability effects at the circuit level

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OutlinePSP project overview

►Introduction to bulk PSPIntroduction to bulk PSPRecent developments in bulk PSP

PSP-SOI

PSP-MGFET

Conclusions

5

s-Based vs. Vth-Based Models

VSB = 0 V; VDS = 1 V

I DS

(A)

VGS (V)0 1 2

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Idiff

Idrift

IDS = Idrift + Idiff

I DS

(A)

VGS (V)0 1 2

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

empirical

interpolation

asymptotic

PSP Vth-based

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Advanced Features of PSP Non-iterative formulation

Completely surface-potential-based including the S/D overlap regions

Complete symmetry of device characteristics including all higher-order effects

Advanced mobility model including Coulomb scattering

Perfect reproduction of gm/Id ratio

Capability to model harmonic distortion including intermodulation effects

Physical gate current model including accurate bias-dependent partitioning scheme implemented via symmetric linearization method

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Advanced Features (cont’d) The most complete ever noise model correctly including velocity

saturation effects and all noise sources

Extensively verified unified large-signal/small signal NQS Model

Most complete and physical junction diode model (JUNCAP2)

Inclusion of non-uniform doping

Accurate CLM modeling in halo-doped devices

New mathematical structure of the model based on solution of several long-standing problems of compact modeling (e.g. symmetric linearization, spline-collocation NQS model, etc.)

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Non-Universality of the Effective Mobility Produced by the Coulomb Scattering

Effective Field (MV/cm)

No

rmal

ized

Mo

bil

ity

Produced by Coulomb Scattering Term

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Drift Velocity PSP uses drift velocity model that is conducive to the highly

accurate description of saturation region including high order drain conductances

This form also assures compliance with Gummel symmetry

test and non-singular model behavior at Vds= 0.

2

1

yd

y c

EV

E E

2

11

yd

y c

y c

EV

E E

E E

Electrons:

Holes:

10

Gm/ID Plots for Two Corners of the 90 nm Process

ID (A)

10µm/0.04µm

Gm /

ID (

1/V

)

ID (A)

10µm/1µm

VDS = 0.025V, VBS = 0 to -1.2V, and VGS = 0 to 1.2V

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Output Conductances

VGS = 0V to 1V in steps of 0.2 V, VSB = 0V

T = 250C

VDS (V)

gD

S (A

/V)

W/L=10/1µm

VDS (V)g

DS (

A/V

)

W/L=10/0.04µm

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Higher Order Transconductances and Conductances

VSB=0V, T=250C, W/L=10/0.04µm (nmos), i=1(lower curve), 2(middle curve), 3(upper curve)

VSB=0V, T=250C, W/L=10/0.04µm (nmos), i=1(lower curve), 2(middle curve), 3(upper curve)

VGS (V)

gm

i (A

/V)

VDS = 0.025V

gD

Si (A

/V)

VDS (V)

VGS = 1V

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Theoretical foundation of PSP is symmetric linearization method: it is used to simplify surface-potential-based approach and to make it practical.

To simplify formulation compact MOSFET models almost always use bulk and inversion charge linearization. The traditional form is

In Vth-based models:

Disadvantage: symmetry between source and drain is lost, accuracy is poor

Traditional Asymmetric Linearization

s ss s ss( )

1 2 ssss

1 11

·2 a a

ss b sb2 V

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Symmetric Linearization Define surface potential midpoint (subscript “m”)

For VDS > 0, this is not a geometric midpoint:

Set inversion charge (per unit channel area)

m ss sd1

( )2

sd ss

m 1 ,2 4

Ly

H

t im m satH q H

s m

ii im s m

s

dqq q

d

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Example of What Symmetric Linearization can Accomplish

Original CSM (C. McAndrew and J. Victory, 2003)

PSP

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Verification of Symmetric Linearization

Vds = 2V, Vbs= 0 V, Vfb=-1V

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CV Characteristics

W/L = 800µm/90nm, Vds=0, Vsb=0

W/L=10/0.08µm, Vbs=-0.1V, Vgs=1.2V

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

-3.00E-015

-2.00E-015

-1.00E-015

0.00E+000

1.00E-015

Cap

acita

nce

(F)

Vd (V)

CBD

CDB

CBG

CGB

CBS

CSB

CDS

CSD

Vds (V)

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Gate Tunneling Current Components

The same form of model and identical parameters are used in Igc, Igsov and Igdov

No scaling parameters are required to fit the data

VDS=0V to 1V in steps of 0.5 V

VSB=0V, W/L=10µm/1µm (nmos)

T=250C

Igc

Ig

Igsov

IgcdIgcsDS

Igdov

Vgs, (V)

I g, (

mA

)

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PSP Noise Model Includes thermal channel noise, 1/f

noise, channel-induced gate noise and shot-noise in the gate-current

Thermal channel noise automatically becomes shot noise below threshold, so it is not necessary to model this phenomena separately

Rigorously includes fluctuations in the velocity saturation term.

Takes advantage of symmetric linearization to simplify expressions for the spectral densities

Experimentally verified

Example

Drain (Sid) and gate (Sig) current noise spectral densities

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NQS Model Verification: Re[Y11]

VDS=1.5 V, VGS= 0.5 to 1.5 in 0.5V steps

PSP, SWNQS=9 MM11, 5 segmentsPSP, SWNQS=5

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OutlinePSP project overview

Introduction to bulk PSP

►Recent developments in bulk PSPRecent developments in bulk PSPPSP-SOI

PSP-MGFET

Conclusions

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Recent Developments in PSP Optional asymmetric junctions

Optional separate doping profiles for I(V) and C(V) characteristics

Optional suppression of back-bias effect for high back biases

GA-based automatic procedure for parameter extraction (local and global)

PSP-LT: PSP model for the extended temperature range

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Automatic GALM Parameter Extraction

GA - Genetic Algorithm, LM - LevenbergMarquardt Algorithm Objectives

• Unbiased evaluation of new parameters (are they really needed)• Ease of parameter extraction

Example :

Table I. Relative RMS error (%) on Id (Vd) with ALP2 on and off.Setting W=L=10m W/L=10/0.24m W/L=10/0.06m

Fit with ALP2=0

Fit with ALP20

1.6

0.63

2.9

1.7

2.5

1.8

2

1 22

im m tbm

im m tim m t

qT T q

qq

ALP1ALP ALP2

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Automatic Parameter Extraction Results for PSP 102.1

0 0.5 1 1.5Vg (V)

Id (

A.U

.)

0 0.5 1 1.5Vg (V)

gm (

A.U

.)

0 0.5 1 1.5Vg (V)

Id (

A.U

.)

0 0.5 1 1.5Vg (V)

gm (

A.U

.)

W=L=10m W=L=10m

W/L=120/65nm W/ L=120/65nm

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measuredPSP

Non-uniform Doping

L = 45 nmVDS = 50 mVVSB = 0 … 1.3 V

0.0 0.5 1.0

VGS (V)

I ds

(arb

. un

its)

PSP 102

0.0 0.5 1.0

I ds

(arb

. un

its)

VGS (V)

PSP 103 with NUD

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Non-uniform Doping

Effective body factor Threshold voltage

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Decouple C-V and I-V

Using a single effective NSUB for both I-V and C-V

Shift of Vth due to lateral halo doping

Separate NSUB for I-V and C-V

Achieve better fit usingalternative NSUB for C-V only

An IBM process using halo doping (from J. Watts)

New C-V fit does not affect I-V

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Parameter Extraction Flowchart

For PSP 103

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OutlinePSP project overview

Introduction to bulk PSP

Recent development in bulk PSP

►PSP-SOIPSP-SOIPSP-MGFET

Conclusions

30

0 0.5 10

0.5

1

1.5

2

2.5

3

Gate voltage, V

Dra

in c

urr

ent,

mA

model with EVBmodel without EVBmeasurement

0 0.5 10

0.5

1

1.5

2

2.5

3

3.5

Gate voltage, V

Tra

nsc

on

du

ctan

ce, m

S

0 0.5 1

0

0.5

1

1.5

2

2.5

3

Drain voltage, V

Dra

in c

urr

ent,

mA EVB affects IDS linearity at high VGS

Model can faithfully reproduce the “humps” in gm characteristics

W/L = 3m/0.13m

Impact of EVB on DC-IV

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Parasitic BJT qB incorporates the Early effect and high level injection

Recombination current in neutral body region Junction diffusion capacitance

0 0.5 110

-1010

-910

-810

-710

-610

-510

-410

-310

-210

-110

0

VBS

, V

Bip

ola

r cu

rren

t. m

A

ID

IB

modeldata

G

BOX

Substrate

body

S D

BJTI

)(recBSI

BT

BD

T

BSSATBJT,BJT q

1

φ

Vexp

φ

VexpII

W/L = 3m/0.055m

VE=VS=0 VVG= -0.3 VVD=VB

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B: mobility of majority carriers in the body Qnbr: total mobile majority charge in the neutral body region

nbrB

2

body Qμ

WR

BSIEFFnbr QWLtqNQ

EjdjsfBB QQQQQ

Mobile charges in neutral body region

Total bulk charge

DS

L

Substrate

tox

tsi

tbox

Qjs Qjd

QBf

Qnbr

G Bias independent

bshbody RL

WR

Bias dependent

biasL,W,RR bodybody

Bias-Dependent Body Resistance Model

Based on Freescale in-house Rbody model (G. Workman et al.)

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-1 -0.5 0 0.5 10

0.5

1

1.5

2

2.5

3

3.5

Body bias (V)

Bo

dy

resi

stan

ce (

M

)

VGBb = 0 V

VGBb = -10 V

nonlinear modeldata

Example: 65nm PD/SOI H-gate

W/L = 3m / 65nmVGS = -0.3 V; VDS = 0 V

IS

Bf

GS D

Bs

If+-

VBS

Junction leakage

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101

102

103

104

105

106

107

108

109

10-11

10-10

10-9

10-8

Frequency, Hz

Dra

in n

oise

vol

tage

spec

tral

den

sity

, V2 /H

z

VDS=0.6, 0.7, 0.8, 0.9V

Excess Low Frequency Noise Modeled Automatically

Excess LF noise is caused by floating body effect

PD/SOI floating bodyW/L = 3m/0.055m

20

1

)(

cff

ffS

bs

T

bs

bseq

eqeqc I

n

dV

dIr

Crf

1

;2

1

G

E

S DCSB

CEB

CDB

CGB

req

GBEBDBSBeq CCCCC

Excess noiseW. Jin et al T-ED 1999

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Body-Contacted PD/SOI

0 0.5 10

1

2

3

4

VDS

, V

I DS

, mA

0 0.5 10

1

2

3

4

VDS

, V

I DS

, mA

0 0.5 10

0.5

1

1.5

2

2.5

3

3.5

VDS

, V

I DS

, mA

0 0.5 10

0.5

1

1.5

2

2.5

VDS

, V

I DS

, mA

0 0.5 110

-3

10-2

10-1

100

101

102

VDS

, V

gD

S, m

S

0 0.5 110

-3

10-2

10-1

100

101

102

VDS

, V

gD

S, m

S

0 0.5 110

-3

10-2

10-1

100

101

102

VDS

, V

gD

S, m

S

0 0.5 110

-4

10-3

10-2

10-1

100

101

VDS

, V

gD

S, m

S

L=150nm 75nm 65nm 55nm

VGS= 0.2, 0.4, 0.6, 0.8, 1.0, 1.3 VVBS = 0.0 V

W=3m, L=55nm-150nm

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BC PD/SOI Cont’d

0 0.5 1

10-6

10-5

10-4

10-3

10-2

10-1

100

VGS

, V

I DS

, mA

0 0.5 1

10-6

10-5

10-4

10-3

10-2

10-1

100

VGS

, V

I DS

, mA

0 0.5 1

10-6

10-5

10-4

10-3

10-2

10-1

100

VGS

, V

I DS

, mA

0 0.5 1

10-6

10-5

10-4

10-3

10-2

10-1

100

VGS

, V

I DS

, mA

0 0.5 10

0.2

0.4

0.6

0.8

1

VGS

, V

gm

S, m

S

0 0.5 1

0

0.2

0.4

0.6

0.8

VGS

, V

gm

S, m

S

0 0.5 1

0

0.2

0.4

0.6

0.8

VGS

, V

gm

S, m

S

0 0.5 1

0

0.1

0.2

0.3

0.4

0.5

VGS

, V

gm

S, m

S

L=150nm 75nm 65nm 55nm

VBS= -0.2, 0, 0.2, 0.4, 0.6 VVDS= 0.05 V

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PSP-SOI-PD Harmonic Balance Simulation

PD/SOI floating body; W/L = 3m/0.055m

-60 -50 -40 -30 -20-350

-300

-250

-200

-150

-100

-50

V IN

, dB

I D, d

B

n=1

2

3

4

5

PSP-SOI simulationTheoretical slope

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OutlinePSP project overview

Introduction to bulk PSP

Recent development in bulk PSP

PSP-SOI

►PSP-MGFETPSP-MGFETConclusions

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DGFET and SGFET Structures

Double Gate Surrounding Gate

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Symmetric Linearization for DGFET

0 0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

Vg- [V]

Nor

mal

ized

Cg

g

Exact (Lu et al., TED 2006)

0 0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

Vg- [V]

Nor

mal

ized

Cg

g

Exact (Lu et al., TED 2006)Symmetric linearization

0 0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

Vg- [V]

Nor

mal

ized

Cg

g

0 0.5 1 1.5 2-1

0

1

Rel

ativ

e er

ror

[%]

Exact (Lu et al., TED 2006)Symmetric linearization

SL formulation:

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Symmetric Linearization for SGFET

0.5 1 1.5 20

0.2

0.4

0.6

0.8

1

Vg- [V]

Nor

mal

ized

Cg

g

0.5 1 1.5 2-2

0

2

Rel

ativ

e er

ror

[%]

Exact (Yu et al., TED 2007)Symmetric linarization

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Conclusions Surface-potential-based approach to MOSFETs of all kinds is an

undisputed industry standard

PSP model includes all relevant device physics and its accuracy is verified down to 32 nm technology node

PSP model structure is flexible and is easily extendable to enable the model to serve as gateway for advanced CMOS design in the coming years

Work is in progress to add the latest developments and to maintain and upgrade the model code

PSP family includes bulk, varactor, SOI and FinFET models

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Acknowledgements PSP developers are grateful to C. McAndrew, P. Bendix, J. Watson,

and G. Workman for numerous stimulating discussion of the subject of compact modeling

The development of PSP is continuously funded in part by SRC since 1998

Testing and implementation of PSP is funded in part by CMC

Past funding from LSI Logic, Mentor Graphics, Freescale, IBM and TI is gratefully acknowledged