1 p6 architecture computer architecture m. 2 pipeline between the three main sections compensation...

1

P6 Architecture

Computer architecture M

2

PIPELINE

Between the three main sections compensation queues are inserted. The machine instructions are rotated in order to align them to the decoders. Superpipelined processor (number of stages greater than necessary in order to increase the clock frequency)

Variablenumberof clocks

IFU1

IFU2

IFU3

DEC1

DEC2

ROB

DIS

EX

RET1

RET2

BUS interfacemanagement

(in order)

Execution mechanism

(Out-Of-Order)

Results handling(in order)

8 c

locks

Dispatcher(issues the

instructions)

RAT

RAT = Register Allocation TableROB = ReOrder Buffer

Renaming

3

Behaviour

• In order results transfers to the machine registers (commitment)

• Instruction extraction from the prefetch queue (a small set of instructions already extracted from the cache )

• Instruction decoding and alignment (in order)

• Machine instructions translation into RISC m-operations – fixed lenght 118 bit (RISC - in order)

• m-operations insertion in the ROB (in order)

• Out-of-order m-operations execution for functional modules use optimization

4

Pipeline stages

RAT: (Register AllocationTable) 40 more registers which can be globally allocated

IFU1: (Instruction Fetch Stage 1) loads the 2x16=32 bytes buffer (a cache line) directly from L1 cache. While one buffer transfers data to IFU2 the other is loaded by L1

IFU2: (Instruction Fetch Stage 2) detects the instructions boundaries (CISC) for the IFU3. If a branch is detected it is forwarded to the BTB

IFU3: (Instruction Fetch Stage 3) sends the instructions to the appropriate decoders (see later)

DEC1: (Decoder Stage 1) transforms the machine instructions into m-operation (118 bit wide). Up to three IA32 instructions per clock can be processed. For very complex machine instructions a sequencer is used. The m-operations consist of two sources and one destination plus op-code (RISC)

DEC2: (Decoder Stage 2) transfers the m-operations to the decoded instruction queue. Sometimes for very complex instructions (for instnce string instructions) many clocks are requested to complete the operation since the m-instruction queue accepts up to elements per clock. Micro Instruction Sequencer. It includes a second BTB (static – see later)

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Pipeline stages

RET2: (RETirement Stage 2). It transfers the results to the architectural machine destination registers when all the preceding machine level instructions have been already committed. Up to 3 m-ops per clock are retired

ROB: loads three m-operations per clock into its buffer. If all m-operations required data are already available (produced by preceding ROB m-operations or already available in the machine registers) and a free slot in the RS queue (Reservation Station of the required functional unit) the m-operation is inserted (here the RS is different from Tomasulo’s. In the RS only ready m-operations that is the required operands are already available).

DIS: (DISpatch Stage) if the m-operations in the previous clocks were not inserted into the RS because of lack of the necessary data or slots, inserts the m-operation as soon as the required conditions are met

EX: (EXecution Stage) executes the m-operation. The number of clocks necessary depends on the m-operation. Several m-operations are executed in a single clock period. Functional modules

RET1: (RETirement Stage 1). When a m-operation has been executed and all the preceding conditional branches have been solved, attaches a ready-for-retirement tag to the m-operation

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IFU1-IFU2 stages

It transfers a 32 bytes line from the L1 cache to the prefetch queue

IFU1

IFU2

It detects the instruction boundaries within a 16 byte block (half cache line). In the IFU2 any conditional BRANCH address is forwarded to the BTB (physical addresses!). Up to 4 addresses can be in parallel analyzed by the BTB. Initially the BTB is obviously empty and for each decision taken the BTB is updated.

If the branch is predicted as taken the following instructions loaded in the prefetch buffer are removed and the buffer is loaded again with the destination instructions. If the branch is predicted as not taken no change

During the branch execution in the Jump Execution Unit no problem if the branch was correctly predicted, otherwise all following ROB u-ops are cancelled together with their results. The same occurs to all other instructions already in the pipeline. The prefetch buffer is emptied and loaded again with the correct instruction sequence.

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Branch

A further buffer exists in the P6 (the Return Stack Buffer) which stores the return addresses of the speculated subroutines. When a call is speculated (executed before beeing top of the instruction queue) it is not yet sure whether it must be really executed since a previous branch could change the instruction flow. In this case the stack would have been «dirtied». The content of the RSB are transferred to the real stack as soon as the call is actually executed. The RSB consists of 8 entries

The BTB is made of a 4-ways set-associative cache with 512 entries (for each index there are 4 physical branch addresses which are handled)

The prediction algorithm is two-levels: for each BTB entry there is a 4 bit register which stores the behaviours of the last occurrences of the address (BHT).

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Pipeline

IFU1

IFU2

IFU3

DEC1

DEC2

RAT

ROB

DIS

EX

RET1

RET2

PrefetchBuffer

Instructionlenght

detection

BranchTargetBuffer

Decoder

Decoderqueue

Functionally this pipeline is triple

OUTOF

ORD.

INORD.

||6Up to 6-m ops/clock

INORD.

In the ROB the -m ops are stored in order, are executed OOO, are retired in order

(alignment for the decodimg)

Compensation queues are needed for different

stages speed

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IFU3 stage

• If there are two ( o more) «complex» instructions the compiler generated instruction sequence is not optimal and the operations take place in sequence

Instructions types

• Simple (converted into a single m-operation): register to register, memory read , etc.

• Complex-2 (converted into 2 m-operations): memory write, read/modify, register-memory (sometimes requiring 3 m-operations)

• Complesse-3: MMX

• Complesse-4: read/modify/write (ex. add [BP], bx)

• It prepares the instructions for the three decoders of stage DEC1

• Using the «markers» inserted into the 16 bytes block by IFU2, IFU3 rotates, if needed, the three IA instructions so as to aligne them for the next stage

• If the three instructions are «simple» no rotation is needed and they are forwarded to the three decoders with no intervention

• If in the three instructions there is one «complex» and two «simple» a rotation takes place so as to align the «complex» to decoder 0

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Decoding

Fetch andAligningIFU1-IFU2-IFU3

16 bytes

decodedm-operations

queue(up to 6 -m ops)

DEC2

RAT

3x118 bits

ROB: in the Pentium II40 slots: loaded with 3 u-ops max per clockROB

3x118 bits

MicroInstructionSequencer

MIS

(4+1+1 = 6) x 118 bits

DEC1

Decoder 1simple

Decoder 2simple

Decoder 0complex

RS 1 RS 2 RS 3 RS 4 RS 5

20 m-ops queue for the ResStations

From the RS to the FU

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DEC1 and DEC2 Stages

DEC1

Decoder 0complex

decodes IAinstructions

into1-4 m-ops

Decoder 1simple


into1 m-op

Decoder 2simple


into1 m-op

• If the decoded instruction is a JMP the instruction queue is immediately emplted and reloaded

• The m-ops are queued in the same order as they were produced. The queue has 6 slots

• The decoder 0 is able to convert in a single clock a complex instruction not longer than 7 bytes generating max 4 m-operations

• Decoders 1 e 2 are able to convert in a single clock a complex instruction not longer than 7 bytes generating max 1 m-operation

• Up to 6 m-operations per clock can be generated• In all other cases MIS The Micro Instruction Sequences is a ROM which stores

the m-operations associated to each complex IA instruction which cannot be decoded in a single clock period.

• The generated sequences (max 6 m-ops per clock) are directly fed into stage DEC2

DEC2• The static BTB (see next slide) is activated if among the m-operations of

the preceding clock there is a m-op branch not handled by the dynamic BTB (not detected as branch – it must noticed that here the instructions are already RISC type: two sources and one destination !!!)

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Static BTB

The P6 uses a static BTB in the stage DEC2 (the stage which decodes the opcode of the m-ops). It handles the branches not present in the dynamic BTB. It is “static” because uses static rules not depending on the previous instruction history. Obviously the static BTB updates the dynamic BTB

IP relative ?

Conditional ?

Back ?

no - takenyes

yesno

taken

no

taken

yes

not taken

The static prediction includes the destination address evaluation too

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RAT stage

EAXEBXECXEDXESIEDIESPEBP

012.............................39

RAT

Register Allocation Table(Register Renaming)

14

ROB stage

NB:Very often the «ports» are common to many functional units. The ports are the busses which link – for instance – the ROB with the FU and require always a lot of space in the IC

• The m-ops with the registers renamed in the RAT stage are stored in order three per clock in the ReOrdering Buffer which has 40 slots (much more in the modern processors which however derive from the P6 architecture)

• The Reservation Station (the unity which handles the functional units availability) extracts up to 5 m-ops per clock from the ROB (there are 5 ports – busses toward the RS) storing them in a buffer with 20 slots (subdivided per FU) whence they are extracted to be forwarded to the exec units

• After the execution the m-ops are stored back into the ROB together with the results. In the ROB there are two pointers : one for the «oldest» m-ops not yet retired and one for the first free slot (if any) where to store the new m-ops

• The m-ops are “committed” always three at time in order. This entails that no m-ops is comitted before a preceding branch has not been solved.

• The ROB can be viewed as a “ 40 instructions window”

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EX Stage(5 functional units only)

JMP xxxx

LoadUnit

StoreAddress

Unit

StoreDataUnit

PORT2 PORT3 PORT4

Jumpexecuti

onUnit

FP UnitFP Unit

IntegerUnit 1

PORT1PORT 0

ReorderBufferROB

ReservationStation

RS (20 slots)

Mov EAX, Mem

Mov Mem,EAX

INC EAX

FMUL ST0FDIV ST1

5 m-ops

Typical ìnstructions

Same portSame port

16

Instructions and m-ops execution

16 bytes

16 bytes

0

1

2

Prefetch 012345

ID queue

012

RAT,ROB

StatusMemoryaddress

m-op op-code renamed registers (RAT)

0

39

ROB (actually the size depends on the processor)

MISMIS

IFU1,IFU2,IFU3

3 CKDecoders

DEC1, DEC2

2 CK 2 CK

Memory address of the first corresponding IA instruction

17

m-ops in the ROB

• It must be noticed that in case of exception a flag in inserted into the m-op : the excepton is handled only when the m-op is retired. All precedingm-ops are retired (precise interrupt)

• m-ops states in the ROB:

SD: scheduled for execution. The m-op has been inserted in the RS queue but not yet sent to the FU

DP: dispatchable. It is in “pole position” in the EU queue EX: executed. It is being executed WB: write back. About to be rewritten in the ROB after the

execution. Unblocks other m-ops stalled waiting for its result RR: ready for retirement. The m-op can be retired RT: retired. The m-op is being retired

• Memory address: it is the memory address of the first byte of the IA32 instruction corresponding to the m-op(s). The address fied for the following m-ops is empty(a IA32 instruction can correspond to many m-ops). An address, therefore, signals a new IA32 instruction

• m-op type: branch or not branch

• Allocation register: one of the 40 allocation registers

18

RESET

vvvvvvvviiiiiiii

iiiiiiiiiiiiiiii

PrefetchStreaming

Buffer (32 bytes)Decoders

Coda ID

RAT/ROB

StatusMemoryaddress

0

39

AL RESET

MIS

Jump 8 bytesv=valid code bytei=invalid bytes

N.B. The dynamic BTB is obviously unable to predict the branch

InitialJUMP

m-op op-coderenamed

registers (RAT)

19

RESET –IFUi stages

vvvvvvvviiiiiiii

iiiiiiiiiiiiiiii

FFFFFFF:0FFFFFFFF:F

Prefetch StreamingBuffer (IFU1) (stores 32

bytes – a cache line)

NB Each clock a 32 bytes line is read by IFU1. In case of «pipeline traffic jam», because of the decoders, the pipeline stalls

First instruction boundary

i: not signifcant bytes

Jump

• The first instruction is always a backward jump (instruction present in IFU1)

• In IFU2 the first instruction boundary is detected (8 bytes). In the remaining 24 bytes other not-signifcant instructions

• In IFU3 the first instruction is aligned to 0

20

RESET

JMP

PrefetchStreaming

buffer DecodersCoda ID

RAT/ROB

0

39

MIS

StatusMemoryaddress m-op op-code

renamed registers (RAT)

21

RESET –DECi stages

• Instructions in the stages from IFU1 to DEC2 are emptied-. This provokes a stall in the pipeline which must reload instructions from the jump address. The m-op is stored in the queue of the decoded instructions

• The detected instructions are decoded by DEC1.

• DEC1 transforms the JMP in a jump m-op (in P6 all jumps are transformed in Branches Taken )

22

RESET

Branch m-op

PrefetchStreaming

buffer DecodersID queue

RAT/ROB

0

39

RESET

MIS



23

RESET – RAT stage

• The m-op is extracted from the queue of the decoded instructions (which still has the initial order) and inserted in the RAT stage for possible register assignment (not used for branch)

24

RESET

PrefetchStreaming


Branch m-op

RAT/ROB

0

39

RESET

MIS



25

RESET – ROB and RS stage

• From the ROB the m-op is then sent to the RS queue (4x5 slots) as soon a slot for its FU is available. This operation can be done in parallel to the previous one if there are slots available. This is the case of the first instruction at the RESET

• The m-op is then sent to the first free ROB slot (normally three of them are trasferred in order to the ROB if there are free slots)

26

RESET

PrefetchStreaming


RAT/ROB

FFFFFFFF0 branch m-op none0

39

RESET

MIS



27

RESET – execution and retirement

• Three m-ops are retired in order bewteen them too per clock.

• The RS after a branch execution informs the BTB in order to update the prediction.)

• The m-op after the execution is tagged as «executed» in the ROB. If a m-op produces a result (typically a register value) for another m-op (stalled) waiting for it, the waiting m-op status becomes “ready” in the ROB and inserted in the RS as soon as a slot is free

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020000042020000044020000045020000051

020000055020000057020000000

020000000020000001

02000000302000000402000000A02000000C02000000F

020000010020000014

02000001602000001B020000021020000025020000026

02000002C02000002F020000034

020000037

EXRREX

SD

DPRR

RTRTRTRRRRRREXWBRRRREXDPSDRRRRRRRRRRRRWBEXRRRRRRRRSDRR

ROB start

non-branch m-op

non-branch m-op

non-branch u-opnon-branch m-op

branch -m op

non-branch m-opnon-branch m-opnon-branch m-op

non-branch m-op

non-branch m-op



non-branch m-op

non-branch m-op



non-branch m-op

non-branch m-op



non-branch m-op

non-branch m-opnon-branch m-op


Mem. Addr. Renamed registerStato m-operation

123456789

101112131415161718192021222324252627282930313233343536373839

0

Instructions execution

29

ROB – description (1)

19. This m-op corresponds to the two bytes long IA instruction starting at address 0200000A. It is now being executed and can last more than a clock. At the end its status will be changed from EX to RR. It will be retired when

Its execution is completedd The result is written in slot 19 The other m-ops in the slots 20 e 21 are RR All previous m-ops in the slots 13 -18 have been already

retired

13. This is the ROB oldest m-op which corresponds to IA instruction whose first byte is at address 02000000 which will be retired together the m-ops of slots 14 and 15

14. This m-op (together those in slots 15 and 16) corresponds to an IA instruction 2 bytes long starting at address 02000001. It must be noticed that the 3 m-ops related to the same IA instruction are NOT retired in the same clock. The address of the first byte of the following IA instruction is 02000003 (slot 17)

15. See previous description (m-op now retired)

16. See previous description (m-op ready for retirement)

17. This m-op corresponds to a IA instruction one byte long at address 02000003. It is ready for retirement and will be retired with m-ops in slots 16 and 18

18. This m-op is the only one generated by the 6 bytes long IA address at addresses 02000004-02000009. It is RR

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26. It derives again from the same IA instruction of the slots 24 and it is RR together with the m-ops in the slots 25 and 27

…………………………………………………………….

20. This m-op is the only one generated by the instruction at addresses 0200000C-0200000E. Its execution is complete and the result is being written in the slot 20 (status WB). The m-op will be then RR but it will be not retired until the m-ops in the slots 19 and 21 are RR

21. This m-op (similar to that of slot 22) corresponds to a single byte IA instruction at address 0200000F. It is RR but must wait for m-ops in the slots 19 and 20.

22. Also this m-op (similar to that of slot 21) corresponds to the same single byte IA instruction at address 0200000F. It will be retired together with the m-ops in the slots 23 and 24

23. This m-op derives from IA instruction at addresses 02000010-02000013. It is still being executed (EX). After execution its status will be WB and afterwards it will become RR and retired together with m-ops in the slots 22 and 24 (when they will be RR)

24. This m-op (as those of the slots 25 and 26) corresponds to the two bytes IA instruction starting at address 02000014. It is waiting for execution and on the RS queue top (DP status). It will be retired together with m-ops in the slots 22 and 23

25. This m-op derives form the same instruction of m-op in the slot 24 but its status is SD that is is already in the RS queue but not on top

31


N.B. If the predction had been detected as incorrect the m-op of the slot 8 and all the following m-ops would have been cancelled

……………………………………………………………………….

1. This m-op derives form the one-byte IA instruction at address 02000044. It is RR and will be retired together with m-ops in the slots 0 and 2 as soon: The m-ops of the slots 0 and 2 have completed their

execution and their results are in the slots 0 and 2 All m-ops in the slots 13-39 have been already retireThe m-op in the slot 2 derives from IA instruction at hexadecimal addresses 02000045-02000050 (12 bytes).

……………………………………………………………………6. This m-op corresponds to the IA instruction at addresses

02000055-02000056

7. This m-op is an already executed branch (RR status) corresponding to the IA instruction at address 02000057. It will be retired together with m-ops of the slots 6 and 8. The branch was predicted as taken and the prediction was detected as correct during the execution, then ..

8. .. the m-op of this slot derives from the iA instrcution at address 02000000 (branch destination address)

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020000042020000044020000045020000051

020000055020000057020000000

02000000302000000402000000A02000000C02000000F

020000010020000014

02000001602000001B020000021020000025020000026

02000002C02000002F020000034

020000037

EXRREX

SD

DPRR

RRRRRREXWBRRRREXDPSDRRRRRRRRRRRRWBEXRRRRRRRRSDRR

ROB start

non-branch m-op

non-branch m-op


branch -m op


non-branch m-op


non-branch m-op

non-branch m-op

non-branch m-op



non-branch m-op

non-branch m-op



non-branch m-op

non-branch m-opnon-branch m-op


Mem. Addr. Renamed registerStato m-operation

123456789

101112131415161718192021222324252627282930313233343536373839

0

After retiring13,14,15

1 p6 architecture computer architecture m. 2 pipeline between the three main sections compensation...

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