1 of 16 april 25, 2006 system-level modeling and synthesis techniques for flow-based microfluidic...

1
1 of 16 April 25, 2006 System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration Biochips Contact: Wajid Hassan Minhass Email: [email protected] Technical University of Denmark Wajid Hassan Minhass Advisors: Paul Pop, Jan Madsen The proposed framework is targeted at facilitating programmability and automation. It is expected to enable designers to auto-generate chip architecture and to take early design decisions by being able to evaluate their own proposed architecture, minimizing the design cycle time. Biochips are replacing conventional biochemical analyzers and are able to integrate on-chip the necessary functionalities for biochemical analysis using microfluidics. In Flow-based biochips, liquid samples of discrete volume flow in the on-chip channel circuitry. The biochip has two layers (fabricated using soft lithography): flow layer and control layer. The liquid samples are in the flow layer and are manipulated through microvalves in control layer. By combining these microvalves, more complex units like mixers, micropumps etc. can be built with hundreds of units being accommodated on a single chip. This approach is called microfluidic Large-Scale Integration (mLSI). Microfluidic Biochips Microval ve Biochip: Functional View Architectural Synthesis: (Allocation, Placement and Routing) Application Mapping: (Binding, Scheduling and Fluid Routing) Starting from a given microfluidic component library and a desired application, our synthesis approach automatically synthesizes the biochip architecture aiming to minimize the application completion time. Currently, biochip designers are using full-custom and bottom-up methodologies involving multiple manual steps for designing chips and executing experiments. With chip design complexity on the rise (technology scaling at rapid speed) and multiple assays being run concurrently on a single chip (commercial chip with 25,000 valves and about a million features running 9,216 polymerase chain reactions in parallel), bottom-up manual methodologies are fast becoming inadequate and would not scale for larger, more complex designs. Objective: Devise a system-level modeling and synthesis framework for flow-based biochips capable of handling larger, more complex designs. List Scheduling-based binding and scheduling heuristic utilized (we have also proposed a constraint programming based approach for finding the optimal solution). Since routing latencies are comparable to operation execution times, thus fluid routing (contention aware edge scheduling) is also taken into account (boxes with labels Fx in figure below) along with the operation scheduling (boxes with labels Ox). As an output, we generate the control sequence for a biochip controller for auto executing the application on the specified biochip. Detect or Mixer Filter In 3 In 4 In 2 In 1 Out 3 Out 2 Out 1 Sourc e Sin k Mix (4) Mix (4) Mix (4) Mix (5) Heat (3) Mix (4) Mix (3) Heat (2) Filt er (5) Mix (2) O1 O2 O3 O5 O4 O6 O7 O8 O9 O10 Waste Input Motivation and Objective Contribution Application Model System Model Microfluidic Mixer Application Model: Directed sequencing graph. Architecture Model: We have proposed a topology graph-based approach. We propose a system-level top-down modeling and synthesis framework in order to synthesize the biochip architecture based on an application and to map the application onto the architecture while minimizing the application completion time and satisfying the constraints (e.g., resource, dependency). Architectural Synthesis In 1 In 2 In 3 In 4 Biochip: Schematic View z 2 z 3 z 4 z 5 z 7 z 8 z 1 1 Out 2 Out 3 Out 1 v 1 v 2 v 3 v 4 v 6 v 5 Detect or Filte r z 1 0 z 1 2 Mixe r z 9 z 1 3 z 1 z 6 v 7 a Pressure source z 1 Contro l layer Flow layer Valve v a Fludic input Mixer 1 Mixer 2 Mixer 3 Heater 1 Filter 1 F26-1 F30-1 F25-1 F16 F32-1 F26-1 F30-1 F22-1 0 s 16 s 23.5 s 42.5 s 56 s 1 2 3 4 56 7 8 9 10 11 O1 O3 O4 O2 O6 O7 O5 O8 O9 O10 F1 F4 F2 F5 F14 F10 F9 F3 F6 F25- 1 F19 F3 F6 F15 F14 F19 F19 F19 F23

Upload: oswald-craig

Post on 21-Jan-2016

212 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: 1 of 16 April 25, 2006 System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration Biochips Contact: Wajid Hassan

1 of 16April 25, 2006

System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration

Biochips

Contact: Wajid Hassan MinhassEmail: [email protected] Technical University of

Denmark

Wajid Hassan Minhass Advisors: Paul Pop, Jan Madsen

The proposed framework is targeted at facilitating programmability and automation. It is expected to enable designers to auto-generate chip architecture and to take early design decisions by being able to evaluate their own proposed architecture, minimizing the design cycle time.

Biochips are replacing conventional biochemical analyzers and are able to integrate on-chip the necessary functionalities for biochemical analysis using microfluidics.

In Flow-based biochips, liquid samples of discrete volume flow in the on-chip channel circuitry.

The biochip has two layers (fabricated using soft lithography): flow layer and control layer. The liquid samples are in the flow layer and are manipulated through microvalves in control layer.

By combining these microvalves, more complex units like mixers, micropumps etc. can be built with hundreds of units being accommodated on a single chip. This approach is called microfluidic Large-Scale Integration (mLSI).

Microfluidic Biochips

Microvalve

Biochip: Functional View

Architectural Synthesis: (Allocation, Placement and Routing)

Application Mapping: (Binding, Scheduling and Fluid Routing)

Starting from a given microfluidic component library and a desired application, our synthesis approach automatically synthesizes the biochip architecture aiming to minimize the application completion time.

Currently, biochip designers are using full-custom and bottom-up methodologies involving multiple manual steps for designing chips and executing experiments.

With chip design complexity on the rise (technology scaling at rapid speed) and multiple assays being run concurrently on a single chip (commercial chip with 25,000 valves and about a million features running 9,216 polymerase chain reactions in parallel), bottom-up manual methodologies are fast becoming inadequate and would not scale for larger, more complex designs.

Objective: Devise a system-level modeling and synthesis framework for flow-based biochips capable of handling larger, more complex designs.

List Scheduling-based binding and scheduling heuristic utilized (we have also proposed a constraint programming based approach for finding the optimal solution).

Since routing latencies are comparable to operation execution times, thus fluid routing (contention aware edge scheduling) is also taken into account (boxes with labels Fx in figure below) along with the operation scheduling (boxes with labels Ox).

As an output, we generate the control sequence for a biochip controller for auto executing the application on the specified biochip.

Detector

Mixer

Filter

In3

In4

In2

In1

Out3

Out2

Out1

Source

Sink

Mix (4)

Mix (4)

Mix (4)

Mix (5)

Heat (3)

Mix (4)

Mix (3)

Heat (2)

Filter (5)

Mix (2)

O1 O2 O3

O5

O4

O6

O7 O8

O9

O10

WasteInput

Motivation and Objective

ContributionApplication Model

System Model

Microfluidic Mixer

Application Model: Directed sequencing graph.

Architecture Model: We have proposed a topology graph-based approach.

We propose a system-level top-down modeling and synthesis framework in order to synthesize the biochip architecture based on an application and to map the application onto the architecture while minimizing the application completion time and satisfying the constraints (e.g., resource, dependency).

Architectural Synthesis

In1

In2 In

3In

4

Biochip: Schematic View

z2

z3

z4

z5

z7

z8

z11

Out2Out

3Out

1

v1

v2

v3

v4

v6

v5

Detector

Filter z10

z12

Mixer

z9

z13

z1 z

6

v7

a

Pressure source z

1

Control layer

Flow layer

Valve v

a

Fludic input

Mixer1

Mixer2

Mixer3

Heater1

Filter1

F26-1

F30-1 F25-1 F16

F32-1 F26-1

F30-1

F22-1

0 s 16 s 23.5 s 42.5 s 56 s

1 2 3 4 5 6 7 8 9 10 11

O1

O3

O4

O2

O6

O7

O5

O8

O9

O10

F1 F4

F2 F5 F14

F10 F9

F3 F6

F25-1

F19

F3 F6

F15 F14

F19

F19

F19F23