1 objective - university of utahccharles/ece6730/project/project_2009.pdf · ece 6730: rf...

ECE 6730: RF Integrated Circuit Design Spring 2009

Course ProjectTopic: RF Down-Conversion ChainDue Dates: Mar. 27, Apr. 15 (Interim reports), May. 11 (Final report)

1 Objective

The objective of this project is to familiarize the student with the trade-offs and design choicesencountered in the design of an RF down-conversion chain. The specifications have been designedto give students freedom to experiment with different architectures and circuit toplogies. Thespecifications are based on the receive band of a fictional cellular phone standard.

Since the design of a complete down-conversion chain is a substantial undertaking, the designwill be done in an incremental manner. The first project will encompass the design of the LNA,the second project will encompass the design of the mixer, and the third project will involve thedesign of the VCO and the integration of the three blocks.

The performance metrics fall into six different areas: input match, noise figure, linearity,gain, power consumption, and layout area (you will not have to layout your circuits, this willbe an estimate based on your schematics, see Table 1 for details). In each area the studentprojects will be ranked against each other, and part of the final grade will be determined by theseperformance rankings. Thus, the student may choose to focus on one particular area, or attemptto compromise and perform reasonably well in all of the areas. Different component topologieswill enhance performance in certain areas, so in making design choices you should keep in mindwhich of these areas you would like to perform well in.

Interim reports will be turned in with each of the projects, and are primarily intended toensure that the student is on track for completing the overall design. The majority of the projectgrade will be determined by the final report.

2 Requirements

• The design will be implemented in a representative 0.13 µm CMOS process, with a supplyvoltage of 1.2 V.

• Inductors and capacitors will be implemented using the provided models which includeestimated parastics. It may be helpful to do the initial design using ideal components (fromanalogLib) and then sub in the parasitic-laden versions once you have it working.

• Resistors will be assumed to be ideal, and can be taken from the analogLib library.

• Varactors will be implemented using MOS varactors.

• You can use one ideal transformer in your design for single-ended to differential conversion.If you choose to do this, you must factor in 1.5 dB of losses for the transformer/balun to youroverall system performance calculations and 50,000 µm2 of additional area to your overallsystem area.

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• You can use one ideal current source per block for biasing purposes, and this current sourcemay not drive your functional blocks. For example, the current source can drive a diode-connected transistor, whose gate voltage is then applied to your LNA drive transistor to setthe current to the desired value.

• The only voltage source permitted is for the power supply, internal bias voltages must bederived from your circuits.

• The standard we are designing for has 20 channels (each with a bandwidth of 5 MHz)centered around 2 GHz.

• The intermediate frequency at the output of the mixer must be 200 MHz, and your VCOmust tune over a range of 200 MHz to account for process variation (i.e., your VCO musttune from 1700 - 1900 MHz or from 2100 - 2300 MHz).

3 Tools

The design will be carried out using Cadence, available in the ECE department UNIX and Linuxlabs. It is assumed that students are familiar with the Cadence design tools from previous courses(such as the prerequisite, ECE 5720). If necessary, a Cadence tutorial will be held to review theoperation of these tools. It may be useful to review the Cadence tutorials from ECE 5720, whichcan be found at http://www.ece.utah.edu/~harrison/ece5720/. A review of Cadence can alsobe found in Dr. Brunvand’s text, a preliminary version of which can be downloaded from theECE 6830 website (http://www.eng.utah.edu/~cs5830/), chapters 2 and 3 will be most usefulfor our purposes. The help files that accompany Cadence on the ECE servers will also be useful.

4 Grading

The overall grading breakdown for the project is shown below:

First interim report (due with project 1) . . . . . . . . . . . . . . 10%Second interim report (due with project 2) . . . . . . . . . . . . 10%Final Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20%Final report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60%

The grading for the interim reports will be lenient, as they are primarily intended to ensurethat the student is on track for completing the final system design. The performance componentwill be divided into 10% for the performance of the overall system, and 10% for the performanceof the individual blocks in isolation. The performance of the overall system will be divided amongthe five different areas mentioned previously. For each area, the projects will be ranked andseperated into 4 quartiles. The students in the top quartile will receive 4/4 for that specification,the students in the next quartile will receive 3/4, etc. Additionally, the top student in each areawill receive one bonus point as well as the respect and accolades of his/her peers. The performanceof each block will be graded similarly.

The 60% final report component of the overall grade will be broken down as follows:

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System level design choices and justification . . . . . . . . . . . . . . . . . . . . . . . . . . 10%LNA design and justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%Mixer design and justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%VCO design and justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%Schematics, waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%Report quality (writing style, structure, clarity) . . . . . . . . . . . . . . . . . . . . . . 10%

5 Report

5.1 First Interim Report (due Mar. 24)

The first interim report will describe the design of the LNA, and should consist of the sectionsdescribed below:

• A brief introduction describing which performance parameters you have chosen to focus on,and the architectural choices that you have made as a result of this.

• A section describing your design, the strategies you used for sizing the components, and thetrade-offs encountered. You must also provide a transistor level schematic for the LNA. Thissection will be graded on a complete/incomplete scale in this report, but you might as welldo a good job since you can then include it in your final report.

• Waveforms and metrics from required performance simulations (see Section 8).

5.2 Second Interim Report (due Apr. 7)

The second interim report will describe the design of the mixer, and should consist of the sectionsdescribed below:

• A brief introduction describing which performance parameters you have chosen to focus on,and the architectural choices that you have made as a result of this.

• A section describing the mixer you have designed. You should describe your design, why youchoose the topology, the strategies you used for sizing the components, and the trade-offsencountered in the design. You must also provide transistor level schematics. This sectionwill be graded on a complete/incomplete scale in this report, but you might as well do agood job since you can then include it in your final report.

• Waveforms and metrics from required performance simulations (see Section 8).

5.3 Final Report (due Apr. 28)

I would like the final report to be formatted in the form of a paper that would appear in anIEEE publication. Since (most of) you are graduate students, there is a good chance you willfind yourselves publishing your work at some point, and now is as good a time as any to getfamiliar with the formatting used. Templates for your paper-style reports can be found at http://www.ieee.org/web/publications/authors/transjnl/index.html. I recommend using theLATEX template, but for those of you who prefer inferior software there is a Word template availableas well.

Here are some links to LATEX tools that will be useful if you decide to go that route:

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Device AreaMOSFET (Width+ 1 µm)× LengthResistor R (kΩ)× 200 µm2

Capacitor C (fF )× 0.25 µm2

Inductor L (nH)× 20, 000 µm2

Table 1: Formulae for calculating the layout areas for your components.

• LATEX tutorial: http://tobi.oetiker.ch/lshort/lshort.pdf

• Free version of LATEX for Windows (called Miktex): http://miktex.org/2.7/setup

• Free LATEX editor for Windows: http://www.texniccenter.org/

The final report will contain descriptions of the designs for each component, as well as theresults of performance simulations. The final report will also contain a number of performancecharacterizations for the overall system. The final report should consist of the sections describedbelow:

• An introduction to the problem, and a description of the performance parameters you havechosen to design for.

• A section describing your top level architecture (including a high level block diagram).

• One section for each of the components you have designed, describing the architecture youselected (and how that impacts performance of the system as a whole), your approachfor transistor/passive sizing, and any tradeoffs that were encountered in the design of thecomponent. You must also include the transistor level schematic for each component, andreproduce the performance plots and tables required for each component.

• A section describing the performance of your system in the specified areas (see Section 8).This section should include a table summarizing the relevant performance parameters foryour design.

• A conclusion summarizing what you have learned in designing your project, and anythingthat you would do differently if you were to do it again.

6 Getting Started

This section will provide you with the information you need to get started running simulationsfor the project. It is assumed that the student has a working knowledge of Cadence.

1. Start an xterm session on one of the ECE Unix or Linux machines.

2. Add the following lines to your .tcshrc file:set path=($path /uusoc/facility/cad common/local/bin/S09)setenv LOCAL CADSETUP /uusoc/facility/cad common/local/class/6830/S09The directory in the second line is 6830 as we are borrowing the setup scripts from Prof.Brunvand’s VLSI Architecture class.

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3. Go to your home directory, and make a directory called Cadence6730 (this is the directoryfrom which you will invoke Cadence).

4. Go to this newly created directory and typeln -s /uusoc/facility/cad common/NCSU/CDK-F07/.cdsinit . (this file does some ini-tialization when you start up Cadence).

5. While still in the same directory, cp /home/ccharles/Cadence6730/.cdsenv ./.cdsenv(this file sets some environment variables for simulations).

6. While still in the same directory, cp /home/ccharles/Cadence6730/cds rename.lib ./cds.lib(this file creates the default libraries needed for the course).

7. Finally, type cad-ncsu to start up Cadence, and you are on your way!

7 Instantiating Components

This section will provide details on how to instantiate basic circuit elements in your schematic.For general information on how to use Cadence, see Prof. Brunvand’s CS 5710 tutorials athttp://www.cs.utah.edu/classes/cs5710/.

• MOSFETs: type i to instantiate a new component, then from the analogLib library browseto the Actives section, and select nmos or pmos. Under Model name enter nfet130 orpfet130. Enter the desired width and length (no less than 130n m) into their respectivefields, and if you wish to divide the transistor into a number of smaller ”fingers”, use theMultiplier field.

• Passives: for your intial design, I would recommend using ideal components, and then re-placing these with the lossy models once you have it working. For ideal components, fromthe analogLib library, browse to the Passives section, and select cap, ind, or res. Fornon-ideal components, from the Passives library, select either cap real or ind real. Wewill use ideal resistors.

• Sources: from the analogLib library browse to the Sources section, where you can selectindependant or dependant sources, or globals (for vdd and gnd).

8 Performance Simulations

8.1 Low Noise Amplifier

Include waveform plots in your report as specified in each of the following simulations, and alsoinclude a table which summarizes your designs performance in each of the following areas. It isrecommended that you create seperate cell views for each of the simulations described below. Itmay also be easiest to create a symbol for your LNA that can be instantiated in each of yoursimulation schematics so that changes made to the LNA are reflected in all of the schematics.

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8.1.1 Area Consumption

No simulation is required for this metric, just add up the areas for all for all of the componentsin your LNA schematic. Be sure to include blocking capacitors and biasing circuitry. If you haveused a differential topology, you may divide your total area by two when reporting the final value.

8.1.2 Power Consumption

1. Ground the input and output of your LNA (if you have no blocking capacitor at the outputjust leave it open).

2. Open the Analog Design Environment, and enable a dc simulation, with Save DC OperatingPoint selected.

3. Run the simulation, and when it is finished, in the Analog Design Environment selectResults->Annotate->DC Operating Point. DC bias currents and voltages will now beshown on your schematic, as seen in Fig. 1.

4. Record the total power consumption as the power supply voltage (1.2 V) multiplied by thecurrent drawn from the power supply (13.94 mA in Fig. 1). No waveforms need to bereported for this simulation. If you have used a differential topology, you may divide yourtotal power consumption by two when reporting the final value.

8.1.3 S-Parameters

1. Instantiate ports (analogLib->Sources->Ports->port) at the input and output of yourLNA.

2. Edit the input port so that the Resistance is 50 Ω, the Port Number is 1, and the SourceType is dc.

3. Edit the output port in the same way, except set the Port Number to 2. Here we areassuming that the LNA will be driving a 50 Ω output impedance. In reality the LNA willbe driving the mixer, so once we have designed the mixer the LNA may need some tweakingaccording to the chance in output loading.

4. Open the Analog Design Environment and enable an sp simulation. Select the ports in yourschematic for the Ports entry, and select Frequency as the Sweep Variable with SweepRange set to Start at 1.5G and Stop at 2.5G. Set Sweep Type to Linear and select Numberof Steps and set it to 100.

5. Run the simulation, then select Results->Direct Plot->Main Form.

6. Using the resulting form, plot S11 with Plot Type set to Rectangular and Modifier setto dB20.

7. Place markers on the resulting plot at 1.95 GHz and 2.05 GHz (the extremes of the band thatwe are interested in recovering). Quote the maximum of these values as the S11 measurementin your performance summary table, and include this plot in your report.

8. Repeat the previous two steps for S21, this time quoting the minimum of the two values inyour performance summary table.

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Figure 1: Schematic for power consumption simulation.

8.1.4 Noise Figure

1. Follow steps 1-4 from Section 8.1.3. In the Choosing Analysis form in step 4, select yesfor Do Noise and select the input and output ports.

2. Now we need to modify the schematic to include the effects of induced gate noise. For eachnoise critical transistor in your LNA (generally, any transistor that appears in the signalpath), add the circuitry described in Lecture 10 for induced gate noise simulations. Anexample for an LNA with one noise critical transistor is shown in Fig. 2. The core LNAcircuitry is in the top half of the figure, and the additional dummy transistor for generatingthe induced gate noise are in the lower half of the figure. The additions that must be madeto the core LNA circuitry are highlighted in red.

3. For the current controlled current sources, use analogLib->Sources->Dependant->cccs.Each cccs requires a dc voltage source (with DC Voltage set to 0) to be inserted where thecontrolling current is to be measured (in Fig. 2 the dc voltage source monitoring the draincurrent of M1 is highlighted in red). In the properties of each cccs, set Type of Source tocccs, set Current gain to the appropriate value, and set Name of voltage source to thename of the dc voltage source that monitors the controlling current.

4. For the voltage buffers, use analogLib->Sources->Dependant->vcvs with the Voltage

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gain set to -1.0.


6. Using the resulting form, select NF under Function, and plot the noise figure with theModifier set to dB10. Be sure that Plotting Mode is set to Append, select NFmin underFunction, and plot the minimum noise figure on the same plot.

7. Place markers on the noise figure at 1.95 GHz and 2.05 GHz, and include this plot in yourreport, citing the higher of the two values in your performance summary table.

8.1.5 IIP3

1. Instantiate a port (analogLib->Sources->Ports->port) at the input and output of yourLNA.

2. Edit the input port so that the Resistance is 50 Ω, the Port Number is 1, and the SourceType is sine. Fill in Fund1 for Frequency name 1, 1.95 GHz for Frequency 1, and prf forAmplitude 1 (dBm). Click on Display second sinusoid and fill in Fund2 for Frequencyname 2, 2.05 GHz for Frequency 2, and prf for Amplitude 2 (dBm).

3. Edit the output port so that the Resistance is 50 Ω, the Port Number is 2, and the SourceType is dc.

4. Open the Analog Design Environment, and click on Variables->Copy From Cellview. Theprf variable should now show up in the Design Variables window. Double click on it andgive it some arbitrary value (it will be swept in the simulation so the value doesn’t make adifference) such as 0.

5. Now enable a pss simulation.

6. Verify that Fund1 and Fund2 show up in the Fundamental Tones window, and select BeatFrequency and Auto Calculate.

7. Fill in 60 for Number of harmonics.

8. Select conservative for Accuracy Defaults.

9. Select Sweep and enter prf for Variable Name.

10. Select Start-Stop for Sweep Range, and set it to -30 to 10.

11. Select Linear for Sweep Type, and set the Step Size to 5.


13. Using the resulting form, select IPN Curves under Function, then select Variable Sweep.

14. Enter -20 for Input Power Extrapolation Point (you may need to replot it with a differentvalue here depending on how your curves look).

15. Make sure that Input Referred IP3 is selected, with Order set to 3rd.

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Figure 2: Schematic for noise figure simulation.

16. Select 2.15G for 3rd Order Harmonic, and select 2.05G for 1st Order Harmonic.

17. Move to the schematic window, click on the output port, and hit escape.

18. Your plot should look something like the example in Fig. 3. From the fundamental youcan clearly see where the 1-dB compression point occurs, your IP3 point should occur at ahigher power. You may need to replot with a different Input Power extrapolation, chooseone in a range where 3rd order curve has about the right slope (as in Fig. 3. Include this

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Figure 3: Example plot from IP3 simulation.

plot with your report, and cite the IIP3 value in your performance summary table.

19. For more information on IP3 simulations, open Help->Cadence Documentation and browseto Spectre RF->SpectreRF Simulation Option User Guide->Simulating Low-Noise Amplifiers.

8.2 Mixer

Include waveform plots in your report as specified in each of the following simulations, and alsoinclude a table which summarizes your designs performance in each of the following areas. It isrecommended that you create seperate cell views for each of the simulations described below. Itmay also be easiest to create a symbol for your mixer that can be instantiated in each of yoursimulation schematics so that changes made to the mixer are reflected in all of the schematics.


No simulation is required for this metric, just add up the areas for all for all of the componentsin your mixer schematic. Be sure to include blocking capacitors and biasing circuitry. If youhave used a topology with a differential RF input, you may divide your total area by two whenreporting the final value.

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1. Small signal ground the input and output of your mixer (The required bias voltages stillneed to be present).


3. Run the simulation, and when it is finished, in the Analog Design Environment selectResults->Annotate->DC Operating Point. DC bias currents and voltages will now beshown on your schematic, as seen in Fig. 1 for the LNA.

4. Record the total power consumption as the power supply voltage (1.2 V) multiplied by thecurrent drawn from the power supply (13.94 mA in Fig. 1). No waveforms need to bereported for this simulation. If you have used a topology with a differential RF input, youmay divide your total power consumption by two when reporting the final value.

8.2.3 Conversion Gain

1. Add ports for the RF, LO, and IF signal inputs to your mixer. If your mixer requires differen-tial signals then you will have to add ideal transformers (xfmr) from the analogLib library,configured to act as baluns as shown in Fig. 4. If the single-ended driving impedanceis matched to the differential input impedance then the transformer should have a pri-mary:secondary turn ratio of 1:

√2, as explained in http://www.atmel.com/dyn/resources/

prod_documents/doc5359.pdf. You may use ideal capacitors for the blocking capacitorsfrom the baluns.

2. Add ideal load capacitors of 0.5 pF to your output nodes (one for each if you have a differ-ential output).

3. Configure the RF and IF ports with a Source type of dc, and the LO port with a Sourcetype of sine, a frequency name, a frequency (1.8 GHz if you plan on using low-side injectionor 2.2 GHz for high-side injection), and an amplitude (choose this based on what you plando design your LO to drive, this will be a design parameter).

4. Open the Analog Design Environment and select Analyses->Choose.

5. Select pss, then make sure Beat Frequency and Auto Calculate are selected.

6. Under Output Harmonics set Number of Harmonics to 0, and select conservative underAccuracy Defaults.

7. Click Apply, then select a pxf analysis.

8. Set Start-Stop of the Frequency Sweep Range to go from 1M to 400M, and set SweepType to Linear with Number of Steps set to 50.

9. Under Sidebands select Maximum sideband and set it to 3.

10. For Output, select voltage and select the appropriate nodes (for the IF) on your schematic.

11. Click OK and run the simulation.

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Figure 4: Example schematic for conversion gain simulation.

12. Select Results->Direct Plot->Main Form and then select pxf under Analysis.

13. Make sure that Voltage Gain, spectrum, and dB20 are selected, and then select the RFport on the schematic.

14. Zoom in on the frequency range around 2 GHz and place a marker at 2 GHz. Include thisplot with your report and quote the conversion gain at 2 GHz in your performance summarytable.

8.2.4 LO Feedthrough

1. Use the same schematic as shown in Fig. 4 for the conversion gain, except reconfigure theRF port with a Source Type of sine, with the frequency set to 2 GHz (give it a name aswell) and Amplitude 1 (dBm) set to -30.





6. Select Results->Direct Plot->Main Form and select Voltage under Function.

7. Choose Differential Nets under the Select option if you have a differential output, setSweep to spectrum, set Signal Level to peak, and choose dB20 for Modifier.

8. Select the IF output nets on the schematic to plot the results. Place a marker on theharmonic that appears at your LO frequency (1.8 GHz for low side injection and 2.2 GHzfor high side injection) in the resulting plot.

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9. Turn in this plot with your report, and quote the marker value for the LO feedthroughmetric in your performance summary table.

8.2.5 Noise Figure

1. Use the same schematic as shown in Fig. 4, except remove the IF port (and accompanyingbalun circuitry if you have a differential output).

2. Configure the RF port with a Source type of dc, and the LO port with a Source typeof sine, a frequency name, a frequency (1.8 GHz if you plan on using low-side injection or2.2 GHz for high-side injection), and an amplitude (choose this based on what you plan todesign your LO to drive, this will be a design parameter).



5. Under Output Harmonics set Number of Harmonics to 0, and select moderate under AccuracyDefaults.

6. Click Apply, then select a pnoise analysis.

7. Set Start-Stop of the Frequency Sweep Range to go from 1K to 4G, and set Sweep Typeto Logarithmic with Points Per Decade set to 10.


9. For Output, select voltage and select the appropriate nodes (for the IF) on your schematic.

10. For Input Source select port and select the RF port.

11. For Reference side-band select Enter in field and enter -1.


13. Select Results->Direct Plot->Main Form and then select pnoise under Analysis.

14. Select Noise Figure and click on Plot to plot the waveform.

15. Zoom in on the frequency range around 200 MHz and place a marker at 200 MHz. Includethis plot with your report and quote the noise figure at 200 MHz in your performancesummary table.

8.2.6 IIP3

1. Use the same schematic as shown in Fig. 4.

2. Configure the IF port with a Source type of dc, and the LO port with a Source type ofsine, a frequency name, a frequency (1.8 GHz if you plan on using low-side injection or2.2 GHz for high-side injection), and an amplitude (choose this based on what you plan todesign your LO to drive, this will be a design parameter).

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3. Configure the RF port with a Source type of sine, a frequency name, and a frequencyof 2 GHz. Set Amplitude 1 (dBm) to the variable name prf, and click on Display smallsignal params and enter prf in the PAC Magnitude (dBm) field that appears.

4. Open the Analog Design Environment and click on Variables->Copy From Cellview. Theprf variable should now show up in the Design Variables window. Double click on it andgive it some arbitrary value (it will be swept in the simulation so the value doesn’t make adifference) such as 0.

5. Now select Analyses->Choose.



8. Select Sweep, make sure that Variable is selected, and enter prf for Variable Name.

9. Under Sweep Range, select Start-Stop and set it to start at -25 and stop at 5. Under SweepType, select Linear, Step Size and set it to 5.

10. Click Apply, then select a pac analysis.

11. Under Frequency Sweep Range (Hz) enter 2.002G for Freq.

12. Under Sidebands select Array of Indices and enter -9 -11 for Additional indices (besure to include the space between the two numbers).


14. Select Results->Direct Plot->Main Form and then select pac under Analysis.

15. Select IPN Curves under Function, select Variable Sweep for Circuit Input Power, andset Input Power Extrapolation Point (dBm) to -20.

16. Select Input Referred IP3, then select 3rd for Order, and select -11 198M under 3rdOrder Harmonic and -9 202M under 1st Order Harmonic.

17. Click on Plot to display the resulting IIP3 plot. The result should look something likethe example shown in 5. You may have to adjust the start stop range for the sweep andthe extrapolation point to get a satisfactory curve. Include this plot with your report, andinclude the IIP3 point in your performance summary table.

8.3 Voltage Controlled Oscillator

Include waveform plots in your report as specified in each of the following simulations, and alsoinclude a table which summarizes your designs performance in each of the following areas. It isrecommended that you create seperate cell views for each of the simulations described below. Itmay also be easiest to create a symbol for your VCO that can be instantiated in each of yoursimulation schematics so that changes made to the VCO are reflected in all of the schematics.

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Figure 5: Example plot for mixer IIP3.


No simulation is required for this metric, just add up the areas for all for all of the componentsin your VCO schematic. Be sure to include blocking capacitors and biasing circuitry.


1. Open your VCO schematic and set your control voltage to 0 V.



4. Record the total power consumption as the power supply voltage (1.2 V) multiplied by thecurrent drawn from the power supply (13.94 mA in Fig. 1). No waveforms need to bereported for this simulation.

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8.3.3 Tuning Range

1. Open your VCO schematic and drive the control voltage for your VCO with a dc voltagesource (vdc). Set the dc voltage of the source to a variable name such as vtune.

2. Open the Analog Design Environment and copy variables from the cellview. The designvariable vtune will now appear under Design Variables, give it a value of 0 V.

3. Open the Choosing Analyses form and select a pss analysis. Enter 1.8G for Beat Frequency.

4. Enter 10 for Number of harmonics and select moderate for Accuracy Defaults.

5. Select the Oscillator option, and select the oscillator and reference nodes on your schematic.If you have single-ended output the reference node will be gnd!, and if you have a differentialoutput it will be the negative output node.

6. Click Apply and then select a pnoise simulation.

7. Change Sweeptype to relative and set Relative Harmonic to 1.

8. Set the Start and Stop of the Frequency Sweep Range to 1K and 100M.

9. Set Sweep Type to Logarithmic, and set Number of Steps to 201.

10. Under Sidebands set Maximum Sideband to 7.

11. Under Output select voltage and select the appropriate nodes on your schematic.

12. Select none for Input Source and click OK.

13. In the Analog Design Environment, select Simulation->Convergence Aids->Initial Condition,and set initial conditions for your tank nodes to enable oscillator start-up (e.g., if you havea differential design, set one node to 1.2 V and the other to 1.0 V).

14. Run the simulation.

15. Select Results->Direct Plot->Main Form and then select pss under Analysis.

16. Select Harmonic Frequency, and record the value of the first harmonic.

17. Re-run the simulation with the vtune variable set to 1.2, and record the value of the firstharmonic.

18. Enter these minimum and maximum frequencies for your VCO in your performance summarytable, as well as the tuning range which is calculated as fmax

fmin. No plots are required to be

turned in for this simulation.

8.3.4 Output Swing

1. Follow steps 1-13 of the Tuning Range simulation, and set the variable vtune so that theoutput frequency (first harmonic in the pss simulation) is approximately 1.8 GHz.

2. Run the simulation.

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3. Select Results->Direct Plot->Main Form and then select pss under Analysis.

4. Select Voltage under Function, and select time under Sweep.

5. Select Differential Nets for Select if you have differential outputs, and chose the appro-priate nets on the output to plot one period of your oscillator output.

6. Turn in this plot with your report, recording the output voltage swing in your performancesummary table.

8.3.5 Phase Noise

1. Follow steps 1-13 of the Tuning Range simulation, and adjust the variable vtune until theoutput frequency (first harmonic in the pss simulation) is approximately 1.8 GHz.

2. Select Results->Direct Plot->Main Form and then select pnoise under Analysis.

3. Select Phase Noise under Function and plot the phase noise for your VCO.

4. Place markers showing the value of the phase noise at 100K and 5M offsets. Turn in thisplot with your report, and quote the phase noise at the specified offsets in your performancesummary table.

8.4 Complete System

This section involves putting all of your components together, and having them function as acomplete system. Your individual components may require some tweaking to work together, sincethe loading they experience in the complete system may differ from what was assumed in thecharacterizations for each component in isolation.

The first simulation is a transient simulation to demonstrate the functionality of your system,and the other simulations determine your systems performance in each of the areas specified at theoutset of the project. Include waveform plots in your report as specified in each of the followingsimulations, and also include a table which summarizes your system performance in each of thefollowing areas.

8.4.1 Basic Functionality

1. Create symbol views for each of your components by adding pins to the schematic and thenselecting Design->Create Cellview->From Cellview in the schematic editing window.

2. Create a schematic for your complete system by instantiating each of the symbols you havejust created, as shown in Fig. 6.

3. Drive the input of your LNA with a port with Source type set to sine, a frequency of 2GHz, and Amplitude 1 (dBm) set to -20. Select Display modulation params and set AMmodulation index 1 to 0.5 and AM modulation freq 1 to 5M.

4. Set the control voltage of your VCO to whatever value gives you an output frequency of1.8 GHz (this may be different from the standalone simulations now that you are loading itwith the mixer).

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Figure 6: Schematic for system simulation.

5. As shown in Fig. 6, have the output of the mixer drive a vcvs with a gain of 1, which thendrives an LC filter. Use ideal components with R = 1.25 Ω, L = 10 nH, and C = 63.3 pF.These values are chosen to yield a bandpass filter centered around 200 MHz with a Q of 10.

6. Open Analog Design Environment, and enable a transient simulation with a length of 500n.

7. Run the simulation, and plot the waveforms at the input of the LNA and the output of thefilter.

8. In the plot display window, select Axis->Strips so that your plot resemble the exampleshown in Fig. 7. Turn in this plot with your report.

8.4.2 Layout Area

No simulation is required for this metric, just add up the areas for all for all of the components inyour system. Assuming that nothing has changed from your previous reports, you can just addthe previously reported areas for your LNA and mixer to the VCO. You do not need to includethe filter in this total, it is just for evaluation purposes.


1. Using the same schematic as in Section 8.4.1, open the Analog Design Environment andenable a dc simulation, with Save DC Operating Point selected.


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Figure 7: Waveforms for system transient simulation.

3. Record the total power consumption as the power supply voltage (1.2 V) multiplied by thecurrent drawn from the power supply (13.94 mA in Fig. 1). No waveforms need to bereported for this simulation.

8.4.4 Gain

1. Use the same schematic as in Section 8.4.1, except change the Source type on the drivingport to dc.

2. Open Analog Design Environment and enable a pss simulation.

3. Make sure Auto Calculate is NOT selected, and enter 1.8G for the Beat Frequency.

4. Under Output harmonics set Number of harmonics to 0, and set Accuracy Defaults tomoderate. Set Additional Time for Stabilization to the length of time that it takesyour VCO output to stabilize (50n is a safe choice).

5. Select the Oscillator option, and select the appropriate nodes in your schematic.

6. Click apply and then select a pxf analysis.

7. Set the Frequency Sweep Range to start at 1M and stop at 400M. Set Sweep Type to Linearand set Number of Steps to 50.

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8. Under Sidebands set Maximum sideband to 3.

9. Select voltage under Output, and select the output nodes of your mixer (NOT the outputof the LC filter) as the output nodes.

10. Click OK, and in Analog Design Environment select Simulation->Convergence Aids->InitialCondition and give initial conditions to your VCO tank so that it will begin to oscillate.

11. Run the simulation, and select Results->Direct Plot->Main Form and then select pxfunder Analysis.

12. Select Voltage Gain under Function, select sideband under Sweep, and select dB20 underModifier.

13. Under Output Harmonic select 0 (this range should contain the frequencies around 2 GHz),and select the input port in the schematic to plot the results.

14. Place markers at 1.95 GHz and 2.05 GHz, and turn this plot in with your report. Quote theminimum of these two gain values in your performance summary table.

8.4.5 Noise Figure

1. Use the same schematic as in Section 8.4.1, except change the Source type on the drivingport to dc.

2. Open Analog Design Environment and enable a pss simulation.

3. Make sure Auto Calculate is NOT selected, and enter 1.8G for the Beat Frequency.

4. Under Output harmonics set Number of harmonics to 0, and set Accuracy Defaults tomoderate. Set Additional Time for Stabilization to the length of time that it takesyour VCO output to stabilize (50n is a safe choice).

5. Select the Oscillator option, and select the appropriate nodes in your schematic.

6. Click apply and then select a pnoise analysis.

7. Set Start-Stop of the Frequency Sweep Range to go from 1K to 4G, and set Sweep Typeto Logarithmic with Points Per Decade set to 10.


9. For Output, select voltage and select the mixer outputs (NOT the LC filter output) onyour schematic.

10. For Input Source select port and select the input port.

11. For Reference side-band select Enter in field and enter -1.

12. Click OK, and in Analog Design Environment select Simulation->Convergence Aids->InitialCondition and give initial conditions to your VCO tank so that it will begin to oscillate.

13. Run the simulation, and then select Results->Direct Plot->Main Form and then selectpnoise under Analysis.

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14. Select Noise Figure and click on Plot to plot the waveform.

15. Double-click on the x-axis and set it to display in log format.

16. Place a marker at 200 MHz and include this plot with your report. Quote the noise figureat 200 MHz in your performance summary table.

8.4.6 Linearity

1. Starting with the same schematic as in Section 8.4.1, run a transient simulation and recordthe amplitude of the LO being driven into the mixer.

2. Replace the LO block with a vsin source, at a frequency of 1.8 GHz and with the amplitudeyou recorded in the previous step. If you had differential LO, use a vcvs with a gain of -1to create the other input, as shown in Fig. 8.

3. Replace the vcvs/LC filter combination at the mixer output with a port with the Sourcetype set to dc (and a transformer if necessary), as shown in Fig. 8.

4. Configure the input port with a Source type of sine, a frequency name, and a frequencyof 2 GHz. Set Amplitude 1 (dBm) to the variable name prf, and click on Display smallsignal params and enter prf in the PAC Magnitude (dBm) field that appears.

5. Open the Analog Design Environment and click on Variables->Copy From Cellview. Theprf variable should now show up in the Design Variables window. Double click on it andgive it some arbitrary value (it will be swept in the simulation so the value doesn’t make adifference) such as 0.

6. Now select Analyses->Choose.



9. Select Sweep, make sure that Variable is selected, and enter prf for Variable Name.

10. Under Sweep Range, select Start-Stop and set it to start at -25 and stop at 5. Under SweepType, select Linear, Step Size and set it to 5.

11. Click Apply, then select a pac analysis.

12. Under Frequency Sweep Range (Hz) enter 2.002G for Freq.

13. Under Sidebands select Array of Indices and enter -9 -11 for Additional indices (besure to include the space between the two numbers).


15. Select Results->Direct Plot->Main Form and then select pac under Analysis.

16. Select IPN Curves under Function, select Variable Sweep for Circuit Input Power, andset Input Power Extrapolation Point (dBm) to -20.

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Figure 8: Schematic for system IIP3 simulation.

17. Select Input Referred IP3, then select 3rd for Order, and select -11 198M under 3rdOrder Harmonic and -9 202M under 1st Order Harmonic.

18. Click on the output port to display the IIP3 plot. You may have to adjust the start stoprange for the sweep and the extrapolation point to get a satisfactory curve. Include this plotwith your report, and include the IIP3 point in your performance summary table.

9 Helpful Hints

9.1 Transistor Parameters

For the initial design procedure, it is useful to know the relevant transistor characteristics (gm, Cgs,etc). The best way to find these is to bias the transistor with the proper current and node voltages,run a dc simulation (as described in the LNA power consumption simulation), and then selectResults->Print->DC Operating Points and click on the transistor. Don’t worry about some ofthe small signal capacitances being negative, that is just a result of the way they are calculated,use the absolute value.

9.2 Parametric Simulations

For optimizing different variables, it can be useful to run parametric simulations. To do this,replace the quantity you would like to optimize with a variable name (e.g., fill in Lg for theinductance of one of your inductors), then in Analog Design Environment select Variables->CopyFrom Cellview. Now select Tools->Parametric Analysis, and in the resulting form fill in thevariable name and the range over which you would like to sweep it. You can then plot all of theusual quantities over this range for whatever simulations that you have enabled.

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9.3 Noise Optimization

For optimizing noise performance, it can be useful to know which noise sources are dominatingthe noise at the output. To determine this, run a pnoise simulation, and you can then print outthe percentage noise contributions of the different noise sources in the circuit. For details on howto run pnoise simulations, see the relevant section in the SpectreRF user guide, which can beaccessed by opening Help->Cadence Documentation and browsing to Spectre RF->SpectreRFSimulation Option User Guide->Simulating Low-Noise Amplifiers.

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