1 model of the package : r,l,c transmission line core model of the die : internal activity (core)...
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Model of the package :• R,L,C• Transmission line
Core
Model of the die :• internal activity (core)• on-chip decoupling• supply network • I/O structure Core
Package
IC
The model of an IC can be derived from its physical architecture. It includes the core and package model.
EMC of IC models
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100 mA
3 A
32 bit processor500 MHz
62.5 ns 2 ns
16 bit processor
16 MHz
I
time
Model core activity : extract noise source
time
IExtraction of internal current waveform
1st order assumption : model core activity by triangular waveform current source
IC model
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Physical Transistor level (Spice)
Huge simulation
Limited to analog blocks
Interpolated Transistor level
Difficult adaptation to usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Gate level Activity (Verilog)
time (ns)0
20040060080010001200
0 20 40 60 80 100 120 140
Activity
Activity estimation from data sheet
Very simple, not limited
Immediate, not accurate
Model core activity: noise source
Equivalent Current
generatorExtraction
IC model
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IC model
PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling capacitors, shows a more stable on-chip power supply © Sigrity http://www.sigrity.com
Model core activity: Tool example - PowerSI
Layout Silicium voltage drop map
Accurate but high level of complexity
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Package model
[Component] Fx45H725 [Manufacturer] Finex[Package]| variable typ min max|R_pkg 800m 500m 950m L_pkg 6nH 5.5nH 7.5nHC_pkg 8pF 4pF 10.5pF[Pin] signal model R_pin L_pin C_pin1 /1OE in1 921m 7.25nH 10.1pF2 1Y1 out 1 916m 7.17nH 9.94pF…
[Component] Fx45H725 [Manufacturer] Finex[Package]| variable typ min max|R_pkg 800m 500m 950m L_pkg 6nH 5.5nH 7.5nHC_pkg 8pF 4pF 10.5pF[Pin] signal model R_pin L_pin C_pin1 /1OE in1 921m 7.25nH 10.1pF2 1Y1 out 1 916m 7.17nH 9.94pF…
Input Buffer I/O specification(IBIS) – R,L,C for each pin
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EMC model exampleConducted/Radiated emission prediction
ICEM model
dBµV
MHz
Emission spectrummeasurement
simulation
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EMC model exampleNear-field emission prediction
Simulation of H field at
32 MHz
Measurement of H field
at 32 MHz
Scan area
Package model with 13 leads
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High frequency measurementHigh frequency modelling2D, 3D modellingElectrical modellingIC designIC floorplan
High frequency measurementHigh frequency modelling2D, 3D modellingElectrical modellingIC designIC floorplan
EMC for Integrated Circuits requires various expertise
Design issues
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6. EMC guidelines
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Basic concepts to reduce emission and susceptibility
Remember the influent parameters on emission and susceptibility
Control IC internal activity
Minimize circuit output load
Control effect of IC interconnections (decoupling)
Control effect of PCB interconnections (decoupling)
Emission: Susceptibility:Control effect of PCB interconnections (decoupling)
Control effect of IC interconnections (decoupling)
Control Impedance of IC nodes
Reduce non linear effects of active devices
Improve block own susceptibility
Techniques used to reduce emission and/or susceptibility issues are based on these principles
Techniques used to reduce emission and/or susceptibility issues are based on these principles
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Golden Rules for Low Emission
Lead: L=0.6nH/mm
Bonding: L=1nH/mm
• Inductance is a major source of resonance• Each conductor acts as an inductance• Ground plane modifies inductance value (worst case is far from ground)
A) Use shortest interconnection to reduce the serial inductance
Rule 1: Power supply routing strategy
Reducing inductance decreases voltage bounce !!
Reducing inductance decreases voltage bounce !!
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
PCB
Long leads
Die of the IC
Close from ground
bonding
Die of the ICShort leads
ballsFlip chip package:
L up to 3nH
Far from ground
Requirements for high speed microprocessors : L < 50 pH !Requirements for high speed microprocessors : L < 50 pH !
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
Correct
Fail
9 I/O ports
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
Current density simulation
C) Place supply pairs close to noisy blocks
Layout view
Digital core
Memory PLL
VDD / VSS
VDD / VSS
VDD / VSS
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
•to increase decoupling capacitance that reduces fluctuations•to reduce current loops that provoke magnetic field
D) Place VSS and VDD pins as close as possible
Current loop
EM field
Added contributions
currentsDie
LeadLead
current
EM wave
current
EM wave
Reduced contributions
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
Case 1 : Infineon Tricore Case 2 : virtex II
Case study 1:
Worst casenot enough supply pairs, bad distribution & dissymmetry
Not idealNot enough supply for IOs : (core emission is lower than IO one)
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
Case study 2:
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
• More Supply pairs for IOs
• Better distribution
• More Supply pairs for IOs
• Better distribution
2 FPGA , same power supply, same IO drive, same characteristicsSupply strategy very different !
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Golden Rules for Low EmissionRule 1: Power supply routing strategy
Case study 2:
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 2: higher emission
level (5 times higher)
Case 2: higher emission
level (5 times higher)
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Golden Rules for Low EmissionRule 2: Add decoupling capacitor
Parasitic emission (dBµV)
-1001020304050607080
1 10 100 1000Frequency (MHz)
Customer’s specification
No decoupling
No decoupling
Keep the current flow internal Local energy tank Reduce power supply voltage
drops
10 – 15 dBVolt
time
Internal voltage drop
10-100 nF decoupling
10-100 nF decoupling
time Efficient on one decadeEfficient on one decade
The most popular and efficient solution !!!
The most popular and efficient solution !!!
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Voltage regulator
Power supply
Ground
On chip interconnections
Vdd
Vss
PCB planesElectrolytic
bulk capacitor
1 µF – 10 mF
HF ceramic capacitor
100 nF – 1 nF
DC – 1 KHz 1 KHz – 1 MHz 1 MHz – 100 MHz > 100 MHz
Z Vdd - Vss
Frequency
Target impedance Zt (0.25 mΩ)Power distribution network design :
Freq range current
rippleVZ ddt
max
Ferrite bead
Golden Rules for Low EmissionRule 2: Add decoupling capacitor on power distribution network
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Golden Rules for Low EmissionRule 2: Add decoupling on-chip capacitor
On chip decoupling capacitance versus technology and complexity
Devices on chip
Intrinsic on-chip supply
capacitance
100K 1M 10M
10pF
100pF
1.0nF
10nF
100M 1G
100nF
0.35µm
0.18µm90nm
65nm
Very high efficient decoupling above 100 MHz (where PCB decoupling capacitors become inefficient) …
… But space consuming Fill white space with decap cells Use MOS capa. or Metal-
Insulator-Metal (MIM) capa.
Capa cell for local decoupling
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Golden Rules for Low EmissionRule 3: Reduce core noise
Reduce operating supply voltage Reduce operating frequency Reduce peak current by optimizing IC activity, using distributed
clock buffers, turning off unused circuitry, avoiding large loads, creating several operation mode
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Golden Rules for Low EmissionRule 3: Reduce core noise
Clock in
T Pseudorandom noise
f
P
+/-Δf
+/-Δf
Clock out
T+/-Δt
Spread spectrum frequency modulation
1/T
specification
f
•Add a controlled jitter on clock signal to spread the noise spectrum
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Golden Rules for Low EmissionRule 3: Reduce core noise
datarequest
acknowledgment
Asynchronous block
data
clock
Synchronous block
1/T
specification
f
• Asynchronous design spreads noise on all spectrum (10 dBµV reduction)
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Golden Rules for Low EmissionRule 4: Reduce I/O noise
•Minimize the number of simultaneous switching lines (bus coding)•Reduce di/dt of I/O by controlling slew rate and drive
f
SR
Emission level
Tr1 Tr2
1/Tr11/Tr2
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Golden Rules for Low Susceptibility
Work done at Eseo France (Ali ALAELDINE)
Immunity level (dBm)
Frequency
No rules to reduce susceptibility
Substrate isolation
Decoupling capacitanc
e
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
combined with resistive supply path
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
combined with resistive supply path
Rule 1: Add decoupling capacitance
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Golden Rules for Low SusceptibilityRule 2: Isolate Noisy blocks
Analog
Standardcells
Noisy blocks
Far fromnoisy blocks
Bulk isolation
Separate supply
Why ? • To reduce the propagation of
switching noise inside the chip• To reduce the disturbance of
sensitive blocks by noisy blocks (auto-susceptibility)
How ?• by separate voltage supply• by substrate isolation• by increasing separation between
sensitive blocks• By reducing crosstalk and
parasitic coupling at package level
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Golden Rules for Low SusceptibilityRule 3: Reduce desynchronisation issues
Work done at INSA Toulouse/TIMA Grenoble (Fraiddy BOUESSE)
• Synchronous design are sensitive to propagation delay variations due to jitter (dynamic errors)
• Improve delay margin to reduce desynchronization failures in synchronous design
• Asynchronous logic design is less sensitive to delay compared to synchronous design
15 dB
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Golden Rules for Low SusceptibilityRule 4: Improve noise immunity of IOs
• Add Schmitt trigger on digital input buffer
• Use differential structures for digital IO to reject common mode noise (as Low Voltage Differential Signaling I/Os)
Schmitt trigger2 dB
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Case studyStarChip #1 Your definitive solution for embedded electronics,16 bit MPU with 16 MHz external quartz,
SIGNAL Description
VDD Positive supply
VSS Logic Ground
VDD_OSC Oscillator supply
VSS_OSC Oscillator ground
PA[0..7] Data port A (programmable drive)
PB[0..7] Data port B (programmable drive)
PC[0..7] Data port C (programmable drive) external 66MHz data/address
ADC In [0..3] 4 analog inputs (12 bit resolution)
CAN Tx CAN interface (high power, 1MHz)
CAN Rx CAN interface (high power, 1MHz)
XTL_1, XTL_2 Quartz oscillator 16MHz
CAPA PLL external capacitance
RESET Reset microcontroller
EmissionSusceptible
• on-chip PLL providing internal 133MHz operating clock.
• 128Kb RAM, 3 general purpose ports (A,B,C, 8bits)
• 4 analog inputs 12 bits, CAN interface
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VSS
PortA PortB
OSC
VDD
VDD_Osc
VSS_Osc
PortC
ADC [0..3] CAN
Reset
NC
Capa
NC
NC
NC
Case studyStarChip #1 Initial floorplan
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Case studyStarChip #1 Your floorplan
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7. Conclusion / Future of EMC
350.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 90 nm 65 nm 45 nm
0
50
100
150
200
250
300
To
tal
Pea
k C
urr
ent
(A)
Technology32 nm 25 nm
350
400
Future of EMCScaling leads to an increase of transient currents
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Future of EMC
0
20
40
60
80
100
10MHz 100MHz 1GHz
Emission dBµV
10GHz
16 bits
32 bits
System on chip
New frequency band
(1-10GHz)
Frequency
Critical frequency bands
Towards complex systems, system on chip, system on package
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1995 2000 2005 2010 2015
0.1V
1V
10VSupply voltage
Year
0.25m
0.18m 0.13m
90nm
65nm
45nm 32nm
External voltage
Internal voltageNoise margin or
static margin
18 nm22 nm
Less noise margin
Future of EMC
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Barber, Herke, IEE Electromagnetic Hazard, 1994
Immunity increases with Freq
Immunity increases with Freq
Immunity suddenly decreases?
Immunity suddenly decreases?
Susceptibility trends vs frequency
Future of EMC
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Future of EMCMost of EMC measurement methods are limited to 1 GHz
How characterizing accurately emission and susceptibility of ICs up to 10 GHz?
IEC 61967-2
(TEM : 1GHz)
IEC 61967-3/6
(Near field scan, 5GHz)IEC 61967-4
(1/150 ohm, 1 GHz)
IEC 62132-2
(BCI, 1 GHz)
IEC 61967-5
(WBFC, 1 GHz)
IEC 61967-7
(Mode Stirred Chamber: 18 GHz)
IEC 61967-2
(GTEM 18 GHz)IEC 62132-3
(DPI, 1 GHz)
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Models become more and more complex
Chip stacking Flip-chip
Substrate
Passive devices
Vdd
Vssresonance
Crosstalk via
Radiation
System-In-Package
Circuits more complex (System-on-chip, System-in-package)
Power distribution networks become larger, more and more IOs
More and more parasitic coupling paths (substrate coupling, package coupling)
Modeling at high frequency ? How ensure accuracy and efficiency ?
Future of EMC
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Future of EMCDeveloping new design guidelines
Customers requirements are more and more constraining
Off-chip decoupling capacitor are limited to several hundred MHz
New technologies require less and less power distribution network impedance
Need of efficient techniques to reduce emission and improve immunity
Electromagnetic bandgap
Active noise cancellation
High density MOS capacitance
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With technology scale down, ICs become more sensitive and
emissive.
EMC of ICs has become a major concerns for ICs suppliers
Standardization groups are working on EMC characterization
method (need to address high frequency)
Needs for simulation models and tools to predict ICs EMC
performances before fabrication
New EMC oriented design rules and techniques have to be
developed to ensure future ICs EMC compliance
Conclusion