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L32:Low Power System On Chip

Jun-Dong ChoSungKyunKwan Univ.

Dept. of ECE, Vada Lab. http://vada.skku.ac.kr

Introduction to SOC

• SOC will bridge the gap b/w s/w and their implementation

in novel, energy-efficient silicon architecture.

•In SOC design, chips are assembled at IP block level (design reusable) and IP interfaces rather than gate level

•SOC specs are coming from ICT system engineers rather

than RTL descriptions.

Common Fabric for IP Blocks

• Soft IP blocks are portable, but not as predictable as hard IP.

• Hard IP blocks are very predictable since a specific physical implementation can be characterized, but are hard to port since are often tied to a specific process.

• Common fabric is required for both portability and predictability.

• Wide availability: Cell Based Array, metal programmable architecture that provides the performance of a standard cell and is optimized for synthesis.

Four main applications

• Set-top box: Mobile multimedia system, base station for the home local-area network.

• Digital PCTV: concurrent use of TV,3D graphics, and Internet services

• Set-top box LAN service: Wireless home-networks, multi-user wireless LAN

• Navigation system: steer and control traffic and/or goods-transportation

Types of System-on-a-Chip Designs

Silicon in 2010

Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 m

Density Access Time(Gbits/cm2) (ns)

DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5

Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)

Custom 25 54 3Std. Cell 10 27 1.5

Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7

FPGA 0.4 4.5 0.25

Why Lower Power

• Portable systems– long battery life– light weight– small form factor

• IC priority list– power dissipation– cost– performance

• Technology direction Reduced voltage/power

designs based on mature high performance IC technology, high integration to minimize size, cost, power, and speed

year

Power(W)

1980 1985 1990 1995 2000

10

20

30

40

50

5

15

25

35

45

i286i386 DX 16 i486 DX25

i486 DX 50

i486 DX2 66 P-PC601 50

P6 166

P5 66

Alpha21064 200

Alpha 21164

i486 DX4 100

P II 300

P-PC604 133

P-PC750 400

P III 500

Alpha 21264

Microprocessor Power Dissipation

Levels for Low Power DesignSystem

Algorithm

Architecture

Circuit/Logic

Technology

Hardware-software partitioning,

Complexity, Concurrency, Locality,

Parallelism, Pipelining, Signal correlations

Sizing, Logic Style, Logic Design

Threshold Reduction, Scaling, Advanced packaging

Possible Power Savings at Different Design LevelsLevel of

Abstraction Expected Saving

Algorithm

Architecture

Logic Level

Layout Level

Device Level

10 - 100 times

10 - 90%

20 - 40%

10 - 30%

10 - 30%

Regularity, Data representation

Instruction set selection, Data rep.

SOI

Power down

Power-hungry Applications

• Signal Compression: HDTV Standard, ADPCM, Vector Quantization, H.263, 2-D motion estimation, MPEG-2 storage management

• Digital Communications: Shaping Filters, Equalizers, Viterbi decoders, Reed-Solomon decoders

New Computing Platforms

• SOC power efficiency more than 10GOPs/w– Higher On Chip System Integration: COTS: 100W, SOAC:10W

(inter-chip capacitive loads, I/O buffers)– Speed & Performance: shorter interconnection,fewer drivers,fast

er devices,more efficient processing artchitectures

• Mixed signal systems• Reuse of IP blocks • Multiprocessor, configurable computing• Domain-specific, combined memory-logic

2P kCFV

Physical gap

• Timing closure problem: layout-driven logic and RT-level synthesis

• Energy efficiency requires locality of computation and storage: match for stream-based data processing of speech,images, and multimedia-system packets.

• Next generation SOC designers must bridge the architectural gap b/w system specification and energy-efficient IP-based architectures, while CAE vendors and IP providers will bridge the physical gap.

Low Power Design Flow IFunction

Partitioning andHW/SW Allocation

SystemLevel

Specification

System-LevelPower Analysis

BehavioralDescription

SoftwareFunctions

ProcessorSelection

Power-drivenBehavioralTransformation

Behavioral-LevelPower Analysis

Power ConsciousBehavioralDescription

Power AnalysisRT-LevelHigh-Level

Synthesis andOptimization

SoftwareOptimization

Software-Level

Power Analysis

To RT-Level Design

Low Power Design Flow II

RT-levelDescription

RTLmapping

Logic SynthesisandOptimization

Gate-LevelPower Analysis

Gate-level

Description

Power AnalysisSwitch-LevelHigh-Level

Synthesis andOptimization

RTLLibrary

Data-path Controller

Switch-level

Description

Standard cellLibraryProcessor

Control andSteering Logic

Memory

RTLMacrocells

Three Factors affecting Energy– Reducing waste by Hardware Simplification: redundant

h/w extraction, Locality of reference,Demand-driven / Data-driven computation,Application-specific processing,Preservation of data correlations, Distributed processing

– All in one Approach(SOC): I/O pin and buffer reduction– Voltage Reducible Hardwares

– 2-D pipelining (systolic arrays)– SIMD:Parallel Processing:useful for data w/ parallel

structure– VLIW: Approach- flexible

Example 1: Filter: Eliminating Redundant Computations

Example2: IBM’s PowerPC Lower Power Architecture

• Optimum Supply Voltage through Hardware Parallel, Pipelining ,Parallel instruction execution– 603e executes five instruction in parallel (IU, FPU, BPU, LSU, SRU) – FPU is pipelined so a multiply-add instruction can be issued every clock cycle – Low power 3.3-volt design

• Use small complex instruction with smaller instruction length – IBM’s PowerPC 603e is RISC

• Superscalar: CPI < 1– 603e issues as many as three instructions per cycle

• Low Power Management– 603e provides four software controllable power-saving modes.

• Copper Processor with SOI

• IBM’s Blue Logic ASIC :New design reduces of power by a factor of 10 times

Power-Down Techniques

◆ Lowering the voltage along with the clock actually alters the energy-per-operation of the microprocessor, reducing the energy required to perform a fixed amount of work

Voltage vs Delay

•Use Variable Voltage Scaling or Scheduling for Real-time Processing •Use architecture optimization to compensate for slower operation, e.g., Parallel Processing and Pipelining for concurrent increasing and critical path reducing.

Low Voltage Main Memories

Why Copper Processor?

• Motivation: Aluminum resists the flow of electricity as wires are made thinner and narrower.

• Performance: 40% speed-up

• Cost: 30% less expensive

• Power: Less power from batteries

• Chip Size: 60% smaller than Aluminum chip

Silicon-on-Insulator• How Does SOI Reduce Capacitance ?

Eliminated junction capacitance by using SOI (similar to glass) is placed between the impuritis and the silicon substrate high performance, low power, low soft error

SOC Co-Design Challenges

• Current systems are complex and heterogenous Contain many different types of components

• Half of the chip can be filled with 200 low-power, RISC-like processors (ASIP) interconnected by field-programmable buses, embedded in 20Mbytes of distributed DRAM and flash memory, Another Half: ASIC

• Computational power will not result from multi-GHz clocking but from parallelism, with below 200 MHz. This will greatly simplify the design for correct timing, testability, and signal integrity.

Configurability

• One-M gate reconfigurable, one-M gate hardwired logic.

• 50GIPS for programmable components or 500 GIPS for dedicated hardwares

• Reduce design risks for which NRE costs will become dominant

• 1 V with the watt range

Bridging the architectural gap

• Product reliability: design at a level far above the RT level, with reuse factors in excess of 100

• Trade-off: 100MOPs/watt (microprocessor) 100GOPs/watt (hardwired) Reconf. Computing with a large number of computing nodes and a very restricted instruction set (Pleiades)

Implementing Digital Systems

SOC CAD Companies

• Avant! www.avanticorp.com• Cadence www.cadence.com• Duet Tech www.duettech.com• Escalade www.escalade.com• Logic visions www.logicvisio

n.com• Mentor Graphics www.mentor.

com• Palmchip www.palmchip.com• Sonic www.sonicsinc.com• Summit Design www.summit-

design.com

• Synopsys www.synopsys.com

• Topdown design solutions www.topdown.com

• Xynetix Design Systems www.xynetix.com

• Zuken-Redac www.redac.co.uk