1 introduction to vlsi physical design
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1
Day 1Introduction to VLSI Physical Design
Session SpeakerAjaya Kumar.s
2©M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
Session Objectives
To understand the Physical design flow
To understand the need for Physical design
To know about the tools used for physical design
To understand the concepts of CMOS process parameters
To know the issues of scaling and its effects
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Session Topics
• Technology Evolution
• Scaling Issues
• Design Principles
• Verification and Simulation
• Detailed Physical Design Flow
• Foundry Files, Parameters, Rules and Guidelines
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PEMP VSD531Technology Evolution: Cost and Integration Drivers
Moore’s Law is about costIncreased integration, decreased cost more possibilities for semiconductor-based productsPentium 4 die shot:
2.2cm
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Sense of Scale (Scaling)
What fits on a VLSI Chip today?State of the art logic chip
20mm on a side (400mm2)0.13mm drawn gate length0.5μm wire pitch8-level metal
For comparison32b RISC processor
8K l x 16KlSRAM
about 32l x 32l per bit8K x 16K is 128Kb, 16KB
DRAM8l x 16l per bit8K x16K is 1Mb, 128KB 20mm
(40,000 wire pitches)320,000 l
0.13mm (2 l)
32b RISCProcessor
64b FPProcessor
0.5mm(8 l)
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MOS Transistor Scaling (1974 to present)
S=0.7 [0.5x per 2 nodes]
(TypicalMPU/ASIC)
Poly Pitc
h
(TypicalDRAM)
Metal
Pitch
Decreased transistor/feature sizes
Increased variability (tox, BEOL, DFM, SEU, etc.)
Short channel effect, leakage power
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SEMATECH Prototype BEOL stack, 2000
Wire
ViaGlobal (up to 5)
Intermediate (up to 4)
Local (2)
PassivationDielectric
Etch Stop Layer
Dielectric Capping Layer
Copper Conductor with Barrier/Nucleation Layer
Pre Metal DielectricTungsten Contact Plug
Reverse-scaled global interconnects
Growing interconnect complexity
Performance critical global interconnects
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Intel 130nm BEOL Stack
Intel 6LM 130nm process with vias shown (connecting layers)
Aspect ratio = thickness / minimum width
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Interconnect Capacitance: Parallel Plate Model
SiO2
Substrate
L
W
T
HILD
ILD = interlevel dielectric
Bottom plate of cap can be another metal layer
Cint = eox * (W*L / tox)
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Line Dimensions and Fringing Capacitance
w S
Capacitive coupling
Crosstalk effect
Signal integrity
Lateral cap
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Interconnect Evolution and Modeling Needs
Before 1990, wires were thick and wide while devices were big and slowLarge wiring capacitances and device resistancesWiring resistance << device resistanceModel wires as capacitances only
In the 1990s, scaling (by scale factor S) led to smaller and faster devices and smaller, more resistive wires
Reverse scaling of properties of wiresRC models became necessary
In the 2000s, frequencies are high enough that inductance has become a major component of total impedance
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Evolving Interconnects Affect Timing
Interconnect capacitance > gate input capacitanceBetter prediction
Interconnect resistance no longer ignorable Better modeling: distributed R(L)C network, AWE, etc.Effective capacitance < total load capacitance
Interconnect delay > gate delay for sub-micron technologies
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Sub-Wavelength Optical Lithography
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…Complexity of Photomasks
How many wafers, on average, are printed with a mask set?
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Summary of Technology Scaling
Scaling of 0.7x every three (two?) years.25u .18u .13u .10u .07u .05u1997 1999 2002 2005 2008 20115LM 6LM 7LM 7LM 8LM 9LM
Interconnect delay dominates system performanceconsumes up to 70% of clock cycle
Cross coupling capacitance is dominatingcross capacitance 100%, ground capacitance 0%ground capacitance is 90% in .18uhuge signal integrity implications (e.g., guardbands in static analysis approaches)
Multiple clock cycles required to cross chipwhether 3 or 15 not as important as fact of “multiple” > 1
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New Materials Implications
Lower dielectric permittivityreduces total capacitancedoesn’t change cross-coupled / grounded capacitance proportions
Copper metallizationreduces RC delayavoids electromigration (factor of 4-5 ?)thinner deposition reduces cross cap
Multiple layers of routingenabled by planarization; 10% extra cost per layerreverse-scaled top-level interconnectsrelative routing pitch may increaseroom for shielding
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Technical Issues
Manufacturability (chip can't be built)antenna rulesminimum area rules for stacked viasCMP (chemical mechanical polishing) area fill ruleslayout corrections for optical proximity effects in subwavelengthlithography; associated verification issues
Signal integrity (failure to meet timing targets)crosstalk induced errorstiming dependence on crosstalkIR drop on power supplies
Reliability (design failures in the field)electromigration on power supplieshot electron effects on deviceswire self heat effects on clocks and signals
Noise
Analog design concerns are due to physical noise sources
because of discreteness of electronic charge and stochastic nature of electronic transport processesexample: thermal noise, flicker noise, shot noise
Digital circuits due to large, abrupt voltage swings, create deterministic noise which is several orders of magnitude higher than stochastic physical noise
still digital circuits are prevalent because they are inherently immune to noise
Technology scaling and performance demands make noisiness of digital circuits a big problem
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Silicon Complexity ChallengesSilicon Complexity Challenges
Silicon Complexity = impact of process scaling, new materials, new device/interconnect architecturesNon-ideal scaling (leakage, power management, circuit/device innovation, current delivery)Coupled high-frequency devices and interconnects (signal integrity analysis and management)Manufacturing variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reusability, static performance verification methodology/tools)Scaling of global interconnect performance (communication, synchronization)Decreased reliability (soft error uncertainty, gate insulator tunneling and breakdown, joule heating and electromigration)Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, manufacturing NRE cost)
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In a PDA…
Reference Design: personal digital assistant (PDA)
Composed of CPU, DSP, peripheral I/O, and memory
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…Implemented With an SoC
0.18um / 400MHz / 470mW (typical)
CPU
I-cache32KB
D-cache32KB
I2C
FICP
USB
MMC
UART AC97
I2S
OST
GPIO
SSP
PWM RTC
DMA controller
LCDCnt.
MEMCnt.
PWR CPG
SDRAM64MB
Flash32MB
LCDPeripheral Area
4 – 48MHz
Data TransferArea
100MHz
Processor Area
Max 400MHz
MM ApplicationMP3JPEGSimple Moving Picture
6.5MTrs.
Available Time6-10Hr
SpecificationUSB
MMC
KEY
Sound
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Design Principles (Traditional)
Partition the problem (hirarchical design)
Different abstraction levels: RTL, gate-level, switch-level, transistor-level
Orthogonize concerns
Abstraction vs. implementation
Logic vs. timingConstrain the design space to simplify the design process
Balance between design complexity and performanceE.g., standard-cell methodology
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Integrate the problem (design closure)
Back-annotation, predictability
Balance design metrics
Area/timing/power/signal integrity/reliability
Explore the design space
Balance between design complexity and performance
Platform-based SoC design
Design Principles(State of the Art)
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Design Methodologies (+ business models)
Full-Custom (high effort, leading-edge performance, high-volume)Semi-Custom (strong infrastructure, economical in lower volumes)
ASIC (Application-Specific Integrated Circuit)Standard Cell/Gate Array/Via Programmable/Structured ASIC
FPGASpecial
Analog (custom layout, I/Os and sense amps)Mixed-Signal / RF (unique to each process, no scaling)
System-on-Chip ( System-in-Package)Various components: IP blocks, ASIC, FPGA, memory, uP, RF, etc.Define implementation platform, hardware-software co-designPerformance vs. complexity
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Flow
Schematic Entry Cell
CharacterizationLayout Entry
Standard Cell Library
3-D RLC Modeling Tool
Wire ModelDevice model
Layout rules
r,s, m
Layers
Synthesis Library (Timing/Power/Area)
C-Model Verilog Behavioral
ModelVerilog
Structural RTL
Structural Model
Parasitic Extraction LibraryPlace & Route Library (Ports)
Floorplan
Global LayoutBlock Layout
Floorplan
P & R
Functional
DRC/ERC/LVS
Static/Dynamic Timing w/extractFunctional
Static TimingPower/Area Scan/Testability
Synthesis P & R
Clock Routing/Analysis
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Test Generation
Design Verification Timing Verification
Simulation Floorplanning
Logic PartitioningDie Planning
LogicSynthesis
Logic Design andSimulation
Behavioral Level Design
Global Placement
Detail Placement
Clock Tree Synthesisand Routing
Global Routing
Detail Routing
Power/Ground Stripes, Rings Routing
Extraction and Delay Calc. Timing
Verification
LVSDRCERC
IO Pad Placement
Traditional Taxonomy
Front End
Back End
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Generic Flow Steps
Library preparation
Library data preparation
Design data preparation
Logic design
Specification to RTL
RTL simulation
Hierarchical floorplanning
Synthesis
Formal verification
Gate level simulation
Static timing analysis
Physical design
•Physical floorplanning
•Place and route
•RC extraction
•Formal verification
•Physical verification
•Release to manufacturing
Design for test
Engineering change order
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Library and Design Data
Models and technology data required to execute the design flowPower, timing: ALF, DCL, OLA, .lib, STAMPLayout: LEF, DEF, GDSIIDelays and path timing, parasitics: SDF, GCF, SDC, DSPF, RSPF, SPEF, SPICELayout rules: Dracula, Calibre “deck”
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Scheduling Assignment of each operation to a time slot corresponding to a clock cycle or time interval
Resource allocation Selection of the types of hardware components and the number foreach type to be included in the final implementation
Module binding Assignment of operation to the allocated hardware components
Controller synthesis Design of control style and clocking scheme
Compilation of the input specification language to the internal representation
Parallelism extraction usually via data flow analysis techniques
…
High-Level Synthesis (Behavior RTL)
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Architecture Level Floorplanning
Defines the basic chip layout architectureDefine the standard cell rows and I/O placement locationsPlace RAMs and other macrosSeparate gate array, memory, analog, RF blocksDefine power distribution structures such as rings and stripesAllow space for clock, major buses, etc.
Rules of thumb for cell density are used to initially calculate design size
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Logic Synthesis
Conversion of RTL to gate-level netlist
Targeted to a foundry-specific library
Can be performed hierarchically (block by block)
Timing-drivenClock informationPrimary input arrival times, primary output required timesInput driving cells, output loadingFalse paths, multi-cycle paths
Interconnect delay may be calculated based on a “wireload model” which uses fanout to estimate delay
Clock parameters (insertion delay, skew, jitter, etc.) are assumed to be attainable later in place and route
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Formal Verification
RTL description and gate level netlist are compared to verify functional equivalence, thereby verifying the synthesis results
Formal methodsGraph isomorphismBinary Decision Diagram (BDD)
Emerging technology that supplements the more traditional gate-level simulation approachFV also performed after place-and-route (if gate netlist changes)
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RTL Simulation
RTL code, written in Verilog, VHDL or a combination of both, is simulated to verify functional correctnessTestbenches apply input stimulus to the designSeveral methods are used to verify the outputs
Self-checking testbenches automatically verify output correctness and report mismatchesResults can be stored in a file and compared to previous resultsWaveform displays can be used to interactively verify the outputs
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Gate-Level Simulation
Covers both functionality and timing
Correctness is only as good as the test vectors used
Especially critical for non-synchronous designs, verification of false path and multi-cycle path constraints
Cell timing is included in the simulation models and interconnect delay is passed from the synthesis run
Worst case PVT conditions are used to analyze for setup violations, and best case PVT conditions are used to analyze for hold violations
PVT = Process, Voltage, Temperature
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Static Timing Analysis
Verifies that design operates at desired frequency Implicitly assumes correct timing constraints (!), e.g., boundary conditions
Timing constraints are similar to those used by logic synthesisVerifies setup and hold times at FF inputs; can also check timing from and to PI’s and PO’s; can also check point-to-point delay values (with blocking of pins, etc.)As with gate-level simulation, both best- and worst-case analysis is performedTypically performed on full-chip (not block) basis
May require modified constraints for inter-block issues: multiple clock domains, multi-cycle paths, etc.
For compatibility with timing-driven layout flow, helps to have simple / single set of constraints
Other issues: incremental analysis, …
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Block-Level Physical Floorplanning
Reconcile logical and physical hierarchies
Cells that are interconnected want to be close togetherTake advantage of RTL hierarchyGenerate a physical hierarchyRTL hierarchy = best physical hierarchy
Often bundled within the same cockpit as the place and route tool
Give placement some initial clues to reduce complexity
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Place and Route
Automatically place the standard cellsGenerate clock treesAdd any remaining power bus connectionsRoute clock linesRoute signal interconnectsDesign rule checks on the routes and cell placementsTiming driven tools
Require timing constraints and analysis algorithms similar to those used during the static timing analysis step
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RC(L) Extraction
Calculate resistance and capacitance (and inductance) of interconnects Based on placement of cellsRouting segments
Calculate capacitive (inductive) effects of adjacent segments Extract capacitance between metal segments
RC(L) data transferred back to Static timing analysis (back annotation)Gate level simulationReplaces wire load model used in synthesis
Drive delay calculation, signal integrity analysis (crosstalk, other noise), static timingQ: How do parasitics and noise affect performance?
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Physical Verification
DRC – Design Rule Check Spacing, min dimension rules
LVS – Layout Versus SchematicVerifies that layout and netlist are equivalent at the transistor level
Electrical Rule CheckDangling nets, floating nodes
GDSII (Stream Format)Final merge of layout, routing and placement data for mask production
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Release to Manufacturing
Final edits to the layout are madeMetal fill and metal stress relief rules are checkedManufacturing information such as scribe lanes, seal rings, mask shop data, part numbers, logos and pin 1 identification information for assembly are also addedDRC and LVS are run to verify the correctness of the modified database‘Tapeout’ documentation is prepared prior to release of the GDSII to the foundryPad location information is prepared, typically in a spreadsheetCadence’s Virtuoso is used for custom-manual edits of the mask layersManufacturing steps
generation of maskssilicon processing wafer testingassembly and packagingmanufacturing test
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More Design Metrics and Techniques
AreaCell areaWirelength
TimingGateInterconnect
PowerDynamicStaticLeakage
Signal IntegrityCrosstalk (capacitive, inductive)Supply voltage drop (IR drop, LdI/dt)
ReliabilityVariation (Vdd, thermal, process variation (tox, BEOL))ElectromigrationHot electron effect (SEU)
Cost minimizationSynthesis (technology mapping)Placement, routing
Performance optimization Logic transformation, transistor sizing Buffering, re-routing
Power minimizationGating (sleep transistors), variant VddProcess optimizationDual-Vth
Signal IntegritySizing, net ordering, shieldingP/G design, placement, synthesis
ReliabilityStatistical design optimizationDesign margin
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Wireload Model
Helps delay estimation at synthesis stageGate delay = f(input slew, load cap)Wire cap = f’(fanout number)
EmpiricalDifferent for each technology, library, tool, design, and design stageStatistical (from library), custom (multiple iterations), structural (look at adjacent nets) …
Large deviation remainsRouting obstacles (hard IP blocks, macros, etc.)Routing algorithms/implementations (timing driven, net ordering, details) -10
-5
0
5
10
15
0 5 10 15
Design
% E
st E
rror
2 5 10 15#Pins
Cap
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Interconnect Statistics
What are some implications?
Local Interconnect
Global Interconnect
SLocal = STechnology
SGlobal = SDie
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Constructive Interconnect Prediction
Statistical models have their limitationsCritical paths and the law of small numbers
Statistics properties, e.g., average wirelengthExtreme statistics properties, e.g., critical path length
Implementation detailsRouting congestion, e.g., horizontal effectTiming optimization, e.g., layer assignmentVia blockage, pin accessability, wrong way routing, etc.
Predict by construction (physical synthesis)try a fast (global) router
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Goal: Design Convergence
What must converge?logic, timing, power, SI, reliability in a physical embeddingsupport front-end signoff with a predictable back-end
Achieve Convergence through Predictabilitycorrect by construction (“assume, then enforce”)
constraints and assumptions passed downstream; not much goes upstreamignores concerns via guardbandingseparates concerns as able (e.g., FE logic/timing vs. BE spatialembedding)
construct by correction (“tight loops”)logic-layout unification; synthesis-analysis unification, concurrent optimization
elimination of concernsreduced degrees of freedom, pre-emptive design techniquese.g., power distribution, layer assignment / repeater rules
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Floorplan / Placement
Routing
Prototype delivers accurate physical dataLevels of accuracy
Placement-acknowledgeable synthesis (PKS)Including global routePost-detailed-route (In-Place Optimization, i.e., IPO)
Hierarchical timing budgeting:Chip-level CTS, top-level route and IPO, power analysis and grid designBlock-level synthesis, placement, IPO, routing
“Handoff with enough physical information to ensure correct results”
RTL
Gates
Physical Prototype
Functionality known
Timing / routability known
“Physical Prototyping Philosophy”
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Power IR Drop Analysis
Hierarchical Clock Tree Synthesis
Full Chip Power Planning
Block-Level Optimization
Timing Closure
150psskew
120ps skew50psskew
50psskew
100psskew
130ps skew
PlaceDetailed Trial Route
RC ExtractionDelay Calc / STA
IPO
Full ChipPhysical
Prototype
Partition
“Tape Out Every Day”
Pictures of the Pieces…
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Session Summary
• Technology and interconnect evolutions are the major sets for the physical design
• New materials with respect to scaling are the key issues for thephysical design
• ASIC design flow like front end and backend with necessary inputs from the foundry are the constraints involved in the process
After completing this session, students will be able