1 introduction - texas a&m universitypeople.tamu.edu/~hailiang/lab689/lab1/lab1_manual.pdf ·...

ECEN 489/689 – Lab 1: FIR and IIR Filters

Texas A & M University

1 Introduction The Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters are discrete-time filters

and are the two classes of digital filters. Filters are mainly used to alter the frequency component of the

time signals by either reducing or amplifying the magnitude of certain frequencies.

The output of FIR filters is a weighted sum of past inputs, whereas the output of IIR filters is based on

both past inputs and previous outputs. The IIR is recursive in nature, as its filters use part of the outputs

as inputs. Consequently, IIR is not always computationally stable as FIR. From the computational

perspectives, FIR filters require more coefficients to execute similar filtering operations than the IIR

filters, thus slower in computations than the IIR filters.

1.1 FIR filter

The order of a digital filter is the number of previous inputs used to calculate the current output. For a

FIR filter with 𝑚 orders, the general equation is defined as follows. Figure 1 demonstrates a simple FIR

filter with 𝑚 = 2.

𝑦[𝑛] = ∑ 𝑏𝑘 𝑥[𝑛 − 𝑘]

𝑚

𝑘=0

Figure 1: FIR Filter



1.2 IIR filter

For an IIR filter with 𝑝 and 𝑞 orders, the general equation is defined below. Figure 2 shows a simple IIR

filter with 𝑝 = 1 and 𝑞 = 2.

𝑦[𝑛] = ∑ 𝑏𝑘 𝑥[𝑛 − 𝑘]

𝑝

𝑘=0

− ∑ 𝑎𝑘 𝑦[𝑛 − 𝑘]

𝑞

𝑘=1

Figure 2: IIR Filter

2 Lab Files Preparation Before proceeding, please download base_vivado.zip and Lab1_code.zip from our lab web page

as shown in Figure 3.

Uncompress base_vivado.zip and base_vivado.zip, you will get two folders named as

“base_vivado/” and “lab1_student_code/” respectively.

http://people.tamu.edu/~hailiang/



Figure 3 Files to Download on the Lab Webpage

3 Setup of the ARM Interface

For all the labs in this semester, we need to use the ARM core to send testcases to FPGA. Please note

that both ARM core and FPGA are on the Zybo board.

The steps to set up the ARM interface are described as follows:

a) Open Vivado. (see lab 0 manual for detailed instructions)

b) Once Vivado is launched, click “Open Project” as shown in Figure 4.

Figure 4 Quick Start Window



c) In the popped-up window, click “Home Button”, navigate to the directory where you

extracted the zip files in Section 2 and select “base_vivado/base/base.xpr” as shown in Figure

5. Click “OK” to open the project.

d) Upon clicking, if a window pops up as shown in Figure 6, please proceed with the rest of

this section. Otherwise, you can skip the rest and jump to Section 4.

Figure 5 Open Project Window

Figure 6: Pop-up Window - Project Version

e) Choose “Automatically update to the current version” as shown in Figure 6, then click

“OK”.

f) Once the update is finished, a window will pop up with an option to report IP status. Click

“Report IP Status”.



Figure 7: Pop-up Window - IP Status

g) In the IP Status window, click “Upgrade Selected” as shown in Figure 8 and click “OK”.

Figure 8: IP Status Upgrade

h) A window will pop up asking to enable the IP container. If you are working with a Linux

system, please select “Do Not Convert IP” and click “OK” as shown in Figure 9. For Windows

users, please select “Continue with Core Container Disabled” as shown in Figure 10.

Figure 9: IP Container Window in Linux



Figure 10 IP Container Window in Windows

i) Upon clicking “OK”, a window with Critical Warning Messages will pop up as shown in

Figure 11. Don’t worry, you can ignore them right now. Please click “OK” to close this window.

Figure 11 Critical Messages Window



j) In the Block Design panel, please click “Sources” tab. Expand the design sources

hierarchy by clicking on the “>” symbol at the beginning of each line. Stop expanding until you

see “datatrans_sys_i: datatrans_sys (datatrans_sys.bd) (3)”, as highlighted in Figure 12.

Figure 12 Open Block Design

k) Right click on “datatrans_sys_i: datatrans_sys (datatrans_sys.bd) (3)” and click on

“generate output products” as shown in Figure 13.



Figure 13: Flow Navigator Panel

l) In the popped-up window, select “Global” in the “Synthesis Options” and click on

“Generate” as shown in Figure 14.



Figure 14: Pop-Up Window - Generate Output

Now we have updated the design completely. Please make a copy of the folder “base_vivado/”, as

we will use a copy of this folder each time for labs in this semester.

4 Lab Design

After updating the design configurations, we can proceed to work on the design of FIR and IIR filters.

Please make sure you have a copy of the “base_vivado/” folder before proceeding.

First, we need to add some necessary source files for the design of the filters.

a) Rename the folder “base_vivado/” as “lab1_vivado/”.

b) Launch Vivado and open the project from “lab1_vivado/base/base.xpr” the same way

as shown in Section 3.

c) Open the “Block Design”, navigate to the “Sources” as shown in Figure 12.

d) Right click on “design source->add source” as shown in Figure 15.

Figure 15: Add Source



e) In the pop-up window, select “Add or create design sources” and click “Next” as shown

in Figure 16.

Figure 16 Add Sources Window 1

f) Click on the “+” button and select “Add Files” as shown in Figure 17.

Figure 17: Add Sources Window 2

g) Navigate to the directory where you extracted the zip files in Section 2 and select

“lab1_student_code/FIR.v” and “lab1_student_code/multiply.v” the same way as shown in

Section 3 step c). Click “finish” to complete adding the source file.

Now please go ahead and implement the FIR module in “FIR.v” based on Section 1.

Regarding the implementation of the FIR module, please note:

1. For the calculations done in this lab, you need to use 8 bits, signed, fixed-point numbers, with 4

bits representing the fractional part.



2. It is recommended to first write a multiplier, which facilitates the multiplication of 8 bits

signed fixed-point number.

After you finish “FIR.v”, you need to write a testbench for simulation.

Please add “FIR_tb.v” to your project in the same way as adding “FIR.v”, and write the testbench in

“FIR_tb.v”.

In the testbench for the FIR module, please use the following setup:

i. set a= 0.5, b= -1.5, c= 2.0

ii. set the input of FIR (x) as: -5, -4, -1, 0, 1, 2 ...5, at each clock posedge.

iii. reset your FIR module before inputing the signals.

After implementing the testbench, please do the behavior simulation to verify the functionalities of

your code.

h) Right click on “Simulation” and navigate to “Simulation Settings” on the Flow Navigator

Panel as shown in Figure 18.

Figure 18 Open Simulation Setting



i) In the Simulation Settings window, please change the simulation top module to “FIR_tb”


Figure 19 Top Module Selection Window

j) Click on the “Simulation” tab to modify the simulation runtime as shown in Figure 20. In

this lab, 50ns is enough. Click on “OK” to confirm this setting.



Figure 20: Project Settings

k) In the Flow Navigator Panel, click on “Run Simulation->Run Behavioral simulation”




Figure 21 Run Behavioral Simulation

l) Now you will see the waveforms of the simulation. Please add the waveform to the lab

report.

Next, please design the IIR module according to Section 1 in a similar fashion as done for the FIR

module. Please repeat all the steps in this section with “IIR.v” and “IIR_tb.v”.

For the testbench, please use the following settings:

i. set a=0.5, b=-1.5, c=2.0, d=-1.0.

ii. set the input signal of IIR as: -5, -4, -1, 0, 1, 2 ... 5, at each clock posedge.

5 Questions Please answer the following questions:

1. Are FIR filters inherently stable? Please specify your reasoning.

2. Are IIR filters inherently stable? Please specify your reasoning.

6 Submission Instructions 1. Please only submit 1 zip file, containing 5 code files: “FIR.v”, “IIR.v”, “FIR_tb.v”, “IIR_tb.v”

and “multiply.v”. and 1 PDF report. Name it as “Section#_Lab#_FirstName_LastName.zip”.

2. In the PDF report, please include the following 3 items:

a. Screenshots of the behavioral simulations for the FIR and IIR modules.

b. For each of the screenshot, briefly summarize on how the simulation justifies the

correctness of your design.



c. Answers to the questions in Section 5.

3. Please email the zip file to the TA with subject as “ECEN 489 Lab Report” or “ECEN 689 Lab

Report”.

4. Multiple numbers of submissions are allowed and the latest one will be timed and graded.

1 introduction - texas a&m universitypeople.tamu.edu/~hailiang/lab689/lab1/lab1_manual.pdf ·...

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