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Instruction Sets and Beyond

Computers, Complexity, and Controversy

Brian Blum, Darren DrewryBen Hocking, Gus Scheidt

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OutlinePoints of ClarificationRISC and CISC definedPoints of Attention and ContentionRISC II and the MCF EvaluationMultiple Register SetsThe 432Summary

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Points of Clarification1985 - What is RISC today?RISC – Number of Instructions

RISC:academic .vs. CISC:commercial

RISC I – 31 VAX 11/780 – 303

88000 – 51 Intel 80486 - 235

R4000 - 94 IBM 370/168 – 208

Pyramid - 90 Ridge – 100

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RISC DefinedSingle Cycle OperationLoad / Store DesignHardwired Control (No microcode)Few Instructions and Addressing ModesFixed Instruction FormatMore Compile Time Effort(Split Data and Instruction Cache)

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CISC in ComparisonLarger and more Complex (Insn & Addr)

Multiple Cycle Execution (micro-instructions)

Upward Compatible (w/ Obsolete Insn)

StandardizedMore Hardware (on-chip logic)

Fewer Registers – Unified Cache?

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RISC and CISC: General Points

CISC Built for Language (Assembly)

CISC Built for Memory ConservationCISC Focuses on Standards and CompatibilityRISC Designed for SpeedRISC Simultaneous Access to Code and OperandsRISC Reliance on CompilersWorse: or just Different?

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Two Misconceptions about

RISC and CISC

Implication that discussion is limited to selection of instruction set.

Tradeoffs across various boundaries: architecture / implementation hardware / software compile-time / run-time

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Two Misconceptions about

RISC and CISCImplication that any machine is one or the other.

Machine performance difficult to interpretAbsolute number of instructions is not the only criterion

- compiler / architecture coupling

- non-instruction set design decisions

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Early arguments for RISC

Simpler designs could be realized more quickly

Avoid performance disadvantages of old implementation technology.

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DEC’s MicroVAX-32Qualifies as a CISCVery short development period

Standardization of instruction setRISC can benefit from standardization

Demonstrates importance of assigning function to appropriate implementation level

Microcoding can be a valuable technique

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Misleading RISC ClaimsAmount of design time saved.

Academic vs. commercial design and production

Performance claims.Typical benchmarks avoid metrics of reliability and response time

Use of micro-benchmarks vs. large, heterogeneous benchmarks

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Multiple Register SetsPerformance feature independent of RISC aspect of processorReduce frequency of register saves/restores on procedure callsOverlap register sets for parameter passingMRS impact performance for both RISC and CISC

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Effect of MRS on CISC

Effect of MRS on RISC

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RISC II and the MCF Evaluation

Used by Department of Defense to evaluate life-cycle cost of computersEfficiency defined as: program size; memory bus traffic; canonical processor cyclesVAX (CISC) judged best by MCFRISC II evaluation compared to VAX

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RISC II and the MCF Evaluation

Results of comparisonVAX requires 3.5 times less memory (for program instructions)RISC II has 2.5 times more processor-memory trafficVAX requires fewer cycles than RISC II

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A CISC Example – The 432Object-orientedGeared towards AdaEvery object protected uniformlyVariable length instructions (6-321 bits)On-chip microcodeEvery memory reference is checked

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Problems with the 43210-20 times as slow on low-level benchmarks (such as Hanoi)No on-chip data cachingNo instruction stream literalsNo local registersAda compile performs almost no optimization

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Advantages of the 432ReliabilityCould be faster at more realistic benchmarks (especially ones that use IPCs)

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Lessons from the 432Even with all of the oversights of the 432, it has an important advantage – reliabilityMore realistic benchmarks should be used to compare RISC with CISCCISCs should take advantage of multiple register sets

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ConclusionsWhen comparing RISC with CISC you should use similar hardware organizationsBenefits depend on

Types of programs being runWhether requirements are based on

PerformanceReliabilitySome other factor or set of factors

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And now to thank those who made this all possible!