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Instruction Set Architecture

or“How to talk to computers if

you aren’t in Star Trek”

Announcementsgroupshomework

1st day reading (2.6-2.10)2nd day reading (1.4)** Bring green sheets

Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a 

Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License

.

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What is Computer Architecture?

Computer Architecture =Machine Organization + Instruction Set Architecture

What the machine looks like

How you talk to the machine

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temp = v[k];v[k] = v[k+1];v[k+1] = temp;

lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)

1000110001100010000000000000000100011001111001000000000000010010101100111100100000000000000001010110001100010000000000000100

ALUOP[0:3] <= InstReg[9:11] & MASK

1 2

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Selection

High Level Language

Assembly

Machine Language

Control Signal Spec

A 4 2 1 3

B 4 1 2 3

C 3 1 2 4

D 3 2 1 4

E None of the above

How to speak computer?

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How to Speak ComputerHigh Level Language

Program

Assembly Language Program

Compiler

lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)

Control Signal Spec

Machine Interpretation

ALUOP[0:3] <= InstReg[9:11] & MASK

Machine Language Program

Assembler

1000110001100010000000000000000100011001111001000000000000010010101100111100100000000000000001010110001100010000000000000100

Discuss what classes cover these parts + what they will do in the lab

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The Instruction Set Architecture° is the agreed-upon interface between all the software that runs on the machine and the hardware that executes it.

I/O systemInstr. Set Proc.

CompilerOperating

System

Application

Digital Design

Circuit Design

Instruction Set Architecture

More in Chapter 2

Talk about impact of legacy code.

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The Instruction Set Architecture

• that part of the architecture that is visible to the programmer- opcodes (available instructions)- number and types of registers- instruction formats- storage access, addressing modes- exceptional conditions

You will make this in the lab!

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Which of the following statement is generally true about ISAs?

Select

Statement

A Many models of processors can support one ISA.

B An ISA is unique to one model of processor.

C Every processor supports multiple ISAs.

D Each processor manufacturer has its own unique ISA.

E None of the above

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Examples of ISAs

• Intel 80x86/pentium• VAX• MIPS• SPARC• Alpha AXP• IBM 360• Intel IA-64 (Itanium)• PowerPC• IBM Cell SPE

Main point – many machines map to 1 ISA

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Computer Organization

• Once you have decided on an ISA, you must decide how to design the hardware to execute those programs written in the ISA as fast as possible - (or as cheaply as possible, or using as little

power as possible, …).

• This must be done every time a new implementation of the architecture is released, with typically very different technological constraints.

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Key ISA decisions

• operations how many? which ones

• operands how many? location types how to specify?

• instruction format size how many formats?

y = x + b

operation

source operands

destination operand

how does the computer know what0001 0100 1101 1111means?

(add r1, r2, r5)

You’ve learned ISAs – now we’re focusing on DESIGNING ISAs

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Your architecture supports 16 instructions and 16 registers (0-15). You have fixed width instructions which are 16 bits. How many register operands can you specify (explicitly) in an add instruction?

LAB!!! (Specify vs. have --- implicit)Just have them discuss for ~1 min.

Selection operands

A <= 1

B <= 2

C <= 3

D <= 4

E None of the above

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Your architecture supports 16 instructions and 32 registers (0-31). You have fixed width instructions which are 16 bits. How many register operands can you specify (explicitly) in an add instruction?

LAB!!!Just have them discuss for ~1 min.Also point out impact of 32 instructions and MIPS funct trick

Selection

operands

A <= 1

B <= 2

C <= 3

D <= 4

E None of the above

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Instruction Formats-what does each bit mean?

• Having many different instruction formats...• complicates decoding • uses more instruction bits (to specify the format)

VAX 11 instruction format

Serial decoding

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MIPS Instruction Formats

opcode

opcode

opcode

rs rt rd sa funct

rs rt immediate

target

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Would be really hard to have less than threeMuch more than three makes decoding more serial, again

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MIPS Instruction Formats

opcode

opcode

opcode

rs rt rd sa funct

rs rt immediate

target

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R-type I-type J-type

A addi sw jr

B addi sub jal

C add sw jr

D add sub jal

E None of the above

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Convert this MIPS machine instruction to assembly:

0010 0001 0001 0000 0000 0000 0010 0010

Selection

Instruction

A addi r16, r8, #34

B addi r8, r16, #34

C sub r8, r16, r31

D sub r31, r8, r16

E None of the above

ISOMORPHIC

A

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Convert this MIPS machine instruction to assembly:

1000 1101 0001 0000 0000 0000 0000 1000

Selection

Instruction

A jr r16

B jr r8

C lw r16, 8 (r8)

D lw r8, 8 (r16)

E None of the above

ISOMORPHIC

C

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Convert this MIPS machine instruction to assembly:

0000 0001 0001 0000 1111 1000 0010 0100

Selection

Instruction

A and r31, r8, r16

B and r8, r16, r31

C add r8, r16, r31

D sub r31, r8, r16

E None of the above

A is correct

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Accessing the Operands

There are typically two locations for operands – registers (internal storage - $t0, $a0) and memory. In each column we have which - reg or mem - is better. Which row is correct?

Faster access

Fewer bits to specify

More locations

A Mem Mem Reg

B Mem Reg Mem

C Reg Mem Reg

D Reg Reg Mem

E None of the above

Explain each – but then point out how this leads to load/store

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Load-store architectures

can do:add r1=r2+r3

andload r3, M(address)

forces heavy dependence on registers, which is exactly what you want in today’s CPUs

can’t doadd r1 = r2 + M(address)

- more instructions+ fast implementation

(e.g., easy pipelining)Which is it that we care about?

Why else can’t do address? (hint – fixed instruction length)

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Accumulator:1 address add A acc acc + mem[A]

Stack:0 address add tos tos + next

General Purpose Register:2 address add A B EA(A) EA(A) + EA(B)3 address add A B C EA(A) EA(B) + EA(C)

Load/Store:3 address add Ra Rb Rc Ra Rb + Rc

load Ra Rb Ra mem[Rb]store Ra Rb mem[Rb] Ra

How Many Operands?Basic ISA Classes

Talk through each one – just describe what it is.Not in the text – but on the CD. Be sure tomention stacks often use internal registers

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A = BC+BYStack Acc Reg-Mem Reg-Reg

Push B pushY mult

pushb pushC mult add popA

Load B multY store temp

Load B Mult C add temp store

A

R1=B*Y R2=B*C

A=R1+R2

R1=B R2=C R3=Y

R4=R1*R2 R5=R1*R3 R6=R4+R5

A=R6

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A = BC+XYStack Acc Reg-Mem Reg-Reg

push B Load B R1 = B*C R1 = B

push C Mult C R2 = X*Y R2 = C

push X Store temp A = R1+R2 R3 = X

push Y Load X R4 = Y

Mult Mult Y R5 = R1*R2

Mult Add temp R6 = R3*R4

add Store A R7 = R5+R6

pop A A = R7

In an alternative universe, memory is VERY SLOW to access relative to registers (internal storage). Which ISA would you most likely find in this universe?A. StackB. AccumulatorC. Reg-RegD. Accumulator and Reg-memE. Stack and Accumulator

ISOMORPHIC

Explain that these are sample codes – but the question is in general

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A = BC+XYStack Acc Reg-Mem Reg-Reg

pushB Load B R1 = B*C R1 = B

pushC Mult C R2 = X*Y R2 = C

push X Store temp A = R1+R2 R3 = X

push Y Load X R4 = Y

Mult Mult Y R5 = R1*R2

Mult Add temp R6 = R3*R4

add Store A R7 = R5+R6

pop A A = R7

In an alternative universe – registers (internal storage) are very expensive, and memory is not as slow. Which ISA would you most likely find in this universe?A.StackB.AccumulatorC.Reg-RegD.Reg-Mem and StackE.Both Reg-Reg and Reg-Mem

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Match the addressing mode with its example:

Immediate

Register Direct

Memory Direct

Register Indirect

Base + displacement

A 1 2 3 4 5

B 3 4 5 1 2

C 3 1 2 4 5

D 2 4 5 1 3

E None of the above

Option Example/description

1 Memory[R7]

2 R7

3 1000

4 Memory[R7 + 1000]

5 Memory[1000]

I’m not a big fan of memorizing “terms” but these are used frequently enough that you need to

know them.

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MIPS addressing modes give flexibility

immediate

add $1, $2, #35

base + displacementlw $1, disp($2)

OP rs rt immediate

rtrs

immediate

(R1 = M[R2 + disp])

Get reg ind and absolute for free

register indirect disp/immediate = 0absolute (rs) = 0

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Memory Organization• Viewed as a large, single-dimension array,

with an address.• A memory address is an index into the array• “______________" means that the index points to

a byte of memory.

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

Byte addressing

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Processor X is 16 bit byte-addressable. If you have a pointer at address 0000 0000 0000 1000 and you increment it by one (0000 0000 0000 1001). What does the new pointer (0000 0000 0000 1001) point to, relative to the original pointer (0000 0000 0000 1000)?

A) The next word in memory

B) The next byte in memory

C) Either the next word or byte – depends on if you use that address for a load byte or load word

D) Pointers are a high level construct – they don’t make sense pointing to raw memory addresses.

E) None of the above.

ISOMORPHIC

B is correct

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Processor Y is 14 bit word-addressable. If you have a pointer at address 00 0000 0000 1000 and you increment it by one (00 0000 0000 1001). What does the new pointer (00 0000 0000 1001) point to, relative to the original pointer (00 0000 0000 1000)?

A) The next word in memory

B) The next byte in memory

C) Either the next word or byte – depends on if you use that address for a load byte or load word

D) Pointers are a high level construct – they don’t make sense pointing to raw memory addresses.

E) None of the above.

ISOMORPHIC

A correct

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Reading Quiz Variant

• You have the following code in C:for(int i = 0; i< 10;i++){A[i]=i;}Where A is an array of shorts (16 bit/half-word).Let's suppose that the base address of A is in $s0 and has the value of 1000 (base ten).What byte address(es) correspond to A[5]?

Selection

Byte(s)

A 1005

B 1010

C 1005-1006

D 1010-1011

E None of the aboveByte word addressing can be problematic to think about – the book

Likes to jump around between them. I’ll try to be consistent in class.

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Memory Organization• Bytes are nice, but most data items use larger

"words"• For MIPS, a word is 32 bits or 4 bytes.

• 232 bytes with byte addresses from 0 to 2^32-1• 230 words with byte addresses 0, 4, 8, ... 2^32-4• Words are aligned

i.e., what are the least 2 significant bits of a word address?

0

4

8

12

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Registers hold 32 bits of data

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MIPS Review

All our processors will be mips based – so just wanna go over it.

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The MIPS ISA, so far

• fixed 32-bit instructions• 3 instruction formats• 3-operand, load-store architecture• 32 general-purpose registers (integer, floating

point)- R0 always equals 0.

• 2 special-purpose integer registers, HI and LO, because multiply and divide produce more than 32 bits.

• registers are 32-bits wide (word)• register, immediate, and base+displacement

addressing modes

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What’s left

• which instructions?• odds and ends

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Which instructions?

• arithmetic• logical• data transfer• conditional branch• unconditional jump

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Which instructions (integer)

• arithmetic- add, subtract, multiply, divide

• logical- and, or, shift left, shift right

• data transfer- load word, store word

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Control Flow

• Jumps• Procedure call (jump subroutine)• Conditional Branch

- Used to implement, for example, if-then-else logic, loops, etc.

• A conditional branch must specify two things- Condition under which the branch is taken - Location that the branch jumps to if taken

(target)

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What form of addressing is used by branch instructions?

Addressing Mode

Best explanation

A Absolute Branch instructions require a full 32-bit address to know the branch target

B Absolute A 32-bit immediate gives us enough bits to specify a full address

C Relative Branches tend to be backward branches which require a negative immediate

D Relative Branch targets tend to be close to the branch instruction

E Register Indirect

We can load a 32 bit full address in a register – which lets us branch anywhere

Mention C isn’t incorrect – and branches tend to be backward, but if they weren’t close – we couldn’t do relative

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slt $t2, $t0, $t1 bne $t2, $zero, false addi $t0, $t0, 1false: next instruction

A

High level code often has code like this:if(i<j) { i++;}Assume $t0 has i and $t1 has j. (slt rd, rs, rt does: R[rd]=1 if R[rs]<R[rt], else R[rd] = 0.) Which of the following is the correct translation of the above code to MIPS assembly (recall $zero is always 0):

slt $t2, $t1, $t0 bne $t2, $zero, truetrue: addi $t0, $t0, 1 next instruction

B C

slt $t2, $t1, $t0 beq $t2, $zero, false addi $t0, $t0, 1false: next instruction

D

slt $t2, $t0, $t1 beq $t2, $zero, false addi $t0, $t0, 1false: next instruction

E

None of the above

Mention useless bne in BD is correct

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Jump instructions have a 26-bit immediate. Since an address must be word aligned we can always use 00 as the lowest bits. To make a 32 bit address, what are the top 4 bits?

Top 4 bits

Why (best answer)

A 0000 All instructions are at low addresses

B pc[3:0] Low order bits of the current program counter best represent the high bits of the new pc

C pc[31:28] High order bits of the current program counter since most jumps go to (relatively) nearby instructions

D pc[31:28] All instructions must be in the same 256MB segment.

E None of the above

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What is the most common use of a jal instruction and why?

Most common use

Best answer

A Procedure call

Jal stores the next instruction in your current function so the called function knows where to return to.

B Procedure call

Jal enables a long jump and most procedures are a fairly long distance away

C If/else Jal lets you go to the if while storing pc+4 (else)

D If/else Jal enables a long branch and most if statements are a fairly long distance away

E None of the above

Mention jr

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To summarize:MIPS operands

Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform

32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is

$fp, $sp, $ra, $at reserved for the assembler to handle large constants.

Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so

230 memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays,words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

MIPS assembly language

Category Instruction Example Meaning Commentsadd add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants

load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register

store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register

store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memoryload upper immediate

lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100

Equal test; PC-relative branch

Conditional

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100

Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0

Compare less than; for beq, bne

set less than immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return

tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

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Review -- Instruction Execution in a CPUMemory2

1000010004

80000

address10:

1000110001000011010011100010000000000000011000010010100000100000

00000000000000000000000000111001

Registers10

R0R1R2R3R4R5...

036600004519812...

ProgramCounter

10000

Instruction Buffer

op rtrs rd shamt

immediate/disp

in1 in2

outALUoperation Load/Store

Unit

addr

data

CPU

57

Watch lw typoOn cheat sheet

What happens when you execute the next instruction?

A. PC=10004B. R[R3] = 80000C. R[R3] = 57D. Both A and BE. Both A and C

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Review -- Instruction Execution in a CPUMemory2

1000010004

80000

address10:

1000110001000011010011100010000000000000011000010010100000100000

00000000000000000000000000111001

Registers10

R0R1R2R3R4R5...

036600004519812...

ProgramCounter

10000

Instruction Buffer

op rtrs rd shamt

immediate/disp

in1 in2

outALUoperation Load/Store

Unit

addr

data

CPUUPDATE! 10004 and R3=57

What happens when you execute the next instruction?

A. PC=10008B. R[R5] = 93C. R[R3] = 48D. Both A and BE. Both A and C

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Key Points

• MIPS is a general-purpose register, load-store, fixed-instruction-length architecture.

• MIPS is optimized for fast pipelined performance, not for low instruction count

• Historic architectures favored code size over parallelism.

• MIPS most complex addressing mode, for both branches and loads/stores is base + displacement.