1 Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs Li Shang and Niraj K.Jha Proceedings of the 15th International Conference on VLSI Design(VLSID 02) Presented by Chun-Hsain, Hwang 2005/12/22 2 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 3 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 4 Introduction HW/SW co-synthesis system have to satisfy multi-objective goals, such as performance, price and power. Three key steps in HW/SW co- synthesis systems (NP-complete) Allocation Assignment Scheduling 5 Introduction (cont) With the success of battery-based personal computing devices and wireless communication systems, low power has become a key issue in system design On-line reconfiguration not only introduces a delay in task execution, but also a power overhead 6 Outline Introduction Definitions of the Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 7 Definitions of the Co-Synthesis Systems Input specifications Task Graphs An embedded system containing multiple task graphs with different periods is called multi-rate 8 Definitions of the Co-Synthesis Systems (cont) Resource library model general-purpose processor dynamically reconfigurable FPGAs communication links memories Dynamically reconfigurable FPGAs One-dimensional reconfiguration model The task has a specific configuration pattern for each frame A task may reutilize a configuration pattern left behind by earlier task Multiple frames can only be reconfigured one by one 9 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 10 HW/SW Co-Synthesis Overview 11 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 12 Scheduling Algorithm Scheduling for dynamically reconfigurable FPGAs is two-dimensional problem time and space domains Scheduling sequence: at each scheduling point, multiple ready task may reside in the candidate pool Location assignment policy: assigning a task to a different location not only influences the current task, but may also impact the tasks scheduled either after or before it 13 Motivational Example Task 1_0 and 3_1 are assumed to have the same configuration patterns The reconfiguration time for each frame is 3.4 units. The communication times of C3_1 and C2_0 are 15 and 10 units. The communication time between two tasks assigned to the same PE is zero 14 Motivational Example 15 Scheduling approach I Static slack-based priority P i =-(T_lasted_ready i -T_earliest_ready i ) Conduct a topological search of task graphs based on as-soon-as-possible (ASAP) and as-late-as-possible (ALAP) scheduling Configuration patterns are allowed to be loaded into FPGA before the task ready time Configuration patterns left by earlier tasks can be utilized by later tasks 16 Scheduling approach I (cont) 17 Scheduling approach II The order of scheduling tasks is determined dynamically by task priorities, which consider both real- time constrains and reconfiguration overhead information 18 Scheduling approach II (cont) 19 Scheduling Result Since reconfiguration itself consumes a significant amount of power, minimizing the reconfiguration overhead is important for reducing system power consumption Solutions that cannot satisfy real-time constrains necessitate faster PEs 20 Analysis of Scheduling Approach - Scheduling Sequence Static slack-based priorities (approach I) are commonly used to order tasks for scheduling on processor In the static slack-based priority approach, tasks along the critical path of one task graph may always be scheduled before tasks in other task graphs 21 Analysis of Scheduling Approach - Scheduling Sequence (cont) Propose a dynamical priority based approach, which dynamically updates the task priority For each task i in the candidate pool that has the same patterns as taskj, which has been remove from the candidate pool for scheduling on the FPGA, the value of inner-task reconfiguration time is zero. 22 Analysis of Scheduling Approach Location Assignment Policy Reconfiguration prefetch Configuration pattern reutilization Eviction candidate Fitting policy Slack time reutilization 23 Pseudo-code of the scheduling algorithm 24 A Task Scheduling Sample 25 Scheduling Algorithm Determine the reconfiguration sequence of frames The idea is that if the duration between the reconfiguration slot start time and the task ready time is short, reconfiguration of the corresponding frame needs to be scheduled first 26 Scheduling Algorithm (cont) In order to reduce the reconfiguration overhead: schedule_back() schedule_front() 27 A Task Scheduling Sample 28 Scheduling Algorithm (cont) A priority needs to be defined to determine the scheduling order for all the needed frames in order to tackle the interrelationship among them 29 Candidate position priority calculation 30 Scheduling Algorithms for Resources 31 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 32 Experimental Setup The system is implemented in C++ using standard template library (STL) The reconfigurable FPGA models are based on Xilinx Virtex-E The task graphs, which are input to co- synthesis system, are generated by TGFF All the experiments were performed on a Pentium-III 667MHz PC (512MB memory) running Linux OS 33 FPGA scheduling results 34 Hardware/software co-synthesis results 35 Experimental Results (cont) 36 Outline Introduction Definitions of Co-synthesis Systems HW/SW Co-Synthesis Overflow Scheduling Algorithm Experimental Results Conclusions 37 Conclusions Present a multi-objective hardware/software co-synthesis system for real-time distributed embedded systems Propose a two-dimensional multi- rate cyclic scheduling algorithm Not only minimizes schedule length, but also significantly reduces reconfiguration power 38 Virtex-E vs. Virtex-II Pro