1 episode iii in our multiprocessing miniseries. relaxed memory models. what i really wanted here...
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Episode III in our multiprocessing miniseries.
Relaxed memory models.
What I really wanted here was an elephant with sunglasses relaxing
On a beach, but I couldn’t find one.
Relaxed Memory Models
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P P P P P P
m
Sequential Consistency =arbitrary order-preserving interleavingof memory references of sequential programs
SC is easy to understand but architects and compiler writers want to violate it for performance
Mark Hill written a paper which essentially says “why break your back for20%”. Actually people are out there breaking their backs for 1% in architecture these days.
Sequential Consistency: A Memory Model
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m
Architectural optimizations that are correct for uniprocessors often result in a new memory model for multiprocessors
Optimizations & Memory Models
Memory
Processor- Memory Interface
Load queue
Pushout buffers
DataCacheCPU
load/store buffers
This means that we are relaxing the ordering or relaxing atomicity.
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Relaxed Models
• What orderings among reads and writes performed by a single processor are preserved by the model?
– R → R, R → W, W → W, W → R
dependence if they are to the same address
• If there is a dependence, then program semantics demand that operations be ordered
• If there is no dependence, the memory consistency model determines what orders must be preserved
– Relaxed model may allow an operation executed later to complete first
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Memory Fences & Weak Memory Models
Processors with relaxed or weak memory models need memory fence instructions to force serialization of memory accesses
– In SC there is an implicit fence at each
memory operation
Processors with relaxed memory models: Sparc V8 (TSO, PSO): Membar PowerPC (WO):Sync, EIEIO
Memory fences are expensive operations, however, one pays for serialization only when it is required
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Ensures that tail pointer is not updated before
X has been stored.
Ensures that R is not loaded before x has been stored.
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Data-Race Free Programs(a.k.a. Properly Synchronized Programs)
Process 1
... Acquire(mutex);
< critical section > Relea
se(mutex);
Process 2
... Acquire(mutex);
< critical section > Rel
ease(mutex);
Synchronization variables (e.g., mutex) are separate from data variables
Accesses to writable shared data variables are protected in c
ritical regions⇒ no data races except for locks
(Formal definition is elusive)
In general, it cannot be proven if a program is data- race free.
Nondeterminator.
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Processor should not speculate or prefetch across fences.
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Total Store Order (TSO)IBM370, DECVAX
• Eliminates the order W(a) → R(b)
• Advantage?
a ≠ b
Allows the buffering of writes with bypassing by reads, which occurs whenever the
processor allows a read to proceed before it guarantees that
an earlier write by the processor has been seen by all the other processors.
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TSO vs. SC
Initially x = old, y = old
Processor P1 Processor P2
x = new; y = new; y_copy = y; x_copy = x;
Under SC what values can x_copy and y_copy get ?
Under TSO what values can x_copy and y_copy get ?
TSO both can get old values.
SC at least one has to get the value of new.
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Allows pipelining or overlapping of write operations, rather than
Forcing one operation to complete before another.
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Non-blocking reads, doesn’t help too much.
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Release ConsistencyAlpha, MIPS
• Read/write that precedes acquire need not complete before acquire, and read/write that follows a release need not wait for the release
Weakest of the memory models used these days.
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Release Consistency Example
Initially data = old
Processor P1 Processor P2
data = new; while(flag != SET) { }
flag = SET; data_copy = data;
How do we ensure that data_copy is always set to new ?
Membar Store Store Membar Load Load
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CRF: Fences
Instructions can be reordered except for
• Data dependence
• StoreL(a,v); Commit(a);
• Reconcile(a); LoadL(a);
Reconcile(a1);
LoadL(a1);
Fencerr (a1, a2)
Reconcile(a2);
LoadL(a2);Fencewr; Fencerw; Fenceww;
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Translating SC into CRF
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