1 csce 932, spring 2007 test generation for combinational logic
TRANSCRIPT
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CSCE 932, Spring 2007
Test Generation for Combinational Logic
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Outline
Fundamental ConceptsStructure vs. FunctionBoolean Difference
Test Generation AlgorithmsMulti-valued AlgebrasComplexity of test generation PODEMBoolean-Satisfiability Based
Summary
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Origins of Stuck-Faults
Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faultsSeshu & Freeman (1962) – Use of stuck-faults for parallel fault simulationPoage (1963) – Theoretical analysis of stuck-at faults
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Functional vs. Structural ATPG
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Carry Circuit
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Functional vs. Structural (Contd)
Functional ATPG – exhaustive set of tests for 129 inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patternsUsing 1 GHz ATE, would take 2.15 x 1022 years
Structural test:No redundant adder hardware, 64 bit slicesEach with 27 faults (using fault equivalence)At most 64 x 27 = 1728 faults (tests)Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %
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Boolean Difference
I will illustrate the concepts in class, along with illustrative examples.
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Multi-valued Algebras
Symbol Meaning
Good M/c
Failing M/c
D 1/0 1 0
Roth’sAlgebra
D 0/1 0 1
0 0/0 0 0
1 1/1 1 1
X X/X X X
G0 0/X 0 X
Muth’sAddition
s
G1 1/X 1 X
F0 X/0 X 0
F1 X/1 X 1
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Roth’s and Muth’s Higher-Order Algebras
Simultaneously represent two machines: Good circuit machine (1st value)Bad circuit machine (2nd value)
Better to represent both in the algebra:Need only 1 pass of ATPG to solve bothGood machine values that preclude bad machine values become obvious sooner & vice versa
Needed for complete ATPG:Combinational: Multi-path sensitization, Roth AlgebraSequential: Muth Algebra -- good and bad machines may have different initial values due to fault
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Path Sensitization Method Circuit Example
Fault SensitizationFault PropagationLine Justification
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Path Sensitization Method Circuit Example
Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i
10
D
D1
1
1DD
D
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Path Sensitization Method Circuit Example
Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears
1
DD D
DD
1
1
1
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Path Sensitization Method Circuit Example
Final try: path g – i – j – k – L – test found!
0
D D D
1 DD
1
0
1
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Complexity of Test Generation
The primary source of complexity is that the number of sensitizable paths grow exponentially with the circuit size and in the worst case the algorithm may have to search all of them for a solution.
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Algorithmic Complexity of Test Generation
Algorithmic complexity refers to the worst-case-time behavior in terms of problem parameter(s)For combinational test generation, circuit size (in number of lines) is used as the parameter.Sahni and Ibarra* showed NP-completeness of test generation by reducing a well NP-complete problem (3-SAT) to the combinational test-generation problem.
O.H. Ibarra and S. K. Sahni, “Polynomially Complete Fault Detection Problems,” IEEE Trans.Computers, March 1975, pp.242-249/
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PODEM Test Generation Algorithm
Structure-based and fault oriented
Signal values are explicitly assigned at the PIs
only; other values are computed by implication
Eliminates D-algorithm’s need to justify internal
signals
Backtracks at PIs only when a contradiction occurs
Many extensions exist with more complex
heuristics, e.g. the FAN algorithm
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PODEM Decision Tree
X X
X
~
~
B=1
D=0 D=1
A=1A=0
A=0A=1
Success, Halt
~
X
Unused assignments
Back up, no test possible
No remaining choicesC=1
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PODEM Algorithm
Initialize all signal values to unknownBranchRepeatImplyIf(fault is detected) then exit loopif(no test possible with current ass’t) then
exit Bound else BranchForever
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&=1
&=1
=1
&
&
&&
=1
x1
x2
x3x4x5
z1
z2
SA0 Fault
Assume sequential input selection, applying 1 before 0
PODEM Example
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
x2
x3x4x5
z1
z2
SA0 Fault
=0
1
Step 1: Set x1 = 1 and imply
D
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
X2
x3x4
x5
z1
z2
SA0 Fault
Step 2: Set x2 = 1 and imply
=0
1
= 1
D
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
X2
x3x4
x5
z1
z2
SA0 Fault=
01
= 1
D
= 10
1
01
Step 3: Set x3 = 1 and imply. Fault cannot be detected atz1 but detection at z2 is still possible.
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
X2
x3x4
x5
z1
z2
SA0 Fault=
01
= 1
D
= 10
1
01
Step 4: Set x4 = 1 and imply. Now the fault cannot be detected at either output hence need to backtrack.
= 1
0
1
0
1
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
X2
x3x4
x5
z1
z2
SA0 Fault=
01
= 1
D
= 10
1
01
Step 4: Set x4 = 1 and imply. Now the fault cannot be detected at either output hence need to backtrack.
= 1
0
1
0
1
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PODEM Example
&=1
&=1
=1
&
&
&&
=1
x1
X2
x3x4
x5
z1
z2
SA0 Fault=
01
= 1
D
= 10
1
01
Step 5 (backtrack): Set x4 = 0 and imply. Now thefault is detected at output z2.
= 0
1
D’
D’ D
D’
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Podem HeuristicsSeveral heuristics are used for speedup
Line objectivesSelecting alternatives in back-tracingSelecting alternatives for extending D-path to an observable output
Many heuristics are based on the controllability and absorbability estimates for lines in the circuit
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Boolean SatisfiabilityGiven a Boolean formula in CNF (product-of-sums), determine if there is an assignment of variable values that satisfies the formula.Special Cases:
2-SAT: CNF clauses have at most 2 literals3-SAT: CNF clauses have at most 3 literals
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Test Generation as a Boolean Satisfiability Problem
1. Gate Representation (AND Gate Example):
Express C = AB in conjunctive normal form (CNF). The formula is true iff the values of A, B, and C are consistent with the AND function.
2. Circuit Representation: Logically AND the CNF for each gate. The resulting formula, in CNF, is true all the signal values are consistent.
3. Construct the Boolean difference circuit for the target fault (next slide).
4. Represent the Boolean difference circuit by its CNF formula and set the signal at its output to 1. An input assignment is a test iff it satisfies the CNF.
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The Boolean Difference Circuit
Set F=1 in the circuit CNF. Any satisfying solution to the resulting formula must be a test for the fault.
Circuit UnderTest (CUT)
CUT with Target Fault
Inserted
F
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Example
For line F sa-1 set F=0, F*=1, and H=1. Then the resulting formula is satisfied by ABC = 0X0 and X01 which are the two tests for the fault.
g1
g2g3
g5g4
A
BC
C1
C2
DE
F
G
g1
g3g5*
g4
A
BC
C1
g1 g2 g3 g4 g5 g5* g6
C’+C1 C+C1’ C’+C2 C+C2”
C1+D C1’+D’
A’+D’+E A+E’ D+E’
B’+c2’+F B+F’ C2+F’
E’+G F’+G E+F+G’
E’+G* F*’+G* E+F*+G*’
G+G*’+H G’+G*+H G+G*+H’ G’+G*’+H’
C2
DE
FG*
g2
Hg6
F*
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SAT SolversThe DPLL Algorithm: Davis-Putnam [JACM 7(1) 1960], and Davis-Putnam-Longemann-Loveland [CACM May 1962] The line justification step in PODEM [Goel, IEEE TC, March 1981] can also be used as a SAT solverThe DPLL algorithm has been enhanced in chaff [Moskewicz et al. DAC 2001] and implemented in mchaff and zchaff, the latter being the most widely known and used. Other SAT solvers to note:
GRASP [Marques-Silva and Sakalla, IEEE TC, May 1999], SATO [Zhang, Int. Conf. Automated Deduction, 1997]
Generally, the DPLL enhancements try to improve on the original backtrack algorithm through careful engineering of all aspects of the search
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Basic Davis-Putnam (DP) Backtrack Search for SAT
decide() selects an unassigned variable and gives it a value.bcp() identifies any variable assignments required by the current variable state to satisfy f.resolveConflict() undoes implied assignment and backtracks to try the next variable assignment
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2-SAT Based SAT SolvingThe boolean satisfiability problem for
binary clauses (2-SAT) is polynomially solvable while 3-SAT and the general satisfiability problem is NP-complete.
This suggests another heuristic of solving the satisfiability problem: generate and test solutions for the binary clauses against the whole CNF until success.
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B
A’
A
B’
A B
C
D EA B
C
D E
Analyzing 2-SAT Constraints Graphically
Step 1 (Construct the implication graph): For each binary clause (A+B) create the subgraph:
Step 2: Find the transitive closure graph (TC) of the implication graph.
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Analyzing 2-SAT Constraints Graphically
Step 3 (Analyze the transitive-closure graph):(Contradiction): Both (C’,C) and (C,C’) are in the TC. This implies C must be true and false at the same time. This would occur if the fault was redundant (untestable).
(Fixed Signal Values): Only one of (C’,C) and (C,C’) is in the TC this implies C has a fixed binary value.
(Identical Signal Values): If both (A’,B) and (A,B’) are in the TC then literals A and B must assume identical signal values.
(Excluded Signal Value): If (A’,B) is in the TC and no other edges occur between these four literals, then the combination AB=10 is excluded from the solution.
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Transitive Closure Test Generation Algorithm (TRAN)*
In TRAN test generation is carried out entirely by dynamically updating the TC after each variable assignment and analyzing it.
* See, Chakradhar et al. IEEE TCAD, June 1993 and Larrabee, TCAD, January 1992.
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TRAN Flow Chart
Circuit withFault
TransitiveClosure
Contradiction?
UnassignedVariables?
Assign valueto a variable
TransitiveClosure
RedundantFault
Contradiction?Both values
tried?
UnassignedVariables?
RedundantFault
Assign next valueto a variable
Y
N
Test Found
N
Y
N Y
NY
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History of Algorithm Speedups
Algorithm Est. speedup Year
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 1988
Waicukauski et al.
2189 1990
EST 8765 1991
TRAN 3005 1993
Recursive Learning
485 1995
Tafertshofer et al.
25057 1997Part of Automatic Test Pattern Generation (ATPG) System
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Test Generation for Sequential-Circuits
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Time-Frame ExpansionCOMBLOGIC C
M
COMBLOGIC C
COMBLOGIC C
COMBLOGIC CM M
Clock Cycle 0 Clock Cycle 1 Clock Cycle 2
InitialState
FinalState
M
Iterative Logic Array (ILA) Representation
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Time-Frame Expansion Based Test Generation
0 1 0 N-2 -1-M
Time Frames for Fault Excitation and Propagation
Time Frames for StateJustification
The sequential test generation problem is reduced to combinational test generation but for multiple time frames and multiple fault instances.
Single Observation:This approach guarantees that by observing the primaryoutputs at the final time frame, the fault will be detected.
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Test Generation Example: 5 valued logic
=1
& &
&
=1
& &
&
Time frame 0Time frame -1
11x
12x
1y
01x
02x
0y
1z 0z
1Y 0Y
SA0
SA0 1
01
1
00
1
1Conflict
D
D
D
D
D
1
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Test Generation Example: 9 valued logic
=1
& &
&
=1
& &
&
Time frame 0Time frame -1
11x
12x
1y
01x
02x
0y
1z 0z
1Y 0Y
SA0 SA0 1/0
1/x
0/1
0/x 1/00/x1/1
1/x
1/x0/x
1/x
1/x
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The “Reset Problem”
Synchronizing sequence is a generalized reset for FSMs. It reduces the total uncertainty of the initial state to a known fixed state.However, the reduction in ambiguity for some FSMs may not be fast enough to find the synchronizing sequence by algorithmic means using 3-valued logic.Consider the example machine (from Miczo’s text, p. 273) on the next page
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Miczo’s Example Machine
Input x:
0 1
S0 S1 S1
S1 S3 S2
S2 S1 S3
S3 S0 S0
It can be verified that (0,1,0,1,0) is the shortest synchronizing sequence
Consider, encoding the states using twoFFs. What is the state ambiguity afterthe first 0?
What does it say about the complexityof sequential ATPG using 3-valuealgebra?
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Multiple Observation Times*
Some faults may only be testable by observing outputs at multiple time frames during the application of the test sequence. Consider the following example from the paper:
* Pomeranz and Reddy, IEEE TC, May 1992
Input x:
0 1
A B,0 C,0
B C/B,0 B,1
C D/A,1 A,1
D A,1 D,0
• Verify that the machine hasno reset sequence.• If the initial state is unknownthe output can be either 0 or 1 inevery timeframe.• Hence, single observation time does not work.
Note: The fault shown is functional affecting state transitions for 0-input in states B and C,as shown.
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PairTime Units for Observation
1 2 3 4
A/A + +
A/B + +
A/C + + +
A/D + + +
B/A + +
B/B + +
B/C + + +
B/D + + +
C/A + +
C/B + +
C/C +
C/D +
D/A + +
D/B + +
D/C +
D/D +
Observation Times for Test Sequence (0000)
No single observation time covers all the pairsHowever, if machine outputs are observed at both time units 2 and 4, all pairs are covered.Hence, independent of the starting state, the fault can be detected only if at least two observations are made.
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Distinguishing Sequence in Finite State Machine
Assume two copies of the same FSM, one starts in state s and the other in state t.A distinguishing sequence for states s and t is any input sequence that produces a different output.
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Example
A B
D C
0/0
1/0
0/0
1/1
0/1
1/1
0/11/1
What is the shortest distinguishingsequence for states C and D?
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Product Machine
Common inputsProduct number of statesSTG derived from component STGsRepresents behavior of concurrent operation of M1 and M2.
M1
M2
ProductMachine
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Test as a Distinguishing Sequence of a Product Machine
Good Machine
Faulty Machine
!=
Assume the good and faulty machines start in state s and tThe test is any distinguishing of the product machineIf the good and faulty machines do not have a reset state, it may not be possible to find a test with single observation.
Product Machine
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Sequential Circuit ATPGSimulation-Based Methods
Contrast with target-fault-based:Main loop starts with an initial sequence of test vectors (could be random or otherwise)The sequence is progressively modified and augmented based on simulation based evaluation of the testability of the current set, until the desired level of coverage is reached.IBM’s SOFTG* is an early example of this approach.
* T. J. Snethen, “Simulator-Oriented Fault Test Generator,” Proc. DAC, 1977, pp. 88-93.
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Other Simulation-Based Methods
ContestDirected searchCost functions
Genetic AlgorithmsSpectral MethodsSummary
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Fault-Simulation Based Test Generation*
Faultsimulator
Vector source:Functional (test-bench),Heuristic (walking 1, etc.),Weighted random,random
Faultlist
Testvectors
New faultsdetected?
Stoppingcriteria (faultcoverage, CPUtime limit, etc.)
satisfied?
Stop
Updatefaultlist
Appendvectors
Restorecircuitstate
Generatenew trial
vectors
Yes No
Yes
No
Trial vectors
* See, Agrawal, et al., IEEE-TCAD, 1989
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Sequential ATPG SummaryCombinational ATPG algorithms are extended:
Time-frame expansion unrolls time as combinational arrayJustification via backward time
Nine-valued logic systemUnlike combinational ATPG:
Completeness not guaranteed using 3-valued logic simulationSome circuits may require 9-valued D-algebra 5-valued is not enoughSimulation-based ATPG may be a more attractive alternative
Cycle-free circuits (where sequential elements don’t form a cycle through combinational logic) are much easier to test than cyclic circuits
Require at most dseq time-framesAlways initializable
DFT a must for large circuits: Either full or partial scan.